MS51
Nov. 28, 2019
Page
401
of 491
Rev 1.00
MS51
32K
SE
RIES
TE
CHNICAL RE
F
EREN
CE MA
N
UAL
SCnETURD1
–SC ETU Rate Divider Register
Register
SFR Address
Reset Value
SC0ETURD1
DCH, Page 2
0011_0001 b
SC1ETURD1
E4H, Page 2
0011_0001 b
SC2ETURD1
ECH, Page 2
0011_0001 b
7
6
5
4
3
2
1
0
-
SCDIV[2:0]
ETURDIV[11:8]
-
R/W
R/W
Bit
Name
Description
7
-
Reserved
6:4
SCDIV
[2:0]
SC clock divider
000 = F
SC
is F
SYS
/1.
001 = F
SC
is F
SYS
/2.
010 = F
SC
is F
SYS
/4.
011 = F
SC
is F
SYS
/8. (By default.)
100 = F
SC
is F
SYS
/16.
101 = F
SC
is F
SYS
/16.
110 = F
SC
is F
SYS
/16.
111 = F
SC
is F
SYS
/16.
Note:
that the F
SC
clock should be 1Mhz ~ 5Mhz for ISO/IEC 7816-3 standard
3:0
ETURDIV
[11:8]
MSB bits of ETU Rate Divider
The field indicates the MSB of clock rate divider.
The real ETU is ETURDIV[11:0] + 1.
Note 1:
ETURDIV[11:0] must be greater than 0x004.
Note 2:
SCnETURD0 has to program first, then SCnETUDR1 .
