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Nuvoton NuMicro MS51 32K Series Technical Reference Manual Download Page 170

MS51

 

 

Nov. 28, 2019 

Page 

170

 of 491 

Rev 1.00

 

MS51 

32K

 SE
RIES

 TE

CHNICAL RE

F

EREN

CE MA

N

UAL

 

 

AINDIDS0 

– ADC Channel Digital Input Disconnect 

 

Register 

SFR Address 

Reset Value 

AINDIDS0 

F6H, Page 0 

 0000_0000 b 

 

7 

6 

5 

4 

3 

2 

1 

0 

P11DIDS 

P03DIDS 

P04DIDS 

P05DIDS 

P06DIDS 

P07DIDS 

P30DIDS 

P17DIDS 

R/W 

R/W 

R/W 

R/W 

R/W 

R/W 

R/W 

R/W 

 

Bit 

Name 

Description 

n 

PnnDIDS 

ADC Channel digital input disable 

0 = ADC channel n digital input Enabled. 

1 = ADC channel n digital input Disabled. ADC channel n is read always 0. 

Summary of Contents for NuMicro MS51 32K Series

Page 1: ...the exclusive intellectual property of Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton Nuvoton is providing this document only for reference purposes of NuM...

Page 2: ...kage Pin Diagram 20 4 2 MS51 32K Series Pin Description 21 5 BLOCK DIAGRAM 25 5 1 MS51 32K Series Block Diagram 25 6 FUNCTIONAL DESCRIPTION 26 6 1 Memory Organization 26 6 1 1 Overview 26 6 1 2 Progra...

Page 3: ...Reset Timer 354 6 7 3 General Purpose Timer 355 6 7 4 Control Registers of Watchdog Timer 357 6 8 Self Wake Up Timer WKT 359 6 8 1 Overview 359 6 8 2 Control register of WKT 360 6 9 Serial Port UART0...

Page 4: ...I Interrupt 435 6 12 9Control Register of SPI 436 6 13 12 Bit Analog To Digital Converter ADC 441 6 13 1Overview 441 6 13 2Functional Description 441 6 13 3Control Registers of ADC 447 6 14 Auxiliary...

Page 5: ...MS51 Nov 28 2019 Page 5 of 491 Rev 1 00 MS51 32K SERIES TECHNICAL REFERENCE MANUAL 11 2 Instruction Set 486 12 REVISION HISTORY 490...

Page 6: ...Reloading 268 Figure 6 3 2 CONFIG2 Power On Reset Reloading 270 Figure 6 4 1 Quasi Bidirectional Mode Structure 273 Figure 6 4 2 Push Pull Mode Structure 273 Figure 6 4 3 Input Only Mode Structure 27...

Page 7: ...2 C Bus Interconnection 408 Figure 6 11 2 I 2 C Bus Protocol 409 Figure 6 11 3 START Repeated START and STOP Conditions 409 Figure 6 11 4 Master Transmits Data to Slave by 7 bit 410 Figure 6 11 5 Mast...

Page 8: ...7 1 1 NuMicro MS51 Power supply circuit 469 Figure 7 2 1 NuMicro MS51 Peripheral interface circuit 470 Figure 7 3 1 nRESET Reset Waveform 472 Figure 7 3 2 Low Voltage Reset LVR Waveform 473 Figure 7...

Page 9: ...cteristics of Each Interrupt Source 238 Table 6 3 1 IAP Modes and Command Codes 250 Table 6 4 1 Configuration for Different I O Modes 272 Table 6 6 1 PWM Pin Define And Enable Control Register 319 Tab...

Page 10: ...T one 16 bit auto reload Timer3 for general purpose or baud rate generator two UARTs with frame error detection and automatic address recognition three ISO 7816 3 interfaces one SPI one I2 C six basic...

Page 11: ...ytes of APROM for User Code 4 3 2 1 Kbytes of Flash for loader LDROM configure from APROM for In System Programmable ISP Flash Memory accumulated with pages of 128 Bytes from APROM by In Application P...

Page 12: ...from LIRC Able self Wake up wake up from Power down or Idle mode and auto reload count value Supports Interrupt PWM Up To 12 output pins can be selected Supports maximum clock source frequency up to...

Page 13: ...s Multi master bus no central master 7 bit addressing mode Standard mode 100 kbps and Fast mode 400 kbps Supports 8 bit time out counter requesting the I2 C interrupt if the I2 C bus hangs up and time...

Page 14: ...rd interrupt pins INT0 and INT1 Supports high drive and high sink current I O I O pin internal pull up or pull down resistor enabled in input mode Maximum I O Speed is 24 MHz Enabling the pin interrup...

Page 15: ...1 4 12 4 5 2 1 1 7 ch TSSOP14 MS51XB9AE 16 1 4 18 4 6 2 1 1 8 ch QFN20 3 MS51XB9BE 16 1 4 18 4 6 2 1 1 8 ch QFN20 3 MS51FB9AE 16 1 4 18 4 6 2 1 1 8 ch TSSOP20 MS51FC0AE 32 2 4 18 4 8 3 2 1 1 10 ch TSS...

Page 16: ...Line Package Flash SRAM Reserve Temperature 1T 8051 Industry 51 Base B MSOP10 3x3 mm D TSSOP14 4 4x5 0 mm E TSSOP28 4 4x9 7 mm F TSSOP20 4 4x6 5 mm I SOP8 4x5 mm O SOP20 300 mil P LQFP32 7x7 mm T QFN3...

Page 17: ...3 ADC_CH5 P0 4 PWM2_CH0 UART3_TXD T0 PWM0_CH2 IC6 ADC_CH4 P0 5 UART0_TXD ADC_CH3 P0 6 UART0_RXD ADC_CH2 P0 7 UART3_RXD PWM3_CH1 P3 4 nRESET P2 0 SPI0_MOSI UART2_TXD INT0 OSCIN ADC_CH1 P3 0 SPI0_CLK UA...

Page 18: ..._CH0 UART4_TXD P2 4 ADC_CH12 T0 P1 3 STADC I2C0_SCL ADC_CH13 P1 4 PWM0_CH1 I2C0_SDA PWM0_BRAKE ADC_CH14 PWM1_CH1 P3 7 UART1_TXD P3 6 UART1_RXD P0 1 PWM0_CH4 SPI0_MISO IC4 HXTOUT PWM3_CH0 P0 0 PWM0_CH3...

Page 19: ...1 P0 2 ICE_CLK I2C0_SCL UART1_RXD P3 3 PWM0_CH0 CLKO PWM0_BRAKE P0 1 PWM0_CH4 SPI0_MISO IC4 HXTOUT PWM3_CH0 P0 0 PWM0_CH3 SPI0_MOSI IC3 UART1_RXD T1 HXTIN PWM2_CH1 P1 0 PWM0_CH2 SPI0_CLK IC2 UART1_TXD...

Page 20: ..._CH2 P0 7 nRESET P2 0 SPI0_MOSI UART2_TXD INT0 OSCIN ADC_CH1 P3 0 SPI0_CLK UART2_RXD INT1 ADC_CH0 P1 7 V SS UART1_TXD I2C0_SDA ICE_DAT P1 6 P1 2 PWM0_CH0 IC0 UART3_TXD PWM1_CH0 P1 3 STADC I2C0_SCL ADC...

Page 21: ...Input capture channel 4 SPI0_MISO SPI master input slave output XT1_OUT External 4 24 MHz high speed crystal output pin 15 18 19 26 P0 2 Port 0 bit 2 I2C0_SCL I 2 C clock UART1_RXD UART1 receive inpu...

Page 22: ...lock output 10 13 13 20 P1 2 Port 1 bit 2 PWM0_CH0 PWM0 output channel 0 PWM1_CH0 PWM1 output channel 0 IC0 Input capture channel 0 UART3_TXD 6 UART3 transmit data output SC1_CLK 6 Smart Card 1 clock...

Page 23: ...0 PWM1 output channel 0 UART4_TXD 6 UART4 transmit data output SC2_CLK 6 Smart card 2 clock pin 8 13 P2 4 Port 2 bit 4 ADC_CH12 ADC input channel 12 T0 External count input to Timer Counter 0 or its t...

Page 24: ...nterrupt pin This feature is not listed in multi function description See Chapter 6 4 3 Pin Interrupt PIT 2 UART0_TXD and UART0_RXD pins are software exchangeable by UART0PX AUXR1 2 3 I2C alternate fu...

Page 25: ...ake up Timer Timer 3 UART2 3 4 ISO 7816 3 port 8 bit Internal Bus AIN0 7 9 15 STADC UART2 3 4_TX UART2 3 4_RX UART0 1_RX UART0 1_TX SPI0_MOSI SPI0_SS SPI0_SCK SPI0_MISO ICAP0 2 T1 T0 6 3 32 KB APROM F...

Page 26: ...rrupt causes the CPU to jump to that location with where it commences execution of the interrupt service routine ISR External Interrupt 0 for example is assigned to location 0003H If External Interrup...

Page 27: ...32 Kbytes 110 LDROM is 1 Kbytes APROM is 31 Kbytes 101 LDROM is 2 Kbytes APROM is 30 Kbytes 100 LDROM is 3 Kbytes APROM is 29 Kbytes 0xx LDROM is 4 Kbytes APROM is 28 Kbytes 1 The logic boundary addre...

Page 28: ...non secured mode the last byte is 0xFF The access behavior of SPROM is the same with APROM and LDROM All area can be read by CPU or ISP command and can be erased and programmed by ISP command 2 SPROM...

Page 29: ...ved 2 RPD Reset pin disable 1 The reset function of P2 0 nRST pin Enabled P2 0 nRST functions as the external reset pin 0 The reset function of P2 0 nRST pin Disabled P2 0 nRST functions as an input o...

Page 30: ...E 2 0 R W Factory default value 1111 1111b Bit Name Description 2 0 LDSIZE 2 0 LDROM size select Part number is MS51 111 No LDROM APROM is 32 Kbytes 110 LDROM is 1 Kbytes APROM is 31 Kbytes 101 LDROM...

Page 31: ...BOIAP Brown out inhibiting IAP This bit decides whether IAP erasing or programming is inhibited by brown out status This bit is valid only when brown out detection is enabled 1 IAP erasing or program...

Page 32: ...RENCE MANUAL CONFIG3 7 6 5 4 3 2 1 0 CKFS 1 0 R W Factory default value 1111 1111b Bit Name Description 7 6 CKFS 1 0 Clock filter time select Enable clock filter It increases noise immunity and EMC ca...

Page 33: ...4 WDTEN 3 0 WDT enable This field configures the WDT behavior after MCU execution 1111 WDT is Disabled WDT can be used as a general purpose timer via software control 0101 WDT is Enabled as a time out...

Page 34: ...all 80C51 devices The lowest 32 bytes as general purpose registers are grouped into 4 banks of 8 registers Program instructions call these registers as R0 to R7 Two bits RS0 and RS1 in the Program Sta...

Page 35: ...6 37 3B 3A 39 38 3C 3D 3E 3F 43 42 41 40 44 45 46 47 4B 4A 49 48 4C 4D 4E 4F 53 52 51 50 54 55 56 57 5B 5A 59 58 5C 5D 5E 5F 63 62 61 60 64 65 66 67 6B 6A 69 68 6C 6D 6E 6F 73 72 71 70 74 75 76 77 7B...

Page 36: ...de below Note that the stack pointer cannot be located in any part of XRAM XRAM demo code Assembler MOV R0 23H write 5AH to XRAM with address 23H MOV A 5AH MOVX R0 A MOV R1 23H read from XRAM with add...

Page 37: ...S51 contains all the SFR presenting in the standard 8051 However some additional SFR are built in Therefore some of unused bytes in the original 8051 have been given new functions The SFR are listed b...

Page 38: ...Register SFR Address Reset Value SFRS 91H All page 0000_0000 b 7 6 5 4 3 2 1 0 SFRPAGE1 SFRPAGE0 R W R W Bit Name Description 1 0 SFRPAGE 1 0 SFR page select 0 Instructions access SFR page 0 1 Instruc...

Page 39: ...ADDR ADCRL ADCRH T3CON RL3 RH3 TA 1 PWM0C4H PWM0C5H PIOCON1 2 PWM2PL PWM2_CH0L PWM2_CH1L PWM2CON0 PWM2CON1 PWM2INTC 0 B8 IP SADEN SADEN_1 SADDR_1 I2DAT I2STAT I2CLK I2TOC 1 2 PWM2PH PWM2_CH0H PWM2_CH1...

Page 40: ...EL1 BSEL0 0000 0000b SCON_1 Serial port 1 control F8H A SM0_1 FE_1 SM1_1 SM2_1 REN_1 TB8_1 RB8_1 TI_1 RI_1 0000 0000b EIPH Extensive interrupt priority high F7H 0 PT2H PSPIH PFBH PWDTH PPWMH PCAPH PPI...

Page 41: ...CHS1 ADCHS0 0000 0000b C1H Input capture 1 high byte E7H 0 C1H 7 0 0000 0000b E7H 1 SC1TSR SC1 Transfer Status Register E7H 2 ACT BEF FEF PEF TXEMPTY TXOV RXEMPTY RXOV 0000 1010b C1L Input capture 1 l...

Page 42: ...0111b Y PNP PWM0 negative polarity D6H 0 PNP5 PNP4 PNP3 PNP2 PNP1 PNP0 0000 0000b D6H 1 PWM3INT C PWM3 Interrupt Control D6H 2 INTTYP1 INTTYP0 INTSEL2 INTSEL1 INTSEL0 0000 0000b PWM0C3 H PWM0 channel...

Page 43: ...PWM0C5 H PWM0 channel 5 duty high byte C5H 1 PWM0C5 15 8 0000 0000b PWM2CO N1 PWM2 control 1 C5H 2 PWMMOD1 PWMMOD0 PWMTYP PWMDIV2 PWMDIV1 PWMDIV0 0000 0000b T3CON Timer 3 control C4H 0 SMOD_1 SMOD0_1...

Page 44: ...L PWM1 channel 1 duty low byte B3H 2 PWM1_CH1 7 0 0000 0000b P0M2 P0 mode select 2 B2H 0 P0M2 7 P0M2 6 P0M2 5 P0M2 4 P0M2 3 P0M2 2 P0M2 1 P0M2 0 0000 0000b P0SR P0 slew rate B2H 1 P0SR 7 P0SR 6 P0SR 5...

Page 45: ...0DG 0000 0000b IAPTRG IAP trigger A4H 0 IAPGO 0000 0000b Y A4H 1 AUXR5 Auxiliary Register 5 A4H 2 CLOP T0P PWM3_CH 1P1 PWM3_CH 1P0 PWM3_CH 0P1 PWM3_CH 0P0 0000 0000b BODCON 0 Brown out detection contr...

Page 46: ...b Y 96H 1 96H 2 0000 0000b CKDIV Clock divider 95H 0 CKDIV 7 0 0000 0000b 95H 1 P3UP Port 3 Pull Up resister control 95H 2 P3UP 7 P3UP 6 P3UP 5 P3UP 4 P3UP 3 P3UP 2 P3UP 1 P3UP 0 0000 0000b CAPCON2 In...

Page 47: ...DCBA2 ADCBA1 ADCBA0 0000 0000b RCTRIM0 Internal RC trim value high byte 84H 0 HIRCTRIM 8 1 0000 0000b Y 84H 1 ADCBAL ADC RAM Base Address Low Byte 84H 2 ADCBA 7 0 0000 0000b DPH Data pointer high byte...

Page 48: ...tatus Pn Port Bit addressable Register SFR Address Reset Value P0 80H All pages Bit addressable 1111_1111 b P1 90H All pages Bit addressable 1111_1111 b P2 A0H All pages Bit addressable 0011_1111 b P3...

Page 49: ...81H All pages 0000_0111b 7 6 5 4 3 2 1 0 SP 7 0 R W Bit Name Description 7 0 SP 7 0 Stack pointer The Stack Pointer stores the scratch pad RAM address where the stack begins It is incremented before...

Page 50: ...lue DPL 82H All pages 0000_0000b 7 6 5 4 3 2 1 0 DPL 7 0 R W Bit Name Description 7 0 DPL 7 0 Data pointer low byte This is the low byte of 16 bit data pointer DPL combined with DPH serve as a 16 bit...

Page 51: ...lue DPH 83H All pages 0000_0000b 7 6 5 4 3 2 1 0 DPH 7 0 R W Bit Name Description 7 0 DPH 7 0 Data pointer high byte This is the high byte of 16 bit data pointer DPH combined with DPL serve as a 16 bi...

Page 52: ...Reload Low Byte Register SFR Address Reset Value RWKL 86H Page 0 0000 0000b 7 6 5 4 3 2 1 0 RWK 7 0 R W Bit Name Description 7 0 RWK 7 0 WKT reload low byte The RWKL register is the low byte of the 16...

Page 53: ...load High Byte Register SFR Address Reset Value RWKH 97H Page 2 0000 0000b 7 6 5 4 3 2 1 0 RWK 15 8 R W Bit Name Description 7 0 RWK 15 8 WKT reload high byte The RWKH register is the low byte of the...

Page 54: ...flag that can be set or cleared by user via software 1 PD Power down mode Setting this bit puts CPU into Power down mode Under this mode both CPU and peripheral clocks stop and Program Counter PC sus...

Page 55: ...t or cleared by software 4 TR0 Timer 0 run control 0 Timer 0 Disabled Clearing this bit will halt Timer 0 and the current count will be preserved in TH0 and TL0 1 Timer 0 Enabled 3 IE1 External interr...

Page 56: ...1 Rev 1 00 MS51 32K SERIES TECHNICAL REFERENCE MANUAL Bit Name Description 0 IT0 External interrupt 0 type select This bit selects by which type that INT0 is triggered 0 INT0 is low level triggered 1...

Page 57: ...e external pin T1 5 M1 Timer 1 mode select M1 M0 Timer 1 Mode 0 0 Mode 0 13 bit Timer Counter 0 1 Mode 1 16 bit Timer Counter 1 0 Mode 2 8 bit Timer Counter with auto reload from TH1 1 1 Mode 3 Timer...

Page 58: ...ECHNICAL REFERENCE MANUAL TL0 Timer 0 Low Byte Register SFR Address Reset Value TL0 8AH Page0 0000_0000b 7 6 5 4 3 2 1 0 TL0 7 0 R W Bit Name Description 7 0 TL0 7 0 Timer 0 low byte The TL0 register...

Page 59: ...ECHNICAL REFERENCE MANUAL TL1 Timer 1 Low Byte Register SFR Address Reset Value TL1 8BH Page0 0000_0000b 7 6 5 4 3 2 1 0 TL1 7 0 R W Bit Name Description 7 0 TL1 7 0 Timer 1 low byte The TL1 register...

Page 60: ...HNICAL REFERENCE MANUAL TH0 Timer 0 High Byte Register SFR Address Reset Value TH0 8CH Page0 0000_0000b 7 6 5 4 3 2 1 0 TH0 7 0 R W Bit Name Description 7 0 TH0 7 0 Timer 0 high byte The TH0 register...

Page 61: ...HNICAL REFERENCE MANUAL TH1 Timer 1 High Byte Register SFR Address Reset Value TH1 8DH Page0 0000_0000b 7 6 5 4 3 2 1 0 TH1 7 0 R W Bit Name Description 7 0 TH1 7 0 Timer 1 high byte The TH1 register...

Page 62: ...the overflow of Timer 1 4 T1M Timer 1 clock mode select 0 The clock source of Timer 1 is the system clock divided by 12 It maintains standard 8051 compatibility 1 The clock source of Timer 1 is direct...

Page 63: ...bal interrupt are enabled setting this bit will make CPU execute WKT interrupt service routine This bit is not automatically cleared via hardware and should be cleared via software 3 WKTR WKT run cont...

Page 64: ...L SFRS SFR Page Selection Register SFR Address Reset Value SFRS 91H All page 0000_0000b 7 6 5 4 3 2 1 0 SFRPAGE1 SFRPAGE0 R W R W Bit Name Description 1 0 SFRPAGE 1 0 SFR page select 0 Instructions ac...

Page 65: ...enable 0 Input capture channel 1 Disabled 1 Input capture channel 1 Enabled 4 CAPEN0 Input capture 0 enable 0 Input capture channel 0 Disabled 1 Input capture channel 0 Enabled 2 CAPF2 Input capture...

Page 66: ...LS 1 0 CAP0LS 1 0 R W R W R W Bit Name Description 5 4 CAP2LS 1 0 Input capture 2 level select 00 Falling edge 01 Rising edge 10 Either Rising or falling edge 11 Reserved 3 2 CAP1LS 1 0 Input capture...

Page 67: ...n 6 ENF2 Enable noise filer on input capture 2 0 Noise filter on input capture channel 2 Disabled 1 Noise filter on input capture channel 2 Enabled 5 ENF1 Enable noise filer on input capture 1 0 Noise...

Page 68: ...er Register SFR Address Reset Value CKDIV 95H Page0 0000_0000b 7 6 5 4 3 2 1 0 CKDIV 7 0 R W Bit Name Description 7 0 CKDIV 7 0 Clock divider The system clock frequency FSYS follows the equation below...

Page 69: ...or disabled 1 External clock P00 input is enabled and stable 5 HIRCST High speed internal oscillator 16 MHz status 0 High speed internal oscillator is not stable or disabled 1 High speed internal osc...

Page 70: ...RCEN High speed internal oscillator 16 MHz enable 0 The high speed internal oscillator Disabled 1 The high speed internal oscillator Enabled Note that once IAP is enabled by setting IAPEN CHPCON 0 the...

Page 71: ...2 and FSYS 2 0 The clock runs at FSYS 12 baud rate It maintains standard 8051 compatibility 1 The clock runs at FSYS 2 baud rate for faster serial communica tion Mode 1 This bit checks valid stop bit...

Page 72: ...after the 8 th bit in Mode 0 or the last data bit in other modes When the serial port 0 interrupt is enabled setting this bit causes the CPU to execute the serial port 0 interrupt service routine Thi...

Page 73: ...Name Description 7 0 SBUF 7 0 Serial port 0 data buffer This byte actually consists two separate registers One is the receiving resister and the other is the transmitting buffer When data is moved to...

Page 74: ...it Name Description 7 0 SBUF_1 7 0 Serial port 1 data buffer This byte actually consists two separate registers One is the receiving resister and the other is the transmitting buffer When data is move...

Page 75: ...PSR 4 Enable 5 EFB Enable Fault Brake interrupt 0 Fault Brake interrupt Disabled 1 Interrupt generated by FBF PWM0FBD 7 Enabled 4 EWDT Enable WDT interrupt 0 WDT interrupt Disabled 1 Interrupt generat...

Page 76: ...N0 5 Enabled 4 EPWM2 Enable PWM2 interrupt 0 PWM2 interrupt Disabled 1 Interrupt generated by PWM2F PWM2CON0 5 Enabled 3 EPWM1 Enable PWM1 interrupt 0 PWM1 interrupt Disabled 1 Interrupt generated by...

Page 77: ...7 6 Reserved 5 HardF mirrored from AUXR1 5 Clear this bit by write AUXR1 5 0 or RSR 5 0 4 POF mirrored from PCON 4 Clear this bit by write PCON 4 0 or RSR 4 0 3 RSTPINF mirrored from AUXR1 6 Clear thi...

Page 78: ...CON0 7 as 1 and BORST BODCON0 2 as 0 This bit should be cleared via software 0 IAPEN IAP enable 0 IAP function Disabled 1 IAP function Enabled Once enabling IAP function the HIRC will be turned on for...

Page 79: ...s recommended that the flag be cleared via software Note If MCU run in OCD debug mode and OCDEN 0 hard fault reset will be disabled and only HardF flag be asserted 4 SLOW ADC Slow Speed Selection This...

Page 80: ...AL REFERENCE MANUAL Bit Name Description 0 DPS Data pointer select 0 Data pointer 0 DPTR is active by default 1 Data pointer 1 DPTR1 is active After DPS switches the activated data pointer the previou...

Page 81: ...lect 00 Reserved by default 01 Assign UART2 TX to P0 3 10 Assign UART2 TX to P3 0 11 Reserved 5 4 UART2RXP UART2 RX pin select 00 Reserved by default 01 Assign UART2 RX to P0 4 10 Assign UART2 RX to P...

Page 82: ...UART4 TX pin select 00 Reserved by default 01 Assign UART4 TX to P2 3 10 Reserved 11 Reserved 5 4 UART4RXP UART4 RX pin select 00 Reserved by default 01 Assign UART4 RX to P2 2 10 Reserved 11 Reserved...

Page 83: ...PWM2_CH1 to P3 0 01 Assign PWM2_CH1 to P3 1 10 Assign PWM2_CH1 to P0 0 11 Assign PWM2_CH1 to P0 4 5 4 PWM2_CH0P PWM2 channel 0 pin select 00 Reserved by default 01 Assign PWM2_CH0 to P2 1 10 Assign P...

Page 84: ...CLK Output pin select 0 Assign CLO to P1 1 while CLO output enabled 1 Assign CLO to P3 3 while CLO output enabled 6 T0P T0 pin select 0 Assign T0 to P0 5 1 Assign T0 to P2 4 5 4 Reserved 3 2 PWM3_CH1...

Page 85: ...R W R W R W Bit Name Description 4 UART4DG UART4 RX Deglitch Control 1 Deglitch is Enabled 0 Deglitch is Disabled 3 UART3DG UART3 RX Deglitch Control 1 Deglitch is Enabled 0 Deglitch is Disabled 2 UAR...

Page 86: ...IMISOP SPICKP R W R W R W R W Bit Name Description 4 3 SPI0NSSP SPI0_SS pin select 00 Assign SPI0_SS to P1 5 01 Reserved 10 Assign SPI0_SS to P3 5 11 Reserved 2 SPI0MOSIP SPI0_MOSI pin select 0 Assign...

Page 87: ...Name Description 7 4 CLODIV 3 0 Clock output divider The system clock output follows the equation below according to CLODIV value while CLODIV 00H and while CLODIV 01H to 0FH 3 0 CKTESTOEN 3 0 Clock...

Page 88: ...are set a brown out interrupt requirement will be generated This bit should be cleared via software 2 BORST Brown out reset enable This bit decides whether a brown out reset is caused by a power drop...

Page 89: ...o IAP begins by setting this bit as logic 1 After this instruction the CPU holds the Program Counter PC and the IAP hardware automation takes over to control the progress After IAP action completed th...

Page 90: ...APUEN R W R W R W Bit Name Description 2 CFUEN CONFIG bytes updated enable 0 Inhibit erasing or programming CONFIG bytes by IAP 1 Allow erasing or programming CONFIG bytes by IAP 1 LDUEN LDROM updated...

Page 91: ...ES TECHNICAL REFERENCE MANUAL IAPAL IAP Address Low Byte Register SFR Address Reset Value IAPAL A6H Page 0 0000 _0000 b 7 6 5 4 3 2 1 0 IAPA 7 0 R W Bit Name Description 7 0 IAPA 7 0 IAP address low b...

Page 92: ...TECHNICAL REFERENCE MANUAL IAPAH IAP Address High Byte Register SFR Address Reset Value IAPAH A7H Page 0 0000 _0000 b 7 6 5 4 3 2 1 0 IAPA 15 8 R W Bit Name Description 7 0 IAPA 15 8 IAP address high...

Page 93: ...pt 0 ADC interrupt Disabled 1 Interrupt generated by ADCF ADCCON0 7 Enabled 5 EBOD Enable brown out interrupt 0 Brown out detection interrupt Disabled 1 Interrupt generated by BOF BODCON0 3 Enabled 4...

Page 94: ...E MANUAL SADDR Slave 0 Address Register SFR Address Reset Value SADDR A9H Page 0 0000 _0000 b 7 6 5 4 3 2 1 0 SADDR 7 0 R W Bit Name Description 7 0 SADDR 7 0 Slave 0 address This byte specifies the m...

Page 95: ...DT counter is completely cleared 1 WDT counter is not yet cleared 5 WDTF WDT time out flag This bit indicates an overflow of WDT counter This flag should be cleared by software 4 WIDPD WDT running in...

Page 96: ...turning on BOD circuit every 6 4 ms periodically 11 BOD low power mode 3 by turning on BOD circuit every 25 6 ms periodically 0 BODFLT BOD filter control BOD has a filter which counts 32 clocks of FSY...

Page 97: ...0 0000 _0000 b 7 6 5 4 3 2 1 0 IAPFD 7 0 R W Bit Name Description 7 0 IAPFD 7 0 IAP Flash data This byte contains Flash data which is read from or is going to be written to the Flash Memory User shoul...

Page 98: ...Control Register SFR Address Reset Value IAPCN AFH Page 0 0011_0000 b 7 6 5 4 3 2 1 0 IAPB 1 0 FOEN FCEN FCTRL 3 0 R W R W R W R W Bit Name Description 7 6 IAPB 1 0 IAP control This byte is used for I...

Page 99: ...1 Register SFR Address Reset Value P0M1 B1H Page 0 1111_1111 b P1M1 B3H Page 0 1111_1111 b P2M1 89H Page 2 0011_1111 b P3M1 ACH Page 0 1111_1111 b 7 6 5 4 3 2 1 0 PnM1 7 PnM1 6 PnM1 5 PnM1 4 PnM1 3 P...

Page 100: ...4 3 2 1 0 PnM2 7 PnM2 6 PnM2 5 PnM2 4 PnM2 3 PnM2 2 PnM2 1 PnM2 0 R W R W R W R W R W R W R W R W Bit Name Description 7 0 PnM2 7 0 Port 0 mode select 2 NOTE PxM1 and PxM2 are used in combination to...

Page 101: ...ss Reset Value P0S B1H Page 1 0000_0000 b P1S B3H Page 1 0000_0000 b P2S 8CH Page 2 0000_0000 b P3S ACH Page 1 0000_0000 b 7 6 5 4 3 2 1 0 PnS 7 PnS 6 PnS 5 PnS 4 PnS 3 PnS 2 PnS 1 PnS 0 R W R W R W R...

Page 102: ...T1OE T0OE R W R W Bit Name Description 3 T1OE Timer 1 output enable 0 Timer 1 output Disabled 1 Timer 1 output Enabled from T1 pin Note that Timer 1 output should be enabled only when operating in it...

Page 103: ...iority high bit 5 PBOD Brown out detection interrupt priority high bit 4 PSH Serial port 0 interrupt priority high bit 3 PT1H Timer 1 interrupt priority high bit 2 PX1H External interrupt 1 priority h...

Page 104: ...t type select These bit select PWM interrupt type 00 Falling edge on PWM channel 0 1 2 3 4 5 pin 01 Rising edge on PWM channel 0 1 2 3 4 5 pin 10 Central point of a PWM period 11 End point of a PWM pe...

Page 105: ...DC interrupt priority low bit 5 PBOD Brown out detection interrupt priority low bit 4 PS Serial port 0 interrupt priority low bit 3 PT1 Timer 1 interrupt priority low bit 2 PX1 External interrupt 1 pr...

Page 106: ...ss Reset Value SADEN B9H Page 0 0000_0000 b 7 6 5 4 3 2 1 0 SADEN 7 0 R W Bit Name Description 7 0 SADEN 7 0 Slave 0 address mask This byte is a mask byte of UART0 that contains don t care bits define...

Page 107: ...Reset Value SADEN_1 BAH Page 0 0000_0000 b 7 6 5 4 3 2 1 0 SADEN_1 7 0 R W Bit Name Description 7 0 SADEN_1 7 0 Slave 1 address mask This byte is a mask byte of UART1 that contains don t care bits de...

Page 108: ...ANUAL SADDR_1 Slave 1 Address Register SFR Address Reset Value SADDR_1 BBH Page 0 0000_0000 b 7 6 5 4 3 2 1 0 SADDR_1 7 0 R W Bit Name Description 7 0 SADDR_1 7 0 Slave 1 address This byte specifies t...

Page 109: ...the I 2 C data to be transmitted or a byte which has just received Data in I2DAT remains as long as SI is logic 1 The result of reading or writing I2DAT during I 2 C transceiving progress is unpredic...

Page 110: ...7 3 I2STAT 7 3 I 2 C status code The MSB five bits of I2STAT contains the status code There are 27 possible status codes When I2STAT is F8H no relevant state information is available and SI flag keeps...

Page 111: ...is register determines the clock rate of I 2 C bus when the device is in a master mode The clock rate follows the equation 1 CLK 2 I 4 FSYS The default value will make the clock rate of I 2 C bus 400k...

Page 112: ...OF R W R W R W Bit Name Description 2 I2TOCEN I 2 C time out counter enable 0 I 2 C time out counter Disabled 1 I 2 C time out counter Enabled 1 DIV I 2 C time out counter clock divider 0 The clock of...

Page 113: ...e STOP condition has been detected on the bus The STO flag setting is also used to recover the I 2 C device from the bus error state I2STAT as 00H In this case no STOP condition is transmitted to the...

Page 114: ...d no interrupt is requested Note that if an addressed slave does not return an ACK under slave receiver mode or not receive an ACK under slave transmitter mode the slave device will become a not addre...

Page 115: ...hould address I 2 C device by sending the same address in the first byte data after a START or a repeated START condition If the AA flag is set this I 2 C device will acknowledge the master after rece...

Page 116: ...NICAL REFERENCE MANUAL ADCRL ADC Result Low Byte Register SFR Address Reset Value ADCRL C2H Page 0 0000_0000 b 7 6 5 4 3 2 1 0 ADCR 3 0 R Bit Name Description 3 0 ADCR 3 0 ADC result low byte The leas...

Page 117: ...CAL REFERENCE MANUAL ADCRH ADC Result High Byte Register SFR Address Reset Value ADCRH C3H Page 0 0000_0000 b 7 6 5 4 3 2 1 0 ADCR 11 4 R Bit Name Description 7 0 ADCR 11 4 ADC result high byte The mo...

Page 118: ...RCK Serial port 0 baud rate clock source This bit selects which Timer is used as the baud rate clock source when serial port 0 is in Mode 1 or 3 0 Timer 1 1 Timer 3 4 TF3 Timer 3 overflow flag This bi...

Page 119: ...ES TECHNICAL REFERENCE MANUAL RL3 Timer 3 Reload Low Byte Register SFR Address Reset Value RL3 C5H Page 0 0000_0000 b 7 6 5 4 3 2 1 0 RL3 7 0 R W Bit Name Description 7 0 RL3 7 0 Timer 3 reload low by...

Page 120: ...S TECHNICAL REFERENCE MANUAL RH3 Timer 3 Reload High Byte Register SFR Address Reset Value RH3 C6H Page 0 0000_0000 b 7 6 5 4 3 2 1 0 RH3 7 0 R W Bit Name Description 7 0 RH3 7 0 Timer 3 reload high b...

Page 121: ...in functions as P1 5 1 P1 5 PWM pin functions as PWM0C5 PWM3_CH1 output PWM3_CH1P 11 select PWM3_CH1 others select PWM0C5 3 PIO04 P0 4 PWM pin function select 0 P0 4 PWM pin functions as P0 4 1 P0 4 P...

Page 122: ...3 3 1 P3 3 PWM0C0 pin functions as PWM0_CH1 output 5 PIO32 P3 2 PWM3_CH0 pin function select 0 P3 2 PWM3_CH0 pin functions as P3 2 1 P3 2 PWM3_CH0 pin functions as PWM3_CH0 output 4 PIO31 P3 1 PWM2_CH...

Page 123: ...1 0 TA 7 0 W Bit Name Description 7 0 TA 7 0 Timed access The timed access register controls the access to protected SFRs To access protected bits user should first write AAH to the TA and immediatel...

Page 124: ...compare match occurs If the Timer 2 interrupt and the global interrupt are enable setting this bit will make CPU execute Timer 2 interrupt service routine This bit is not automatically cleared via ha...

Page 125: ...APCR Capture auto clear This bit is valid only under Timer 2 auto reload mode It enables hardware auto clearing TH2 and TL2 counter registers after they have been transferred in to RCMP2H and RCMP2L w...

Page 126: ...Register SFR Address Reset Value RCMP2L CAH Page 0 0000_0000 b 7 6 5 4 3 2 1 0 RCMP2L 7 0 R W Bit Name Description 7 0 RCMP2L 7 0 Timer 2 reload compare low byte This register stores the low byte of...

Page 127: ...Register SFR Address Reset Value RCMP2H CBH Page 0 0000_0000 b 7 6 5 4 3 2 1 0 RCMP2H 7 0 R W Bit Name Description 7 0 RCMP2H 7 0 Timer 2 reload compare high byte This register stores the high byte of...

Page 128: ...CHNICAL REFERENCE MANUAL TL2 Timer 2 Low Byte Register SFR Address Reset Value TL2 CCH Page 0 0000_0000 b 7 6 5 4 3 2 1 0 TL2 7 0 R W Bit Name Description 7 0 TL2 7 0 Timer 2 low byte The TL2 register...

Page 129: ...HNICAL REFERENCE MANUAL TH2 Timer 2 High Byte Register SFR Address Reset Value TH2 CDH Page 0 0000_0000 b 7 6 5 4 3 2 1 0 TH2 7 0 R W Bit Name Description 7 0 TH2 7 0 Timer 2 high byte The TH2 registe...

Page 130: ...FERENCE MANUAL ADCMPL ADC Compare Low Byte Register SFR Address Reset Value ADCMPL CEH Page 0 0000_0000 b 7 6 5 4 3 2 1 0 ADCMP 3 0 W R Bit Name Description 3 0 ADCMP 3 0 ADC compare low byte The leas...

Page 131: ...ERENCE MANUAL ADCMPH ADC Compare High Byte Register SFR Address Reset Value ADCMPH CFH Page 0 0000_0000 b 7 6 5 4 3 2 1 0 ADCMP 11 4 W R Bit Name Description 7 0 ADCMP 11 4 ADC compare high byte The m...

Page 132: ...4 RS1 Register bank selection bits These two bits select one of four banks in which R0 to R7 locate RS1 RS0 Register Bank RAM Address 0 0 0 00H to 07H 0 1 1 08H to 0FH 1 0 2 10H to 17H 1 1 3 18H to 1F...

Page 133: ...for an even number of ones It performs even parity check Instruction CY OV AC Instruction CY OV AC ADD X 1 X X CLR C 0 ADDC X X X CPL C X SUBB X X X ANL C bit X MUL 0 X ANL C bit X DIV 0 X ORL C bit...

Page 134: ...1 2 3 Register SFR Address Reset Value PWM0PH D1H Page 0 0000_0000 b PWM1PH A9H Page 2 0000_0000 b PWM2PH B9H Page 2 0000_0000 b PWM3PH C9H Page 2 0000_0000 b 7 6 5 4 3 2 1 0 PWM0P 15 8 R W Bit Name D...

Page 135: ...ative Polarity Register SFR Address Reset Value PNP D6H Page 0 0000_0000 b 7 6 5 4 3 2 1 0 PNP5 PNP4 PNP3 PNP2 PNP1 PNP0 R W R W R W R W R W R W Bit Name Description n PNPn PWMn negative polarity outp...

Page 136: ...n 7 FBF Fault Brake flag This flag is set when FBINEN is set as 1 and FB pin detects an edge which matches FBINLS PWM0FBD 6 selection This bit is cleared by software After FBF is cleared Fault Brake d...

Page 137: ...r the loading is complete LOAD will be automatically cleared via hardware The meaning of writing and reading LOAD bit is different Writing 0 No effect 1 Load new period and duty in their buffers while...

Page 138: ...be automatically cleared via hardware The meaning of writing and reading LOAD bit is different Writing 0 No effect 1 Load new period and duty in their buffers while a PWM period is completed Reading...

Page 139: ...starts running Note This bit is only for PWM0CON0 0 P33FBINEN P33 FB pin input enable 0 PWM0 output Fault Braked by P33 FB pin input Disabled 1 PWM0 output Fault Braked by P33 FB pin input Enabled On...

Page 140: ...1 2 3 Register SFR Address Reset Value PWM0PL D9H Page 0 0000_0000 b PWM1PL B1H Page 2 0000_0000 b PWM2PL C1H Page 2 0000_0000 b PWM3PL D1H Page 2 0000_0000 b 7 6 5 4 3 2 1 0 PWMnP 7 0 R W Bit Name D...

Page 141: ...nnel 1 Duty High Byte 0000_0000 b PWM0C2H D4H Page 0 PWM0 Channel 2 Duty High Byte 0000_0000 b PWM0C3H D5H Page 0 PWM0 Channel 3 Duty High Byte 0000_0000 b PWM0C4H C4H Page 1 PWM0 Channel 4 Duty High...

Page 142: ...Channel 1 Duty Low Byte 0000_0000 b PWM0C2L DCH Page 0 PWM0 Channel 2 Duty Low Byte 0000_0000 b PWM0C3L DDH Page 0 PWM0 Channel 3 Duty Low Byte 0000_0000 b PWM0C4L CCH Page 1 PWM0 Channel 4 Duty Low B...

Page 143: ...utput PWM3_CH0P 10b select PWM3_CH0 others select PWM0C4 3 PIO00 P0 0 PWM pin function select 0 P0 0 PWM pin functions as P0 0 1 P0 0 PWM pin functions as PWM0_CH3 PWM2_CH1 output PWM2_CH1P 10b select...

Page 144: ...es the group mode If enabled the duty of first three pairs of PWM are decided by PWM01H and PWM01L rather than their original duty control registers 0 Group mode Disabled 1 Group mode Enabled Note Thi...

Page 145: ...91 Rev 1 00 MS51 32K SERIES TECHNICAL REFERENCE MANUAL Bit Name Description 2 0 PWMDIV 2 0 PWM clock divider This field decides the pre scale of PWM clock source 000 1 1 001 1 2 010 1 4 011 1 8 100 1...

Page 146: ...or Register SFR Address Reset Value ACC E0H All pages Bit addressable 0000_0000 b 7 6 5 4 3 2 1 0 ACC 7 ACC 6 ACC 5 ACC 4 ACC 3 ACC 2 ACC 1 ACC 0 R W R W R W R W R W R W R W R W Bit Name Description 7...

Page 147: ...C clock source FSYS 2 10 ADC clock source FSYS 4 11 ADC clock source FSYS 8 3 2 ETGTYP 1 0 External trigger type select When ADCEX ADCCON1 1 is set these bits select which condition triggers ADC conve...

Page 148: ...fine The ADCF register changes to 1 only when ADC comparing result matches the condition and then enters interrupt vector if ADC interrupt is enabled 0 ADC result comparator trig ADCF Disabled 1 ADC r...

Page 149: ...3 bit field decides the acquisition sampling time for ADC AIN9 AIN15 sampling following by equation below ADC sampling time ADCAQT F 6 ADCAQT 4 FADCAQT is defined in ADCDIV ADCCON2 3 1 As default FAD...

Page 150: ...7 0 ADC external trigger delay counter low byte This 8 bit field combined with ADCCON2 0 forms a 9 bit counter This counter inserts a delay after detecting the external trigger An A D converting star...

Page 151: ...Byte n 0 1 2 Register SFR Address Reset Value C0L E4H Page 0 0000_0000 b C1L E6H Page 0 0000_0000 b C2L EDH Page 0 0000_0000 b 7 6 5 4 3 2 1 0 CnL 7 0 R W Bit Name Description 7 0 CnL 7 0 Input captur...

Page 152: ...Byte n 1 2 3 Register SFR Address Reset Value C0H E5H Page 0 0000_0000 b C1H E7H Page 0 0000_0000 b C2H EEH Page 0 0000_0000 b 7 6 5 4 3 2 1 0 CnH 7 0 R W Bit Name Description 7 0 CnH 7 0 Input captur...

Page 153: ...g is 1 ADC cannot start a new converting This bit is cleared by software 6 ADCS A D converting software start trigger Setting this bit 1 triggers an A D conversion This bit remains logic 1 during A D...

Page 154: ...el select This filed selects the activating analog input source of ADC If ADCEN is 0 all inputs are disconnected 0000 ADC_CH0 0001 ADC_CH1 0010 ADC_CH2 0011 ADC_CH3 0100 ADC_CH4 0101 ADC_CH5 0110 ADC_...

Page 155: ...red 1 Edge triggered 5 PIT5 Pin interrupt channel 5 type select This bit selects which type that pin interrupt channel 5 is triggered 0 Level triggered 1 Edge triggered 4 PIT4 Pin interrupt channel 4...

Page 156: ...f 491 Rev 1 00 MS51 32K SERIES TECHNICAL REFERENCE MANUAL Bit Name Description 0 PIT0 Pin interrupt channel 0 type select This bit selects which type that pin interrupt channel 0 is triggered 0 Level...

Page 157: ...0 PINEN7 PINEN6 PINEN5 PINEN4 PINEN3 PINEN2 PINEN1 PINEN0 R W R W R W R W R W R W R W R W Bit Name Description n PINENn Pin interrupt channel n negative polarity enable This bit enables low level fal...

Page 158: ...0 PIPEN7 PIPEN6 PIPEN5 PIPEN4 PIPEN3 PIPEN2 PIPEN1 PIPEN0 R W R W R W R W R W R W R W R W Bit Name Description n PIPENn Pin interrupt channel n positive polarity enable This bit enables high level ri...

Page 159: ...e R level R W edge R level R W edge R level R W edge R level R W edge R level R W edge Bit Name Description n PIFn Pin interrupt channel n flag If the edge trigger is selected this flag will be set by...

Page 160: ...nterrupt priority low bit 6 PSPI SPI interrupt priority low bit 5 PFB Fault Brake interrupt priority low bit 4 PWDT WDT interrupt priority low bit 3 PPWM PWM interrupt priority low bit 2 PCAP Input ca...

Page 161: ...TRIM 2 0 LDOTRIM 4 0 R W R W Bit Name Description 7 5 Uldotrim 2 0 Suspend LDO output voltage trim This field is used to adjust the output voltage of suspend LDO 000 Maximum voltage 001 110 Minimum vo...

Page 162: ...ter SFR Address Reset Value B F0H All pages Bit addressable 0000_0000 b 7 6 5 4 3 2 1 0 B 7 B 6 B 5 B 4 B 3 B 2 B 1 B 0 R W R W R W R W R W R W R W R W Bit Name Description 7 0 B 7 0 B register The B...

Page 163: ...R W R W R W R W R W R W R W R W Bit Name Description 7 4 CAP1 3 0 Input capture channel 0 input pin select 0000 P1 2 IC0 0001 P1 1 IC1 0010 P1 0 IC2 0011 P0 0 IC3 0100 P0 4 IC3 0101 P0 1 IC4 0110 P0 3...

Page 164: ...FR Address Reset Value CAPCON4 F2H Page 0 0000_0000 b 7 6 5 4 3 2 1 0 CAP23 CAP22 CAP21 CAP20 R W R W R W R W Bit Name Description 3 0 CAP2 3 0 Input capture channel 0 input pin select 0000 P1 2 IC0 0...

Page 165: ...e select the Slave device 6 SPIEN SPI enable 0 SPI function Disabled 1 SPI function Enabled 5 LSBFE LSB first enable 0 The SPI data is transferred MSB first 1 The SPI data is transferred LSB first 4 M...

Page 166: ...FSYS 16 MHz condition Fsys 16 MHz SPR1 SPR0 Divider SPI clock rate 0 0 2 8M bit s 0 1 4 4M bit s 1 0 8 WM bit s 1 1 16 1 M bit s Fsys 24 MHz SPR1 SPR0 Divider SPI clock rate 0 0 2 12M bit s 0 1 4 6M...

Page 167: ...6 5 4 3 2 1 0 SPIS1 SPIS0 R W R W Bit Name Description 7 2 Reserved 0 SPIS 1 0 SPI Interval time selection between adjacent bytes SPIS 1 0 and CPHA select eight grades of SPI interval time selection b...

Page 168: ...an overrun event occurs this bit will be set If ESPI and EA are enabled an SPI interrupt will be required This bit should be cleared via software 4 MODF Mode Fault error flag This bit indicates a Mod...

Page 169: ...0000 b 7 6 5 4 3 2 1 0 SPDR 7 0 R W Bit Name Description 7 0 SPDR 7 0 Serial peripheral data This byte is used for transmitting or receiving data on SPI bus A write of this byte is a write to the shif...

Page 170: ...SFR Address Reset Value AINDIDS0 F6H Page 0 0000_0000 b 7 6 5 4 3 2 1 0 P11DIDS P03DIDS P04DIDS P05DIDS P06DIDS P07DIDS P30DIDS P17DIDS R W R W R W R W R W R W R W R W Bit Name Description n PnnDIDS A...

Page 171: ...ter SFR Address Reset Value AINDIDS1 99H Page 2 0000_0000 b 7 6 5 4 3 2 1 0 P25DIDS P14DIDS P13DIDS P24DIDS P23DIDS P22DIDS P21DIDS R W R W R W R W R W R W R W R W Bit Name Description n PnnDIDS ADC C...

Page 172: ...interrupt priority high bit 6 PSPIH SPI interrupt priority high bit 5 PFBH Fault Brake interrupt priority high bit 4 PWDTH WDT interrupt priority high bit 3 PPWMH PWM interrupt priority high bit 2 PCA...

Page 173: ...eption is always valid no matter the logic level of stop bit 1 Reception is valid only when the received stop bit is logic 1 andthe received data matches Given or Broadcast address Mode 2 or 3 For mul...

Page 174: ...s bit causes the CPU to execute the serial port 1 interrupt service routine This bit must be cleared manually via software 0 RI_1 Receiving interrupt flag This flag is set via hardware when a data fra...

Page 175: ...bit is valid only when PWM4 5 is under complementary mode 0 No delay on GP4 GP5 pair signals 1 Insert dead time delay on the rising edge of GP4 GP5 pair signals 1 PDT23EN PWM2 3 pair dead time inserti...

Page 176: ...6 5 4 3 2 1 0 PWM0DTCNT 7 0 R W Bit Name Description 7 0 PWM0DTCNT 7 0 PWM dead time counter low byte This 8 bit field combined with PWM0DTEN 4 forms a 9 bit PWM dead time counter PWM0DTCNT This count...

Page 177: ...R W Bit Name Description x PMENx PWMnCx mask enable 0 PWMnCx signal outputs from its PWM generator 1 PWMnCx signal is masked by PMDx Note PMEN2 5 are only for PWM0 Register SFR Address Description Res...

Page 178: ...nCx mask data The PWMnCx signal outputs mask data once its corresponding PMENx is set 0 PWMnCx signal is masked by 0 1 PWMnCx signal is masked by 1 Note PMD2 5 are only for PWM0 Register SFR Address D...

Page 179: ...MANUAL PORDIS POR Disable Register SFR Address Reset Value PORDIS FDH Page 0 TA protected 0000_0000 b 7 6 5 4 3 2 1 0 PORDIS 7 0 W Bit Name Description 7 0 PORDIS 7 0 POR disable To first writing 5AH...

Page 180: ...Name Description 5 PPWM3 PWM3 interrupt priority low bit 4 PPWM2 PWM2 interrupt priority low bit 3 PPWM1 PWM1 interrupt priority low bit 2 PWKT WKT interrupt priority low bit 1 PT3 Timer 3 interrupt...

Page 181: ...t Name Description 5 PPWM3H PWM3 interrupt priority high bit 4 PPWM2H PWM2 interrupt priority high bit 3 PPWM1H PWM1 interrupt priority high bit 2 PWKTH WKT interrupt priority high bit 1 PT3H Timer 3...

Page 182: ...E MANUAL LVRDIS LVR disable Register SFR Address Reset Value EIPH1 FFH Page 1 TA protected 0000_0000 b 7 6 5 4 3 2 1 0 LVRDIS 7 0 W Bit Name Description 7 0 LVRDIS 7 0 LVR disable To first writing 5AH...

Page 183: ...5 4 3 2 1 0 PUART4 PUART3 PUART2 R W R W R W Bit Name Description 2 PUART4 UART4 interrupt priority low bit 1 PUART3 UART3 interrupt priority low bit 0 PUART2 UART2 interrupt priority low bit Note EI...

Page 184: ...5 4 3 2 1 0 PSC2H PSC1H PSC0H R W R W R W Bit Name Description 2 PSC2H SC2 UART4 interrupt priority high bit 1 PSC1H SC1 UART3 interrupt priority high bit 0 PSC0H SC0 UART2 interrupt priority high bit...

Page 185: ...0000_0000 b PIPS2 FBH page 2 0000_0000 b PIPS1 FAH page 2 0000_0000 b PIPS0 F9H page 2 0000_0000 b 7 6 5 4 3 2 1 0 PSEL 2 0 BSEL 2 0 R W R W Bit Name Description 6 4 PSEL 2 0 Pin interrupt channel Po...

Page 186: ...er for the bit length of block guard time According to ISO 7816 3 in T 0 mode the software must clear T bit to 0 for real block guard time 16 5 In T 1 mode the software must set T bit to 1 for real bl...

Page 187: ...e before Answer to Reset state and the first data must be 0x3B or 0x3F After hardware received first data and stored it at buffer hardware will decided the convention and change the CONSEL SCnCR0 4 bi...

Page 188: ...the last data word bit and stop bit of the serial data 1 Parity bit is not generated transmitting data or checked receiving data during transfer Note In ISO 7816 3 mode this field must be 0 default se...

Page 189: ...UART Mode Enable Bit 0 ISO 7816 3 mode 1 UART mode Note 1 When operating in UART mode user must set CONSEL SCnCR0 4 0 and AUTOCEN SCnCR0 3 0 Note 2 When operating in ISO 7816 3 mode user must set UAR...

Page 190: ...age 2 0000_0000 b SC2DR E9H Page 2 0000_0000 b 7 6 5 4 3 2 1 0 SCnDR 7 0 R W Bit Name Description 7 0 SCnDR 7 0 SC UART buffer data This byte is used for transmitting or receiving data on SC UART bus...

Page 191: ...rd Time Register Register SFR Address Reset Value SC0EGT DAH Page 2 0000_0000 b SC1EGT E2H Page 2 0000_0000 b SC2EGT EAH Page 2 0000_0000 b 7 6 5 4 3 2 1 0 SCnEGT 7 0 R W Bit Name Description 7 0 SCnE...

Page 192: ...DBH Page 2 0111_0011 b SC1ETURD0 E3H Page 2 0111_0011 b SC2ETURD0 EBH Page 2 0111_0011 b 7 6 5 4 3 2 1 0 ETURDIV 7 0 R W Bit Name Description 7 0 ETURDIV 7 0 LSB bits of ETU Rate Divider The field ind...

Page 193: ...Description 7 Reserved 6 4 SCDIV 2 0 SC clock divider 000 FSC is FSYS 1 001 FSC is FSYS 2 010 FSC is FSYS 4 011 FSC is FSYS 8 By default 100 FSC is FSYS 16 101 FSC is FSYS 16 110 FSC is FSYS 16 111 FS...

Page 194: ...t 0 Block guard time interrupt Disabled 1 Block guard time interrupt Enabled 2 TERRIEN Transfer Error Interrupt Enable Bit This field is used to enable transfer error interrupt The transfer error stat...

Page 195: ...us Flag Read Only This field is used for transfer error interrupt status flag The transfer error states is at SC0TSR register which includes receiver break error BEF SC0TSR 6 frame error FEF SC0TSR 5...

Page 196: ...ever the received character does not have a valid stop bit that is the stop bit following the last data bit or parity bit is detected as logic 0 Note This bit is read only but it can be cleared by wri...

Page 197: ...91 Rev 1 00 MS51 32K SERIES TECHNICAL REFERENCE MANUAL Bit Name Description 0 RXOV RX Overflow Error Status Flag Read Only This bit is set when RX buffer overflow Note This bit is read only but it can...

Page 198: ...rol TA Protected Register SFR Address Reset Value XTLCON D7H Page 2 0111_0111 b 7 6 5 4 3 2 1 0 HXSG R W Bit Name Description 7 Reserved 6 4 HXSG HXT gain value select 000 L0 mode smallest value 001 L...

Page 199: ...dress Reset Value P0DW 9AH page 2 0000_0000 b P1DW 9BH page 2 0000_0000 b P2DW 9CH page 2 0000_0000 b P3DW 9DH page 2 0000_0000 b 7 6 5 4 3 2 1 0 PnDW 7 PnDW 6 PnDW 5 PnDW 4 PnDW 3 PnDW 2 PnDW 1 PnDW...

Page 200: ...Address Reset Value P0UP 92H page 2 0000_0000 b P1UP 93H page 2 0000_0000 b P2UP 94H page 2 0000_0000 b P3UP 95H page 2 0000_0000 b 7 6 5 4 3 2 1 0 PnUP 7 PnUP 6 PnUP 5 PnUP 4 PnUP 3 PnUP 2 PnUP 1 PnU...

Page 201: ...gram System Clock Sources 6 2 1 2 There are a total of three system clock sources selectable in the MS51 including high speed internal oscillator low speed internal oscillator and external clock input...

Page 202: ...Nov 28 2019 Page 202 of 491 Rev 1 00 MS51 32K SERIES TECHNICAL REFERENCE MANUAL HIRC speed slower about 40 kHz Following shows two Byte combine the 9 bit internal RC trim value And HIRC 24 MHz define...

Page 203: ...03 of 491 Rev 1 00 MS51 32K SERIES TECHNICAL REFERENCE MANUAL RCTRIM0 High Speed Internal Oscillator 16 MHz Trim 0 Register SFR Address Reset Value RCTRIM0 84H Page0 TA protected 0000_0000b 7 6 5 4 3...

Page 204: ...f external clock sources 4 MHz to 24 MHz high speed crystal resonator HXT and the external clock input ECLK through XIN pin User can set OSC 2 0 as 0 1 x to select ECLK as the system clock By setting...

Page 205: ...equires some amount of warm up period for an original disabled clock source Therefore use should follow steps below to ensure a complete clock source switching User can enable the target clock source...

Page 206: ...it for stabilization of the target clock source and then switch to it in the background During this waiting period the device will continue executing the program with the original clock source and CKS...

Page 207: ...or disabled 1 External clock P00 input is enabled and stable 5 HIRCST High speed internal oscillator 16 MHz status 0 High speed internal oscillator is not stable or disabled 1 High speed internal osc...

Page 208: ...ning by the clock source of the internal 10 kHz oscillator 3 BOD is enabled or 4 LVR filter is enabled a write 0 to LIRCEN will be ignored LIRCEN is always 1 and the internal 10 kHz oscillator is alwa...

Page 209: ...the equation below according to CKDIV value OSC SYS F F while CKDIV 00H and CKDIV 2 F F OSC SYS while CKDIV 01H to FFH System Clock Output 6 2 1 7 The MS51 provides a CLO pin that outputs the system...

Page 210: ...N Clock Control Register SFR Address Reset Value CKCON 8EH Page0 0000_0000b 7 6 5 4 3 2 1 0 PWMCKS T1M T0M CLOEN R W R W R W R W Bit Name Description 1 CLOEN System clock output enable 0 System clock...

Page 211: ...ion at the instruction which follows the instruction that put the system into Power down mode Note that If IDL bit and PD bit are set simultaneously CPU will enter Power down mode Then it does not go...

Page 212: ...enters Power down mode In the Power down mode RAM maintains its content The port pins output the values held by their own state before Power down respectively There are several ways to exit the MS51...

Page 213: ...e applications These eight nominal levels are 1 8V 2 0V 2 4V 2 7V 3 0V 3 7V and 4 4V selected via setting CBOV 2 0 CONFIG2 6 4 BOD level can also be changed by setting BOV 2 0 BODCON0 6 4 after power...

Page 214: ...sis feature will disappear in low power BOD mode For a noise sensitive system the MS51 has a BOD filter which filters the power noise to avoid BOD event triggering unconsciously The BOD filter is enab...

Page 215: ...detection circuit on 0 Brown out detection circuit off 5 4 CBOV 1 0 CONFIG brown out voltage select 11 VBOD is 2 2V 10 VBOD is 2 7V 01 VBOD is 3 7V 00 VBOD is 4 4V 2 CBORST CONFIG brown out reset enab...

Page 216: ...are set a brown out interrupt requirement will be generated This bit should be cleared via software 2 BORST Brown out reset enable This bit decides whether a brown out reset is caused by a power drop...

Page 217: ...turning on BOD circuit every 6 4 ms periodically 11 BOD low power mode 3 by turning on BOD circuit every 25 6 ms periodically 0 BODFLT BOD filter control BOD has a filter which counts 32 clocks of FS...

Page 218: ...1 FLIRC Low power mode 2 LPBOD 1 0 1 0 Any clock source 64 1 FLIRC Low power mode 3 LPBOD 1 0 1 1 Any clock source 256 1 FLIRC 1 Normal mode LPBOD 1 0 0 0 HIRC ECLK Normal operation 32 1 FSYS Idle mo...

Page 219: ...a power on flag POF PCON 4 will be set 1 to indicate a cold reset a power on process complete Note that the contents of internal RAM will be undetermined after a power on It is recommended that user...

Page 220: ...t Once the device is in reset condition it will remain as long as RST pin is low After the RST high is removed the MCU will exit the reset state and begin code executing from address 0000H If an exter...

Page 221: ...eared via software Note If MCU run in OCD debug mode and OCDEN 0 Hard fault reset will disable Only HardF flag be asserted Watchdog Timer Reset 6 2 4 5 The WDT is a free running timer with programmabl...

Page 222: ...s quite useful in the end of an ISP progress For example if an ISP of Boot Code updating User Code finishes a software reset can be asserted to re boot CPU to execute new User Code immediately Writing...

Page 223: ...FR Address Reset Value CHPCON 9FH All page TA protected Software 0000_00U0 b Others 0000_00C0 b 7 6 5 4 3 2 1 0 SWRST IAPFF BS IAPEN W R W R W R W Bit Name Description 7 SWRST Software reset To set th...

Page 224: ...11b software reset flag clear CLR EA MOV TA 0Aah MOV TA 55h ORL CHPCON 10000000b software reset Boot Select 6 2 4 7 RST pin reset Brown out reset Software reset Low voltage reset Load Reset and boot f...

Page 225: ...CDEN LOCK R W R W R W R W Factory default value 1111 1111b Bit Name Description 7 CBS CONFIG boot select This bit defines from which block that MCU re boots after resets except software reset 1 MCU wi...

Page 226: ...released from reset state the hardware will always check the BS bit instead of the CBS bit to determine from which block that the device reboots Reset State 6 2 4 8 The reset state besides power on r...

Page 227: ...crucial to proper operation of the system If leaving these control registers unprotected errant code may write undetermined value into them and results in incorrect operation and loss of control To pr...

Page 228: ...ed access window is opened It remains open for 4 clock cycles during which user may write to the protected bits After 4 clock cycles this window automatically closes Once the window closes the procedu...

Page 229: ...the protected bits is done before the 3 clock cycle window closes In example 2 however the writing to BODCON0 does not complete during the window opening there will be no change of the value of BODCON...

Page 230: ...Number Source Vector Address Vector Number Reset 0000H Input capture interrupt 0063H 12 External interrupt 0 0003H 0 PWM0 interrupt 006BH 13 Timer 0 overflow 000BH 1 Fault Brake interrupt 0073H 14 Ex...

Page 231: ...rupts can be generated Note that every interrupts if enabled is generated by a setting as logic 1 of its interrupt flag no matter by hardware or software User should take care of each interrupt flag i...

Page 232: ...pt 0 ADC interrupt Disabled 1 Interrupt generated by ADCF ADCCON0 7 Enabled 5 EBOD Enable brown out interrupt 0 Brown out detection interrupt Disabled 1 Interrupt generated by BOF BODCON0 3 Enabled 4...

Page 233: ...SPSR 4 Enable 5 EFB Enable Fault Brake interrupt 0 Fault Brake interrupt Disabled 1 Interrupt generated by FBF PWM0FBD 7 Enabled 4 EWDT Enable WDT interrupt 0 WDT interrupt Disabled 1 Interrupt genera...

Page 234: ...ON0 5 Enabled 4 EPWM2 Enable PWM2 interrupt 0 PWM2 interrupt Disabled 1 Interrupt generated by PWM2F PWM2CON0 5 Enabled 3 EPWM1 Enable PWM1 interrupt 0 PWM1 interrupt Disabled 1 Interrupt generated by...

Page 235: ...e a low priority interrupt handler is running if a high priority interrupt arrives the handler will be interrupted and the high priority handler will run When the high priority handler does RETI the l...

Page 236: ...ity bits natural priority and the permission to wake up the CPU from Power down mode For details of waking CPU up from Power down mode please see Section 6 2 2 3 Power Down Mode Interrupt Priority Con...

Page 237: ...terrupt 003BH PIF0 to PIF7 PIF 3 EPI 8 PPI PPIH Yes Timer 1 001BH TF1 2 ET1 9 PT1 PT1H No Serial port 0 0023H RI TI ES 10 PS PSH No Fault Brake event 0073h FBF PWM0FBD 7 EFB 11 PFB PFBH No SPI 004Bh S...

Page 238: ...interrupt pin is set as edge triggered Itx 1 its own flag Iex will be automatically cleared if the interrupt service routine ISR is executed While as level triggered Itx 0 Iex follows the inverse of r...

Page 239: ...DC interrupt priority low bit 5 PBOD Brown out detection interrupt priority low bit 4 PS Serial port 0 interrupt priority low bit 3 PT1 Timer 1 interrupt priority low bit 2 PX1 External interrupt 1 pr...

Page 240: ...ority high bit 5 PBOD Brown out detection interrupt priority high bit 4 PSH Serial port 0 interrupt priority high bit 3 PT1H Timer 1 interrupt priority high bit 2 PX1H External interrupt 1 priority hi...

Page 241: ...terrupt priority low bit 6 PSPI SPI interrupt priority low bit 5 PFB Fault Brake interrupt priority low bit 4 PWDT WDT interrupt priority low bit 3 PPWM PWM interrupt priority low bit 2 PCAP Input cap...

Page 242: ...interrupt priority high bit 6 PSPIH SPI interrupt priority high bit 5 PFBH Fault Brake interrupt priority high bit 4 PWDTH WDT interrupt priority high bit 3 PPWMH PWM interrupt priority high bit 2 PCA...

Page 243: ...Name Description 5 PPWM3 PWM3 interrupt priority low bit 4 PPWM2 PWM2 interrupt priority low bit 3 PPWM1 PWM1 interrupt priority low bit 2 PWKT WKT interrupt priority low bit 1 PT3 Timer 3 interrupt...

Page 244: ...Name Description 5 PPWM3H PWM3 interrupt priority high bit 4 PPWM2H PWM2 interrupt priority high bit 3 PPWM1H PWM1 interrupt priority high bit 2 PWKTH WKT interrupt priority high bit 1 PT3H Timer 3 i...

Page 245: ...5 4 3 2 1 0 PSC2 PSC1 PSC0 R W R W R W Bit Name Description 2 PSC2 SC2 UART4 interrupt priority low bit 1 PSC1 SC1 UART3 interrupt priority low bit 0 PSC0 SC0 UART2 interrupt priority low bit Note EI...

Page 246: ...system clock cycle If an interrupt flag is active in one cycle but not responded to for the above conditions are not met if the flag is not still active when the blocking condition is removed the den...

Page 247: ...e RETI 6 clock cycles to complete the longest instruction 1 clock cycle to detect the interrupt and 4 clock cycles to complete the hardware LCALL to the interrupt vector location Thus in a single inte...

Page 248: ...rigger this flag follows the inverse of the INT1 input signal s logic level Software cannot control it 2 IT1 External interrupt 1 type select This bit selects by which type that INT1 is triggered 0 IN...

Page 249: ...lly controlled disregard of the operating voltage and frequency Nominally a page erase time is 5 ms and a byte program time is 23 5 s After IAP action completed the Program Counter continues to run th...

Page 250: ...001H CONFIG2 0002H CONFIG4 0004H CONFIG6 0005H Data in CONFIG byte read 11 0 0 0000 CONFIG0 0000H CONFIG1 0001H CONFIG2 0002H CONFIG4 0004H CONFIG6 0005H Data out Note 1 X means don t care 2 Each page...

Page 251: ...tory default value 1111 1111b Bit Name Description 3 BOIAP Brown out inhibiting IAP This bit decide whether IAP erasing or programming is inhibited by brown out status This bit is valid only when brow...

Page 252: ...tion is met 1 The accessing address is oversize 2 IAPCN command is invalid 3 IAP erases or programs updating un enabled block 4 IAP erasing or programming operates under VBOD while BOIAP CONFIG2 5 rem...

Page 253: ...CPU memory address 0xff80 0xffff is mapping to SPROM memory 3 SPUEN SPROM Memory space updated enable TA protected 0 Inhibit erasing or programming SPRO Mbytes by IAP 1 Allow erasing or programming SP...

Page 254: ...CAL REFERENCE MANUAL IAPCN IAP Control Register SFR Address Reset Value IAPCN AFH Page 0 0011_0000 b Bit Name Description 7 6 IAPB 1 0 IAP control This byte is used for IAP command For details see Tab...

Page 255: ...MS51 32K SERIES TECHNICAL REFERENCE MANUAL IAPAH IAP Address High Byte Register SFR Address Reset Value IAPAH A7H Page 0 0000 _0000 b Bit Name Description 7 0 IAPA 15 8 IAP address high byte IAPAH con...

Page 256: ...ES TECHNICAL REFERENCE MANUAL IAPAL IAP Address Low Byte Register SFR Address Reset Value IAPAL A6H Page 0 0000 _0000 b 7 6 5 4 3 2 1 0 IAPA 7 0 R W Bit Name Description 7 0 IAPA 7 0 IAP address low b...

Page 257: ...0 0000 _0000 b 7 6 5 4 3 2 1 0 IAPFD 7 0 R W Bit Name Description 7 0 IAPFD 7 0 IAP Flash data This byte contains Flash data which is read from or is going to be written to the Flash Memory User shou...

Page 258: ...ings will possible cause undetermined results even serious damages of devices Furthermore this paragraph will also support useful suggestions during IAP procedures 1 If no more IAP operation is needed...

Page 259: ...APROM 201h as a byte of Data Flash when user code is executed in APROM PAGE_ERASE_AP EQU 00100010b BYTE_PROGRAM_AP EQU 00100001b ORG 0000h MOV TA 0Aah CHPCON is TA protected MOV TA 55h ORL CHPCON 000...

Page 260: ...element array in code area from absolute address 0x0200 volatile unsigned char code Data_Flash 128 _at_ 0x0200 Main void TA 0Xaa CHPCON is TA protected TA 0x55 CHPCON 0x01 IAPEN 1 enable IAP mode TA 0...

Page 261: ...e that resides in LDROM The maximum size of LDROM is 4K Byte User developed Boot Code can be re programmed by parallel writer or In Circuit Programming ICP tool General speaking an ISP is carried out...

Page 262: ...erify Programmed CONFIG2 CALL Disable_IAP MOV TA 0Aah TA protection MOV TA 55h ANL CHPCON 11111101b BS 0 reset to APROM MOV TA 0Aah MOV TA 55h ORL CHPCON 80h software reset and reboot from APROM SJMP...

Page 263: ...APTRG 00000001b write 1 to IAPGO to trigger IAP process RET IAP APROM Function Erase_AP MOV IAPCN PAGE_ERASE_AP MOV IAPFD 0FFh MOV R0 00h Erase_AP_Loop MOV IAPAH R0 MOV IAPAL 00h CALL Trigger_IAP MOV...

Page 264: ..._AP_Verify_Loop RET Program_AP_Verify_Error CALL Disable_IAP MOV P0 00h SJMP IAP CONFIG Function Erase_CONFIG MOV IAPCN ALL_ERASE_CONFIG MOV IAPAH 00h MOV IAPAL 00h MOV IAPFD 0FFh CALL Trigger_IAP RET...

Page 265: ...mmed with the most recent firmware or a customized firmware There are three signal pins RST ICP_DAT and ICP_CLK involved in ICP function RST is used to enter or exit ICP mode ICP_DAT is the data input...

Page 266: ...he MS51 is a fully featured microcontroller that multiplexes several functions on its limited I O pins Some device functionality must be sacrificed to provide resources for OCD system The OCD has the...

Page 267: ...factory pre programmed with a 96 bit width serial number which is guaranteed to be unique The serial number is called Unique Code The user can read the Unique Code only by IAP command Please see Chapt...

Page 268: ...ed 2 RPD Reset pin disable 1 The reset function of P2 0 Nrst pin Enabled P2 0 Nrst functions as the external reset pin 0 The reset function of P2 0 Nrst pin Disabled P2 0 Nrst functions as an input on...

Page 269: ...W Factory default value 1111 1111b Bit Name Description 2 0 LDSIZE 2 0 LDROM size select This field selects the size of LDROM 111 No LDROM APROM is 32 Kbytes 110 LDROM is 1 Kbytes APROM is 31 Kbytes 1...

Page 270: ...P Brown out inhibiting IAP This bit decides whether IAP erasing or programming is inhibited by brown out status This bit is valid only when brown out detection is enabled 1 IAP erasing or programming...

Page 271: ...4 WDTEN 3 0 WDT enable This field configures the WDT behavior after MCU execution 1111 WDT is Disabled WDT can be used as a general purpose timer via software control 0101 WDT is Enabled as a time ou...

Page 272: ...suppression capability All I O pins also have bit controllable slew rate select ability via software The control registers are PxSR By default the slew rate is slow If user would like to increase the...

Page 273: ...ce current is needed for an output driving Port Pin Input Port Latch P N VDD Strong Figure 6 4 2 Push Pull Mode Structure Input Only Mode 6 4 1 3 Input only mode provides true high impedance input pat...

Page 274: ...Structure 6 4 2 Read Modify Write Instructions Instructions that read a byte from SFR or internal RAM modify it and rewrite it back are called Read Modify Write instructions When the destination is an...

Page 275: ...terrupt flags located in PIF register The respective flags for each pin interrupt channel allow the interrupt service routine to poll on which channel on which the interrupt event occurs All flags in...

Page 276: ...rs are bit addressable Pn Port Bit addressable Register SFR Address Reset Value P0 80H All pages Bit addressable 1111_1111 b P1 90H All pages Bit addressable 1111_1111 b P2 A0H All pages Bit addressab...

Page 277: ...1 Register SFR Address Reset Value P0M1 B1H Page 0 1111_1111 b P1M1 B3H Page 0 1111_1111 b P2M1 89H Page 2 0011_1111 b P3M1 ACH Page 0 1111_1111 b 7 6 5 4 3 2 1 0 PnM1 7 PnM1 6 PnM1 5 PnM1 4 PnM1 3 P...

Page 278: ...I O pin can be configured individually as TTL input or Schmitt triggered input Note that all of PxS registers are accessible by switching SFR page to Page 1 PnS Port n Schmitt Triggered Input Registe...

Page 279: ...MS51 Nov 28 2019 Page 279 of 491 Rev 1 00 MS51 32K SERIES TECHNICAL REFERENCE MANUAL Note that all PxSR registers are accessible by switching SFR page to Page 1...

Page 280: ...set Value P0SR B2H Page 1 0000_0000 b P1SR B4H Page 1 0000_0000 b P2SR 8BH Page 2 0000_0000 b P3SR ADH Page 1 0000_0000 b 7 6 5 4 3 2 1 0 PnSR 7 PnSR 6 PnSR 5 PnSR 4 PnSR 3 PnSR 2 PnSR 1 PnSR 0 R W R...

Page 281: ...red 1 Edge triggered 5 PIT5 Pin interrupt channel 5 type select This bit selects which type that pin interrupt channel 5 is triggered 0 Level triggered 1 Edge triggered 4 PIT4 Pin interrupt channel 4...

Page 282: ...f 491 Rev 1 00 MS51 32K SERIES TECHNICAL REFERENCE MANUAL Bit Name Description 0 PIT0 Pin interrupt channel 0 type select This bit selects which type that pin interrupt channel 0 is triggered 0 Level...

Page 283: ...0 PINEN7 PINEN6 PINEN5 PINEN4 PINEN3 PINEN2 PINEN1 PINEN0 R W R W R W R W R W R W R W R W Bit Name Description n PINENn Pin interrupt channel n negative polarity enable This bit enables low level fal...

Page 284: ...0 PIPEN7 PIPEN6 PIPEN5 PIPEN4 PIPEN3 PIPEN2 PIPEN1 PIPEN0 R W R W R W R W R W R W R W R W Bit Name Description n PIPENn Pin interrupt channel n positive polarity enable This bit enables high level ri...

Page 285: ...e R level R W edge R level R W edge R level R W edge R level R W edge R level R W edge Bit Name Description n PIFn Pin interrupt channel n flag If the edge trigger is selected this flag will be set by...

Page 286: ...0000_0000 b PIPS2 FBH page 2 0000_0000 b PIPS1 FAH page 2 0000_0000 b PIPS0 F9H page 2 0000_0000 b 7 6 5 4 3 2 1 0 PSEL 2 0 BSEL 2 0 R W R W Bit Name Description 6 4 PSEL 2 0 Pin interrupt channel Po...

Page 287: ...automatically to toggle output whenever a timer overflow occurs The same device pins that are used for the T0 and T1 count inputs are also used for the timer toggle outputs This function is enabled by...

Page 288: ...uto reload mode In this mode TL0 TL1 acts as an 8 bit count register whereas TH0 TH1 holds the reload value When the TL0 TL1 register overflow the TF0 TF1 bit in TCON is set and TL0 TL1 is reloaded wi...

Page 289: ...ching it out of or into its own Mode 3 It can still be used in Modes 0 1 and 2 although its flexibility is restricted It no longer has control over its overflow flag TF1 and the enable bit TR1 However...

Page 290: ...with auto reload from TH1 1 1 Mode 3 Timer 1 halted 4 M0 3 GATE Timer 0 gate control 0 Timer 0 will clock when TR0 is 1 regardless of INT0 logic level 1 Timer 0 will clock only when TR0 is 1 and INT0...

Page 291: ...ll be preserved in TH0 and TL0 1 Timer 0 Enabled 3 IE1 External interrupt 1 edge flag If IT1 1 falling edge trigger this flag will be set by hardware when a falling edge is detected It remain set unti...

Page 292: ...ECHNICAL REFERENCE MANUAL TL0 Timer 0 Low Byte Register SFR Address Reset Value TL0 8AH Page0 0000_0000b 7 6 5 4 3 2 1 0 TL0 7 0 R W Bit Name Description 7 0 TL0 7 0 Timer 0 low byte The TL0 register...

Page 293: ...CHNICAL REFERENCE MANUAL TH0 Timer 0 High Byte Register SFR Address Reset Value TH0 8CH Page0 0000_0000b 7 6 5 4 3 2 1 0 TH0 7 0 R W Bit Name Description 7 0 TH0 7 0 Timer 0 high byte The TH0 register...

Page 294: ...ECHNICAL REFERENCE MANUAL TL1 Timer 1 Low Byte Register SFR Address Reset Value TL1 8BH Page0 0000_0000b 7 6 5 4 3 2 1 0 TL1 7 0 R W Bit Name Description 7 0 TL1 7 0 Timer 1 low byte The TL1 register...

Page 295: ...CHNICAL REFERENCE MANUAL TH1 Timer 1 High Byte Register SFR Address Reset Value TH1 8DH Page0 0000_0000b 7 6 5 4 3 2 1 0 TH1 7 0 R W Bit Name Description 7 0 TH1 7 0 Timer 1 high byte The TH1 register...

Page 296: ...r 0 output Disabled 1 Timer 0 output Enabled from T0 pin Note that Timer 0 output should be enabled only when operating in its Timer mode 6 5 2 Timer2 And Input Capture Overview 6 5 2 1 Timer 2 is a 1...

Page 297: ...Capture 0 Module Input Capture 1 Module Input Capture 2 Module Input Capture Flags CAPF 2 0 CAPCR 1 T2MOD 3 CAPF0 CAPF1 CAPF2 Clear Timer 2 1 Once CAPCR and LDEN are both set an input capture event o...

Page 298: ...MP2L contents TF2 Timer 2 Interrupt Pre scalar FSYS RCMP2H T2DIV 2 0 T2MOD 6 4 RCMP2L TH2 TL2 00 01 10 11 CAPF0 CAPF1 CAPF2 LDEN 1 T2MOD 7 LDTS 1 0 T2MOD 1 0 TR2 T2CON 2 Timer 2 Module C0H C0L Noise F...

Page 299: ...er 2 counter as 0000H automatically after a compare match has occurred Input Capture Interrupt CAPF0 CAPF1 CAPF2 TF2 Timer 2 Interrupt Pre scalar FSYS RCMP2H T2DIV 2 0 T2MOD 6 4 RCMP2L TH2 TL2 TR2 T2C...

Page 300: ...channel has to set its own enabling bit CAPEN0 2 CAPCON0 6 4 before use While input capture channel is enabled and the selected edge trigger occurs the content of the free running Timer 2 counter TH2...

Page 301: ...ch occurs If the Timer 2 interrupt and the global interrupt are enable setting this bit will make CPU execute Timer 2 interrupt service routine This bit is not automatically cleared via hardware and s...

Page 302: ...APCR Capture auto clear This bit is valid only under Timer 2 auto reload mode It enables hardware auto clearing TH2 and TL2 counter registers after they have been transferred in to RCMP2H and RCMP2L w...

Page 303: ...Register SFR Address Reset Value RCMP2L CAH Page 0 0000_0000 b 7 6 5 4 3 2 1 0 RCMP2L 7 0 R W Bit Name Description 7 0 RCMP2L 7 0 Timer 2 reload compare low byte This register stores the low byte of...

Page 304: ...Register SFR Address Reset Value RCMP2H CBH Page 0 0000_0000 b 7 6 5 4 3 2 1 0 RCMP2H 7 0 R W Bit Name Description 7 0 RCMP2H 7 0 Timer 2 reload compare high byte This register stores the high byte of...

Page 305: ...CHNICAL REFERENCE MANUAL TL2 Timer 2 Low Byte Register SFR Address Reset Value TL2 CCH Page 0 0000_0000 b 7 6 5 4 3 2 1 0 TL2 7 0 R W Bit Name Description 7 0 TL2 7 0 Timer 2 low byte The TL2 register...

Page 306: ...H2 7 0 R W Bit Name Description 7 0 TH2 7 0 Timer 2 high byte The TH2 register is the high byte of the 16 bit counting register of Timer 2 Note that the TH2 and TL2 are accessed separately It is stron...

Page 307: ...1 enable 0 Input capture channel 1 Disabled 1 Input capture channel 1 Enabled 4 CAPEN0 Input capture 0 enable 0 Input capture channel 0 Disabled 1 Input capture channel 0 Enabled 3 Reserved 2 CAPF2 In...

Page 308: ...CAP0LS 1 0 R W R W R W Bit Name Description 7 6 Reserved 5 4 CAP2LS 1 0 Input capture 2 level select 00 Falling edge 01 Rising edge 10 Either rising or falling edge 11 Reserved 3 2 CAP1LS 1 0 Input c...

Page 309: ...on 6 ENF2 Enable noise filer on input capture 2 0 Noise filter on input capture channel 2 Disabled 1 Noise filter on input capture channel 2 Enabled 5 ENF1 Enable noise filer on input capture 1 0 Nois...

Page 310: ...Byte n 0 1 2 Register SFR Address Reset Value C0L E4H Page 0 0000_0000 b C1L E6H Page 0 0000_0000 b C2L EDH Page 0 0000_0000 b 7 6 5 4 3 2 1 0 CnL 7 0 R W Bit Name Description 7 0 CnL 7 0 Input captur...

Page 311: ...Byte n 1 2 3 Register SFR Address Reset Value C0H E5H Page 0 0000_0000 b C1H E7H Page 0 0000_0000 b C2H EEH Page 0 0000_0000 b 7 6 5 4 3 2 1 0 CnH 7 0 R W Bit Name Description 7 0 CnH 7 0 Input captur...

Page 312: ...R W R W R W R W R W R W R W R W Bit Name Description 7 4 CAP1 3 0 Input capture channel 1 input pin select 0000 P1 2 IC0 0001 P1 1 IC1 0010 P1 0 IC2 0011 P0 0 IC3 0100 P0 4 IC3 0101 P0 1 IC4 0110 P0 3...

Page 313: ...FR Address Reset Value CAPCON4 F2H Page 0 0000_0000 b 7 6 5 4 3 2 1 0 CAP23 CAP22 CAP21 CAP20 R W R W R W R W Bit Name Description 3 0 CAP2 3 0 Input capture channel 2 input pin select 0000 P1 2 IC0 0...

Page 314: ...he baud rate clock source of both UARTs For details please see Section 6 9 3 Baud Rate RL3 TR3 T3CON 3 FSYS Internal 16 bit Counter 0 7 RH3 0 7 Timer 3 Overflow Pre scalar 1 1 1 128 T3PS 2 0 T3CON 2 0...

Page 315: ...v 1 00 MS51 32K SERIES TECHNICAL REFERENCE MANUAL Bit Name Description 2 0 T3PS 2 0 Timer 3 pre scalar These bits determine the scale of the clock divider for Timer 3 000 1 1 001 1 2 010 1 4 011 1 8 1...

Page 316: ...ES TECHNICAL REFERENCE MANUAL RL3 Timer 3 Reload Low Byte Register SFR Address Reset Value RL3 C5H Page 0 0000_0000 b 7 6 5 4 3 2 1 0 RL3 7 0 R W Bit Name Description 7 0 RL3 7 0 Timer 3 reload low by...

Page 317: ...S TECHNICAL REFERENCE MANUAL RH3 Timer 3 Reload High Byte Register SFR Address Reset Value RH3 C6H Page 0 0000_0000 b 7 6 5 4 3 2 1 0 RH3 7 0 R W Bit Name Description 7 0 RH3 7 0 Timer 3 reload high b...

Page 318: ...two PWM1 2 3 can be configured as one of independent mode complementary mode or synchronous mode The PWM1 2 3 waveform can be edge aligned or center aligned with variable interrupt points PWM output...

Page 319: ...riod counter The duty of each PWM is determined independently by the value of duty registers PWM0 has six duty registers PWM1 2 3 has two duty registers These PWMs output can be generated independentl...

Page 320: ...egister PWM0C4 buffer PWM0C4 Register PWM0C5 buffer PWM0C5 Register P0G2 P0G3 P0G4 P0G5 0 1 0 1 0 1 0 1 GP PWM0CON1 5 PWM0PH PWM0PL PWM0CH0H PWM0CH0L PWM0CH1H PWM0CH1L PWM0CH2H PWM0CH2L PWM0CH3H PWM0C...

Page 321: ...CON0 4 PWMnP registers LOAD PWMnCON0 6 PWMF PWMnCON0 5 PWMnP buffer PWMnC0 buffer PWMnC0 Register 0 to 1 PWMn and Fault Brake output control PWMTYP PWMnCON1 4 edge center Interrupt select type PWMDIV0...

Page 322: ...CH0 PWM0_CH3 PWM0_CH1 PWM0_CH2 PWM0_CH5 PWM0_CH4 Figure 6 6 3 PWM0 and Fault Brake Output Control Block Diagram User should follow the initialization steps below to start generating the PWM signal out...

Page 323: ...AD bit Any updating of PWM control registers during LOAD bit as logic 1 will cause unpredictable output PWM Types 6 6 2 2 The PWM generator provides two PWM types edge aligned or center aligned PWM ty...

Page 324: ...y PWMDIV PWM high level duty 1 PWMnPL PWMnPH PWMnCHxL PWMnCHxH Center Aligned Type 6 6 2 4 In center aligned mode the 16 bit counter use dual slop operation by counting up from 0000H to PWMnPH PWMnPL...

Page 325: ...n a real motor application a complementary PWM0 output always has a need of dead time insertion to prevent damage of the power switching device like GPIBs due to being active on simultaneously of the...

Page 326: ...ardware to assert a Fault Brake interrupt if enabled PWMnFBD data output remains even after the FBF is cleared by software User should resume the PWM output only by setting PWM0RUN again Meanwhile the...

Page 327: ...flag PWMF PWMnCON0 5 to indicate certain point of each complete PWM period The indicating PWM channel and point can be selected by INTSEL 2 0 and INTTYP 1 0 PWMnINTC 2 0 and 5 4 Note that the center p...

Page 328: ...t type select These bit select PWM interrupt type 00 Falling edge on PWM channel 0 1 2 3 4 5 pin 01 Rising edge on PWM channel 0 1 2 3 4 5 pin 10 Central point of a PWM period 11 End point of a PWM pe...

Page 329: ...nter Dead time PWMF falling edge INTTYP 1 0 0 0 PWMF rising edge INTTYP 1 0 0 1 Edge aligned PWM Center aligned PWM Reserved Figure 6 6 9 PWM Interrupt Type Fault Brake event requests another interrup...

Page 330: ...ected on the next PWM cycle After the loading is complete LOAD will be automatically cleared via hardware The meaning of writing and reading LOAD bit is different Writing 0 No effect 1 Load new period...

Page 331: ...PWM1RUN PWM1 run enable 0 PWM1 stays in idle 1 PWM1 starts running Note This bit is only for PWM0CON0 0 P33FBINEN P33 FB pin input enable 0 PWM0 output Fault Braked by P33 FB pin input Disabled 1 PWM...

Page 332: ...r the loading is complete LOAD will be automatically cleared via hardware The meaning of writing and reading LOAD bit is different Writing 0 No effect 1 Load new period and duty in their buffers while...

Page 333: ...es the group mode If enabled the duty of first three pairs of PWM are decided by PWM01H and PWM01L rather than their original duty control registers 0 Group mode Disabled 1 Group mode Enabled Note Thi...

Page 334: ...91 Rev 1 00 MS51 32K SERIES TECHNICAL REFERENCE MANUAL Bit Name Description 2 0 PWMDIV 2 0 PWM clock divider This field decides the pre scale of PWM clock source 000 1 1 001 1 2 010 1 4 011 1 8 100 1...

Page 335: ...lock Control Register SFR Address Reset Value CKCON 8EH Page0 0000_0000b 7 6 5 4 3 2 1 0 PWMCKS T1M T0M T0OE CLOEN R W R W R W R W R W Bit Name Description 6 PWMCKS PWM clock source select 0 The clock...

Page 336: ...1 2 3 Register SFR Address Reset Value PWM0PL D9H Page 0 0000_0000 b PWM1PL B1H Page 2 0000_0000 b PWM2PL C1H Page 2 0000_0000 b PWM3PL D1H Page 2 0000_0000 b 7 6 5 4 3 2 1 0 PWM0P 7 0 R W Bit Name D...

Page 337: ...1 2 3 Register SFR Address Reset Value PWM0PH D1H Page 0 0000_0000 b PWM1PH A9H Page 2 0000_0000 b PWM2PH B9H Page 2 0000_0000 b PWM3PH C9H Page 2 0000_0000 b 7 6 5 4 3 2 1 0 PWM0P 15 8 R W Bit Name D...

Page 338: ...nnel 1 Duty High Byte 0000_0000 b PWM0C2H D4H Page 0 PWM0 Channel 2 Duty High Byte 0000_0000 b PWM0C3H D5H Page 0 PWM0 Channel 3 Duty High Byte 0000_0000 b PWM0C4H C4H Page 1 PWM0 Channel 4 Duty High...

Page 339: ...Channel 1 Duty Low Byte 0000_0000 b PWM0C2L DCH Page 0 PWM0 Channel 2 Duty Low Byte 0000_0000 b PWM0C3L DDH Page 0 PWM0 Channel 3 Duty Low Byte 0000_0000 b PWM0C4L CCH Page 1 PWM0 Channel 4 Duty Low B...

Page 340: ...alid only when PWM0C4 5 is under complementary mode 0 No delay on P0G4 P0G5 pair signals 1 Insert dead time delay on the rising edge of P0G4 P0G5 pair signals 1 PDT23EN PWM0_CH2 3 pair dead time inser...

Page 341: ...5 4 3 2 1 0 PWM0DTCNT 7 0 R W Bit Name Description 7 0 PWM0DTCNT 7 0 PWM0 dead time counter low byte This 8 bit field combined with PWM0DTEN 4 forms a 9 bit PWM0 dead time counter PWM0DTCNT This count...

Page 342: ...R W Bit Name Description x PMENx PWMnCx mask enable 0 PWMnCx signal outputs from its PWM generator 1 PWMnCx signal is masked by PMDx Note PMEN2 5 are only for PWM0 Register SFR Address Description Res...

Page 343: ...nCx mask data The PWMnCx signal outputs mask data once its corresponding PMENx is set 0 PWMnCx signal is masked by 0 1 PWMnCx signal is masked by 1 Note PMD2 5 are only for PWM0 Register SFR Address D...

Page 344: ...R W R W Bit Name Description 3 FBINEN FB pin input enable 0 PWM output Fault Braked by FB pin input Disabled 1 PWM output Fault Braked by FB pin input Enabled Once an edge which matches FBINLS PWM0FB...

Page 345: ...n 7 FBF Fault Brake flag This flag is set when FBINEN is set as 1 and FB pin detects an edge which matches FBINLS PWM0FBD 6 selection This bit is cleared by software After FBF is cleared Fault Brake d...

Page 346: ...tive Polarity Register SFR Address Reset Value PNP D6H Page 0 0000_0000 b 7 6 5 4 3 2 1 0 PNP5 PNP4 PNP3 PNP2 PNP1 PNP0 R W R W R W R W R W R W Bit Name Description 5 0 PNPn PWMn negative polarity out...

Page 347: ...output PWM3_CH0P 10 select PWM3_CH0 others select PWM0C4 3 PIO03 P0 0 PWM pin function select 0 P0 0 PWM pin functions as P0 0 1 P0 0 PWM pin functions as PWM0_CH3 PWM2_CH1 output PWM2_CH1P 10 select...

Page 348: ...ut When AUXR5 3 2 PWM3CH1P 11 PIO15 1 P1 5 define as PWM3_CH1 When AUXR5 3 2 PWM3CH1P 00 PIO15 1 P1 5 define as PWM0_CH5 3 PIO04 P0 4 PWM pin function select 0 P0 4 PWM pin functions as P0 4 1 P0 4 PW...

Page 349: ...3 3 1 P3 3 PWM0C0 pin functions as PWM0_CH1 output 5 PIO32 P3 2 PWM3_CH0 pin function select 0 P3 2 PWM3_CH0 pin functions as P3 2 1 P3 2 PWM3_CH0 pin functions as PWM3_CH0 output 4 PIO31 P3 1 PWM2_CH...

Page 350: ...PWM2_CH1 to P3 0 01 Assign PWM2_CH1 to P3 1 10 Assign PWM2_CH1 to P0 0 11 Assign PWM2_CH1 to P0 4 5 4 PWM2_CH0P PWM2 channel 0 pin select 00 Reserved by default 01 Assign PWM2_CH0 to P2 1 10 Assign P...

Page 351: ...00_0000 b 7 6 5 4 3 2 1 0 CLOP T0P PWM3_CH1P PWM3_CH0P R W R W R W R W Bit Name Description 3 2 PWM3_CH1P PWM3 channel 1 pin select 00 Reserved by default 01 Assign PWM3_CH1 to P3 4 10 Assign PWM3_CH1...

Page 352: ...ONFIG4 7 4 initialize the WDT to operate as a time out reset timer or a general purpose timer The Watchdog time out interval is determined by the formula 64 scalar divider clock F 1 LIRC where FLIRC i...

Page 353: ...e Others WDT is Enabled as a time out reset timer and it keeps running during Idle or Power down mode The WDT is implemented with a set of divider that divides the low speed internal oscillator clock...

Page 354: ...cleared 5 WDTF WDT time out flag This bit indicates an overflow of WDT counter This flag should be cleared by software 4 WIDPD WDT running in Idle or Power down mode This bit is valid only when contro...

Page 355: ...WDT occurs the WDT reset flag WDTRF WDCON 3 will be set This bit keeps unchanged after any reset other than a power on reset User may clear WDTRF via software Note that all bits in WDCON require time...

Page 356: ...ption of Idle mode still keeps at a mA level To further reducing the current consumption to uA level the CPU should stay in Power down mode when nothing needs to be served and has the ability of wakin...

Page 357: ...timer and it stops running during Idle or Power down mode Others WDT is Enabled as a time out reset timer and it keeps running during Idle or Power down mode The WDT is implemented with a set of divid...

Page 358: ...1 WDT counter is not yet cleared 5 WDTF WDT time out flag This bit indicates an overflow of WDT counter This flag should be cleared by software 4 WIDPD WDT running in Idle or Power down mode This bit...

Page 359: ...of WKT will not automatically enabled along with WKT configuration User should manually enable the selected clock source and waiting for stability to ensure a proper operation The WKT is implemented...

Page 360: ...interrupt and the global interrupt are enabled setting this bit will make CPU execute WKT interrupt service routine This bit is not automatically cleared via hardware and should be cleared via softwa...

Page 361: ...Reload Low Byte Register SFR Address Reset Value RWKL 86H Page 0 0000 0000b 7 6 5 4 3 2 1 0 RWK 7 0 R W Bit Name Description 7 0 RWK 7 0 WKT reload low byte The RWKL register is the low byte of the 1...

Page 362: ...eload High Byte Register SFR Address Reset Value RWKH 97H Page 2 0000 0000b 7 6 5 4 3 2 1 0 RWK 15 8 R W Bit Name Description 7 0 RWK 15 8 WKT reload high byte The RWKH register is the low byte of the...

Page 363: ...communication with external devices Serial data centers and exits through RXD pin TXD outputs the shift clocks 8 bit frame of data are transmitted or received Mode 0 therefore provides half duplex co...

Page 364: ...gin at any time Reception is initiated by a detected 1 to 0 transition at RXD Data will be sampled and shifted in at the selected baud rate In the midst of the stop bit certain conditions should be me...

Page 365: ...ditions fail there will be no data loaded and RI will remain 0 After above receiving progress the serial control will look forward another 1 to 0 transition on RXD pin to start next data reception Mod...

Page 366: ...256 F 32 1 SYS Timer 3 3 RL 3 RH 256 65536 scale Pre F 32 1 SYS 1 Time1 TM1 CKCON 3 0 TH1 256 12 F 16 1 SYS Time1 TM1 CKCON 3 1 TH1 256 F 16 1 SYS Timer 3 RL3 RH3 256 65536 scale Pre F 16 1 SYS 2 11...

Page 367: ...3 256 65536 scale Pre F 16 1 SYS Table 6 9 2 Serial Port UART1 Mode baudrate Description Sample code we list the most popular UART setting Mode 1 initial step as following Serial port 0 UART0 use time...

Page 368: ...and the deviation value Fsys Value Baud Rate TH1 Value Hex RH3 RL3 Value Hex Baudrate Deviation 24 MHz 4800 64 SMOD 0 FEC8 0 160256 9600 64 FF64 0 160256 19200 B2 FFB2 0 160256 38400 D9 FFD9 0 160256...

Page 369: ...1 so that when a byte of frame is received the serial interrupt will be generated only if the 9th bit is 1 For Mode 2 the 9th bit is the stop bit When the SM2 bit is 1 serial data frames that are rec...

Page 370: ...bit Using the automatic address recognition feature allows a master to selectively communicate with one or more slaves by invoking the Given slave address or addresses All of the slaves may be contact...

Page 371: ...ess is 11100011b To select Slaves 0 and 1 and exclude Slave 2 use address 11100100b since it is necessary to make bit 2 1 to exclude slave 2 The Broadcast address for each slave is created by taking t...

Page 372: ...ud rate between FSYS 12 and FSYS 2 0 The clock runs at FSYS 12 baud rate It maintains standard 8051compatibility 1 The clock runs at FSYS 2 baud rate for faster serial communication Mode 1 This bit ch...

Page 373: ...0 after the 8th bit in Mode 0 or the last data bit in other modes When the serial port 0 interrupt is enabled setting this bit causes the CPU to execute the serial port 0 interrupt service routine Thi...

Page 374: ...ption is always valid no matter the logic level of stop bit 1 Reception is valid only when the received stop bit is logic 1 and the received data matches Given or Broadcast address Mode 2 or 3 For mul...

Page 375: ...s bit causes the CPU to execute the serial port 1 interrupt service routine This bit must be cleared manually via software 0 RI_1 Receiving interrupt flag This flag is set via hardware when a data fra...

Page 376: ...DL R W R W RW R W R W R W R W R W Bit Name Description 7 SMOD Serial port 0 double baud rate enable Setting this bit doubles the serial port baud rate when UART0 is in Mode 2 or when Timer 1 overflow...

Page 377: ...details 6 SMOD0_1 Serial port 1 framing error access enable 0 S1CON 7 accesses to SM0_1 bit 1 S1CON 7 accesses to FE_1 bit SBUF Serial Port 0 Data Buffer Register SFR Address Reset Value SBUF 99H Pag...

Page 378: ...it Name Description 7 0 SBUF_1 7 0 Serial port 1 data buffer This byte actually consists two separate registers One is the receiving resister and the other is the transmitting buffer When data is move...

Page 379: ...egister SFR Address Reset Value IE A8H All pages Bit addressable 0000 _0000 b 7 6 5 4 3 2 1 0 EA EADC EBOD ES ET1 EX1 ET0 EX0 R W R W R W R W R W R W R W R W Bit Name Description 4 ES Enable serial po...

Page 380: ...Register SFR Address Reset Value EIE1 9CH Page 0 0000 _0000 b 7 6 5 4 3 2 1 0 EPWM3 EPWM2 EPWM1 EWKT ET3 ES_1 R W R W R W R W R W R W Bit Name Description 0 ES1 Enable serial port 1 interrupt 0 Serial...

Page 381: ...CE MANUAL SADDR Slave 0 Address Register SFR Address Reset Value SADDR A9H Page 0 0000 _0000 b 7 6 5 4 3 2 1 0 SADDR 7 0 R W Bit Name Description 7 0 SADDR 7 0 Slave 0 address This byte specifies the...

Page 382: ...ss Reset Value SADEN B9H Page 0 0000_0000 b 7 6 5 4 3 2 1 0 SADEN 7 0 R W Bit Name Description 7 0 SADEN 7 0 Slave 0 address mask This byte is a mask byte of UART0 that contains don t care bits define...

Page 383: ...ANUAL SADDR_1 Slave 1 Address Register SFR Address Reset Value SADDR_1 BBH Page 0 0000_0000 b 7 6 5 4 3 2 1 0 SADDR_1 7 0 R W Bit Name Description 7 0 SADDR_1 7 0 Slave 1 address This byte specifies t...

Page 384: ...Reset Value SADEN_1 BAH Page 0 0000_0000 b 7 6 5 4 3 2 1 0 SADEN_1 7 0 R W Bit Name Description 7 0 SADEN_1 7 0 Slave 1 address mask This byte is a mask byte of UART1 that contains don t care bits de...

Page 385: ...4 3 2 1 0 SWRF RSTPINF HardF SLOW GF2 UART0PX 0 DPS R W R W R W R W R W R W R R W Bit Name Description 2 UART0PX Serial port 0 pin exchange 0 Assign RXD to P0 7 and TXD to P0 6 by default 1 Exchange R...

Page 386: ...000 b 7 6 5 4 3 2 1 0 UART2TXP UART2RXP UART1TXP UART1RXP R W R W R W R W Bit Name Description 3 2 UART1TXP UART1 TX pin select 00 Reserved by default 01 Assign UART1 TX to P1 6 10 Assign UART1 TX to...

Page 387: ...ta Bus TX_OUT RX_IN Figure 6 10 1 SC Controller Block Diagram ISO 7816 3 T 0 T 1 compliant Programmable transmission clock frequency Programmable extra guard time selection Supports auto inverse conve...

Page 388: ...ace controller supports activation cold reset warm reset and deactivation sequence by software control The activation cold reset warm reset and deactivation and sequence are shown as follows SC Interf...

Page 389: ...T at high level reception mode by software programming to 1 period of timing T1 3 Enable SCn_CLK clock by programming CLKKEEP SCCR2 1 to 1 after timing T1 4 De assert SCn_RST to high by software progr...

Page 390: ...measured by chip IO pin the real value will depended on system design Time 81 129 161 161 483 531 563 42106 T4 T5 T5 T6 Suggesting timing Unit SC Clock 400 T6 40000 SC_DAT SC_RST SC_RST to SC_DAT Rec...

Page 391: ...gth by setting WLS SCCR2 5 4 parity format by setting OPE SCCR2 7 and PBOFF SCCR2 6 and stop bit length by setting NSB SCnCR1 7 5 Write the SCnDR SCnDR 7 0 TX register or read the SCnDR SCnDR 7 0 RX r...

Page 392: ..._DAT to low by 1 5 bit period to inform the transmitter parity error Then the transmitter will retransmit the character The SC interface controller supports hardware error detection function SC0TSR 4...

Page 393: ...O 7816 3 host controller sends data to ISO 7816 3 first If the ISO 7816 3 sends data to ISO 7816 3 host controller at the time which is less than 16 5 or 22 5 by T bit setting the block guard time int...

Page 394: ...d indicates the counter for the bit length of block guard time According to ISO 7816 3 in T 0 mode the software must clear T bit to 0 for real block guard time 16 5 In T 1 mode the software must set T...

Page 395: ...e before Answer to Reset state and the first data must be 0x3B or 0x3F After hardware received first data and stored it at buffer hardware will decided the convention and change the CONSEL SCnCR0 4 bi...

Page 396: ...the last data word bit and stop bit of the serial data 1 Parity bit is not generated transmitting data or checked receiving data during transfer Note In ISO 7816 3 mode this field must be 0 default se...

Page 397: ...UART Mode Enable Bit 0 ISO 7816 3 mode 1 UART mode Note 1 When operating in UART mode user must set CONSEL SCnCR0 4 0 and AUTOCEN SCnCR0 3 0 Note 2 When operating in ISO 7816 3 mode user must set UAR...

Page 398: ...age 2 0000_0000 b SC2DR E9H Page 2 0000_0000 b 7 6 5 4 3 2 1 0 SCnDR 7 0 R W Bit Name Description 7 0 SCnDR 7 0 SC UART buffer data This byte is used for transmitting or receiving data on SC UART bus...

Page 399: ...rd Time Register Register SFR Address Reset Value SC0EGT DAH Page 2 0000_0000 b SC1EGT E2H Page 2 0000_0000 b SC2EGT EAH Page 2 0000_0000 b 7 6 5 4 3 2 1 0 SCnEGT 7 0 R W Bit Name Description 7 0 SCnE...

Page 400: ...DBH Page 2 0111_0011 b SC1ETURD0 E3H Page 2 0111_0011 b SC2ETURD0 EBH Page 2 0111_0011 b 7 6 5 4 3 2 1 0 ETURDIV 7 0 R W Bit Name Description 7 0 ETURDIV 7 0 LSB bits of ETU Rate Divider The field ind...

Page 401: ...Description 7 Reserved 6 4 SCDIV 2 0 SC clock divider 000 FSC is FSYS 1 001 FSC is FSYS 2 010 FSC is FSYS 4 011 FSC is FSYS 8 By default 100 FSC is FSYS 16 101 FSC is FSYS 16 110 FSC is FSYS 16 111 FS...

Page 402: ...t 0 Block guard time interrupt Disabled 1 Block guard time interrupt Enabled 2 TERRIEN Transfer Error Interrupt Enable Bit This field is used to enable transfer error interrupt The transfer error stat...

Page 403: ...us Flag Read Only This field is used for transfer error interrupt status flag The transfer error states is at SC0TSR register which includes receiver break error BEF SC0TSR 6 frame error FEF SC0TSR 5...

Page 404: ...ever the received character does not have a valid stop bit that is the stop bit following the last data bit or parity bit is detected as logic 0 Note This bit is read only but it can be cleared by wri...

Page 405: ...91 Rev 1 00 MS51 32K SERIES TECHNICAL REFERENCE MANUAL Bit Name Description 0 RXOV RX Overflow Error Status Flag Read Only This bit is set when RX buffer overflow Note This bit is read only but it can...

Page 406: ...H Page 2 0000_0000 b 7 6 5 4 3 2 1 0 UART2TXP UART2RXP UART1TXP UART1RXP R W R W R W R W Bit Name Description 7 6 UART2TXP UART2 TX pin select 00 Reserved by default 01 Assign UART2 TX to P0 3 10 Assi...

Page 407: ...UART4 TX pin select 00 Reserved by default 01 Assign UART4 TX to P2 3 10 Reserved 11 Reserved 5 4 UART4RXP UART4 RX pin select 00 Reserved by default 01 Assign UART4 RX to P2 2 10 Reserved 11 Reserve...

Page 408: ...l the line high In MS51 user should set output latches of I2C0_SCL and I2C0_SDA As logic 1 before enabling the I 2 C function by setting I2CEN SDA SCL Slave Device SDA SCL Other MCU SDA SCL VDD RUP RU...

Page 409: ...thout first generating a STOP condition Various combinations of read write formats are then possible within such a transfer SDA SCL START STOP START Repeated START STOP Figure 6 11 3 START Repeated ST...

Page 410: ...the General Call it operates as like in the slave receiver mode Note that the address 0x00 is reserved for General Call and cannot be used as a slave address therefore in theory a 7 bit addressing I 2...

Page 411: ...the competing master devices to place a 1 high on I2C0_SDA while another master transmits a 0 low switches off its data output stage because the level on the bus does not match its own level The arbit...

Page 412: ...tion of the new action a new status code will be updated in I2C_STATUS0 register and the SI flag of I2C_CTL0 register will be set But the SI flag will not be set when I2 C STOP If the I2 C interrupt c...

Page 413: ...A STO SI AA 1 0 1 x STATUS 0xF8 STA STO SI AA 0 1 1 x STATUS 0x08 STA STO SI AA 1 1 1 x I2CnDAT SLA W ACK NAK Arbitration Lost STATUS 0x38 I2C_DAT SLA W STA STO SI AA 0 0 1 x I2CnDAT Data ACK NAK STAT...

Page 414: ...repeated START condition to terminate the transmission or initial another one I2CnDAT SLA R ACK NAK I2CnDAT Data NAK I2CnDAT Data ACK P S P Sr I2CnDAT SLA R STA STO SI AA 0 0 1 x STATUS 0x40 STATUS 0x...

Page 415: ...late with the master It cannot receive any byte of data with I2CnDAT remaining the previous byte of data which is just received Slave Transmitter The I2 C port is equipped with four slave address regi...

Page 416: ...Data ACK NAK STA STO SI AA 0 0 1 1 I2CnDAT Data STA STO SI AA 0 0 1 0 STATUS 0x80 STATUS 0x88 Arbitration Lost Master to Slave Slave to Master STATUS 0xA0 Arbitration Lost STATUS 0x68 P Sr Sr P STATU...

Page 417: ...X STA STO SI AA 0 0 1 X I2CnDAT SLA W 0x00 ACK Figure 6 11 13 Flow and Status of General Call Mode Miscellaneous States 6 11 2 6 There are two I2CnSTAT status codes that do not correspond to the 25 de...

Page 418: ...t 0Xa8 Slave Transmit Address ACK 0x18 Master Transmit Address ACK 0Xb0 Slave Transmit Arbitration Lost 0x20 Master Transmit Address NACK 0Xb8 Slave Transmit Data ACK 0x28 Master Transmit Data ACK 0Xc...

Page 419: ...0x28 28H DATA transmitted ACK received if Conti_TX_Data if continuing to send DATA I2DAT NEXT_SEND_DATA2 else if no DATA to be sent STO 1 AA 1 break case 0x30 30H DATA transmitted NACK received STO 1...

Page 420: ...Call received ACK returned AA 0 STA 1 break case 0x80 80H previous own SLA W DATA received ACK returned DATA_RECEIVED2 I2DAT if To_RX_Last_Data2 AA 0 else AA 1 break case 0x88 88H previous own SLA W...

Page 421: ...eceived not addressed SLAVE mode entered AA 1 break case 0Xc8 C8H previous own SLA R last DATA trans mitted ACK received not addressed SLAVE AA 1 mode entered break end of switch I2STAT SI 0 SI should...

Page 422: ...Counter 6 11 5 I 2 C Interrupt There are two I 2 C flags SI and I2TOF Both of them can generate an I 2 C event interrupt requests If I 2 C interrupt mask is enabled via setting EI2 C and EA as 1 CPU w...

Page 423: ...ag When STA is set the I 2 C generates a START condition if the bus is free If the bus is busy the I 2 C waits for a STOP condition and generates a START condition following If STA is set while the I...

Page 424: ...C device is a receiver or an own address matching slave If the AA flag is cleared a NACK high level on I2C0_SDA will be returned during the acknowledge clock pulse of the I2C0_SCL line while the I 2...

Page 425: ...bits of I2STAT are always read as 0 I2DAT I 2 C Data Register SFR Address Reset Value I2DAT BCH Page 0 0000_0000 b 7 6 5 4 3 2 1 0 I2DAT 7 0 R W Bit Name Description 7 0 I2DAT 7 0 I 2 C data I2DAT con...

Page 426: ...hould address I 2 C device by sending the same address in the first byte data after a START or a repeated START condition If the AA flag is set this I 2 C device will acknowledge the master after rece...

Page 427: ...is register determines the clock rate of I 2 C bus when the device is in a master mode The clock rate follows the equation 1 CLK 2 I 4 FSYS The default value will make the clock rate of I 2 C bus 400k...

Page 428: ...EN I 2 C time out counter enable 0 I 2 C time out counter Disabled 1 I 2 C time out counter Enabled Note please always enable I 2 C interrupt when enable I 2 C time out counter function 1 DIV I 2 C ti...

Page 429: ...E SPIEN Internal Data Bus FSYS Write Data Buffer 8 bit Shift Register Read Data Buffer Figure 6 12 1 SPI Block Diagram Figure15 1 SPI Block Diagram shows SPI block diagram It provides an overview of S...

Page 430: ...a general purpose I O However SS can be used as Master Mode Fault detection see chapter 6 12 5 Mode Fault Detection via software setting if multi master environment exists The MS51 also provides auto...

Page 431: ...the data received from the Slave is also transferred in SPInDR User can clear SPIF and read data out of SPInDR Slave Mode 6 12 2 2 When MSTR is 0 the SPI operates in Slave mode The SPCLK pin becomes i...

Page 432: ...an example of LSBFE 0 MSB first Therefore the Slave should shift its MSB data before the first SPCLK edge The falling edge of SS is used for preparing the MSB on MISO line The SS pin therefore should...

Page 433: ...5 SPI Clock and Data Format with CPHA 0 Transfer Progress 1 internal signal SPCLK Cycles SPCLK CPOL 0 MOSI SS output of Master 2 SPIF Master 1 2 3 4 5 6 7 8 SPCLK CPOL 1 MSB MISO 6 5 4 3 2 1 LSB MSB I...

Page 434: ...nerated if ESPI and EA are enabled 6 12 6 Write Collision Error The SPI is signal buffered in the transfer direction and double buffered in the receiving and transmit direction New data for transmissi...

Page 435: ...ure 6 12 7 SPI Overrun Waveform 6 12 8 SPI Interrupt Three SPI status flags SPIF MODF and SPIOVF can generate an SPI event interrupt requests All of them locate in SPInSR SPIF will be set after comple...

Page 436: ...electing external Slave device and goes high during each idle state to de select the Slave device 6 PIEN SPI enable 0 SPI function Disabled 1 SPI function Enabled 5 LSBFE LSB first enable 0 The SPI da...

Page 437: ...FSYS 16 MHz condition Fsys 16 MHz SPR1 SPR0 Divider SPI clock rate 0 0 2 8M bit s 0 1 4 4M bit s 1 0 8 2M bit s 1 1 16 1 M bit s Fsys 24 MHz SPR1 SPR0 Divider SPI clock rate 0 0 2 12M bit s 0 1 4 6M...

Page 438: ...election between adjacent bytes SPIS 1 0 and CPHA select eight grades of SPI interval time selection between adjacent bytes As below table CPHA SPIS1 SPIS0 SPI clock 0 0 0 0 5 0 0 1 1 0 0 1 0 1 5 0 1...

Page 439: ...an overrun event occurs this bit will be set If ESPI and EA are enabled an SPI interrupt will be required This bit should be cleared via software 4 MODF Mode Fault error flag This bit indicates a Mod...

Page 440: ...0000 b 7 6 5 4 3 2 1 0 SPDR 7 0 R W Bit Name Description 7 0 SPDR 7 0 Serial peripheral data This byte is used for transmitting or receiving data on SPI bus A write of this byte is a write to the shif...

Page 441: ...ADC ADCRH ADCRL ADCF ADC result comparator External Trigger VDD ADCEN ADCS ADC XRAM Control ADCBAH ADCSN XRAM Auxiliary RAM ADC Interrupt 1 2 ADC flag Re trigger VREF V REF ADC VDD STADC ADC_CH0 ADC_C...

Page 442: ...et ADCF ADCCON0 7 and generate an interrupt if enabled The new conversion result will also be stored in ADCRH most significant 8 bits and ADCRL least significant 4 bits The 12 bit ADC result value is...

Page 443: ...ADC_ channel analog input ADC_CH15 P2 5 ADC_ channel analog input ADC Conversion Triggered by External Source 6 13 2 2 Besides setting ADCS via software the MS51 32K series is enhanced by supporting h...

Page 444: ...after enabling the result compare function the ADCF register changes to 1 only when ADC comparing result matches the condition and then enters interrupt vector if ADC interrupt is enabled After this...

Page 445: ...ivide 8 bit high byte and 4 bit low nibble data two part Considering to reduce XRAM memory size two 4 bit nibble data continuing ADC conversion results are automatically combine into one byte size and...

Page 446: ...ADC into continues conversion mode 3 Set ADCBAH and ADCBAL registers to configure store address of conversion result 4 Set ADCCN register to configure ADC conversion count 5 Set HIE FIE ADCCON1 5 to e...

Page 447: ...d While this flag is 1 ADC cannot start a new converting This bit is cleared by software 6 ADCS A D converting software start trigger Setting this bit 1 triggers an A D conversion This bit remains log...

Page 448: ...el select This filed selects the activating analog input source of ADC If ADCEN is 0 all inputs are disconnected 0000 ADC_CH0 0001 ADC_CH1 0010 ADC_CH2 0011 ADC_CH3 0100 ADC_CH4 0101 ADC_CH5 0110 ADC_...

Page 449: ...e clock divider value 00 FADCAQT FSYS 1 01 FADCAQT FSYS 2 10 FADCAQT FSYS 4 11 FADCAQT FSYS 8 3 2 ETGTYP 1 0 External trigger type select When ADCEX ADCCON1 1 is set these bits select which condition...

Page 450: ...t to 1 This condition base on ADCMPH ADCMPL and ADCMPOP register define The ADCF register changes to 1 only when ADC comparing result matches the condition and then enters interrupt vector if ADC inte...

Page 451: ...tinue sampling ADC interrupt is set while total A D conversions are completed 3 1 ADCAQT1 ADC acquisition time 1 This 3 bit field decides the acquisition time for ADC AIN9 AIN15 sampling following by...

Page 452: ...7 0 ADC external trigger delay counter low byte This 8 bit field combined with ADCCON2 0 forms a 9 bit counter This counter inserts a delay after detecting the external trigger An A D converting star...

Page 453: ...ddress Reset Value AINDIDS0 F6H Page 0 0000_0000 b 7 6 5 4 3 2 1 0 P11DIDS P03DIDS P04DIDS P05DIDS P06DIDS P07DIDS P30DIDS P17DIDS R W R W R W R W R W R W R W R W Bit Name Description 7 0 AINnDIDS ADC...

Page 454: ...Disconnect Register SFR Address Reset Value AINDIDS1 99H Page 2 0000_0000 b 7 6 5 4 3 2 1 0 P25DIDS P14DIDS P13DIDS P24DIDS P23DIDS P22DIDS P21DIDS Bit Name Description n PnnDIDS ADC Channel digital i...

Page 455: ...CAL REFERENCE MANUAL ADCRH ADC Result High Byte Register SFR Address Reset Value ADCRH C3H Page 0 0000_0000 b 7 6 5 4 3 2 1 0 ADCR 11 4 R Bit Name Description 7 0 ADCR 11 4 ADC result high byte The mo...

Page 456: ...EFERENCE MANUAL ADCRL ADC Result Low Byte Register SFR Address Reset Value ADCRL C2H Page 0 0000_0000 b 7 6 5 4 3 2 1 0 ADCR 3 0 R Bit Name Description 7 4 Reserved 3 0 ADCR 3 0 ADC result low byte Th...

Page 457: ...ERENCE MANUAL ADCMPH ADC Compare High Byte Register SFR Address Reset Value ADCMPH CFH Page 0 0000_0000 b 7 6 5 4 3 2 1 0 ADCMP 11 4 W R Bit Name Description 7 0 ADCMP 11 4 ADC compare high byte The m...

Page 458: ...E MANUAL ADCMPL ADC Compare Low Byte Register SFR Address Reset Value ADCMPL CEH Page 0 0000_0000 b 7 6 5 4 3 2 1 0 ADCMP 3 0 W R Bit Name Description 7 4 Reserved 3 0 ADCMP 3 0 ADC compare low byte T...

Page 459: ...gh Byte Register SFR Address Reset Value ADCBAH 84H Page 2 0000_0000 b 7 6 5 4 3 2 1 0 ADCBAH 3 0 R W Bit Name Description 7 4 Reserved 3 0 ADCBAH 3 0 ADC RAM base address High byte The most significa...

Page 460: ...ress Low Byte Register SFR Address Reset Value ADCBAL 85H Page 2 0000_0000 b 7 6 5 4 3 2 1 0 ADCBAL 7 0 R W Bit Name Description 7 0 ADCBAL 7 0 ADC RAM base address Low byte The least significant 8 bi...

Page 461: ...E MANUAL ADCSN ADC Sampling Number Register SFR Address Reset Value ADCSN 8DH Page 2 0000_0000 b 7 6 5 4 3 2 1 0 ADCSN 7 0 R W Bit Name Description 7 0 ADCSN 7 0 ADC Sampling Number The total sampling...

Page 462: ...CN ADC Current Sampling Number Register SFR Address Reset Value ADCCN 8EH Page 2 0000_0000 b 7 6 5 4 3 2 1 0 ADCCN 7 0 R W Bit Name Description 7 0 ADCCN 7 0 ADC Current Sampling Number The current sa...

Page 463: ...it is set by hardware when ADCMPO ADCCON2 4 flag rising Note This bit can be cleared by writing 0 to it 1 HDONE A D Conversion Half Done Flag This bit is set by hardware when half of ADCSN A D convers...

Page 464: ...2 1 0 SWRF RSTPINF HardF SLOW GF2 UART0PX 0 DPS R W R W R W R W R W R W R R W Bit Name Description 4 SLOW ADC Slow Speed Selection This bit is used to select ADC low speed 0 ADC convert time is high...

Page 465: ...ointers and activating cyclic makes block RAM data move more simple and efficient than only one DPTR The INC AUXR1 instruction is the shortest 2 bytes instruction to accomplish DPTR toggling rather th...

Page 466: ...alue DPL 82H All pages 0000_0000b 7 6 5 4 3 2 1 0 DPL 7 0 R W Bit Name Description 7 0 DPL 7 0 Data pointer low byte This is the low byte of 16 bit data pointer DPL combined with DPH serve as a 16 bit...

Page 467: ...lue DPH 83H All pages 0000_0000b 7 6 5 4 3 2 1 0 DPH 7 0 R W Bit Name Description 7 0 DPH 7 0 Data pointer high byte This is the high byte of 16 bit data pointer DPH combined with DPL serve as a 16 bi...

Page 468: ...0b 7 6 5 4 3 2 1 0 SWRF RSTPINF HardF SLOW GF2 UART0PX 0 DPS R W R W R W R W R W R W R R W Bit Name Description 3 GF2 General purpose flag 2 The general purpose flag that can be set or cleared by the...

Page 469: ...2K SERIES TECHNICAL REFERENCE MANUAL 7 APPLICATION CIRCUIT 7 1 Power Supply Scheme VDD VSS 0 1uF N 10uF 0 1uF EXT_PWR EXT_VSS as close to VDD as possible as close to the EXT_PWR as possible MS51 Serie...

Page 470: ...F nRESET VDD VSS I2 C Device CLK DIO I2C_SDA I2C_SCL DVCC DVCC VDD VSS SPI Device CS CLK MISO SPI_SS MOSI SPI_CLK SPI_MISO SPI_MOSI DVCC 10K 4 7K 4 7K Reset Circuit VDD VSS nRESET ICE_DAT ICE_CLK ICE...

Page 471: ...DD is not adequate performing the Flash reading If an undetermined operating code is read from the program Flash and executed this will put CPU and even the whole system in to an erroneous state After...

Page 472: ...the state keeps longer than 200 us glitch filter The POF will be set 1 Figure 7 3 1 nRESET Reset Waveform shows the nRESET reset waveform nRESET 0 2 VDD 0 7 VDD nRESET Reset 200 us 32 Fsys Clock Figu...

Page 473: ...e MCU if BORST BODCON0 2 setting 1 After a brown out reset BORF BODCON0 1 will be set as 1 via hardware BORF will not be altered by any reset other than a power on reset or brown out reset itself This...

Page 474: ...ck resuming After the system clock is stable MCU will enter the reset state There is a RSTPINF AUXR0 6 flag which indicates an external reset took place After the external reset this bit will be set a...

Page 475: ...his bit keeps unchanged after any reset other than a power on reset or WDT reset itself User can clear WDTRF via software WDCON Watchdog Timer Control Register SFR Address Reset Value WDCON AAH Page 0...

Page 476: ...nger than De glitch time set by LVRDGSEL SYS_BODCTL 14 12 The default setting of Low Voltage Reset is enabled without De glitch function Figure 7 3 4 shows the Low Voltage Reset waveform AVDD VLVR Low...

Page 477: ...ctor BOD Waveform Watchdog Timer Reset WDT 7 3 1 10 In most industrial applications system reliability is very important To automatically recover the MCU from failure status is one way to improve syst...

Page 478: ...8 2019 Page 478 of 491 Rev 1 00 MS51 32K SERIES TECHNICAL REFERENCE MANUAL 8 ELECTRICAL CHARACTERISTICS Please refer to the relative Datasheet for detailed information about the MS51 electrical charac...

Page 479: ...MS51 Nov 28 2019 Page 479 of 491 Rev 1 00 MS51 32K SERIES TECHNICAL REFERENCE MANUAL 9 PACKAGE DIMENSIONS 9 1 QFN 33 pin 4 0 x 4 0 x 0 8 mm Figure 9 1 1 QFN 33 Package Dimension...

Page 480: ...MS51 Nov 28 2019 Page 480 of 491 Rev 1 00 MS51 32K SERIES TECHNICAL REFERENCE MANUAL 9 2 LQFP 32 pin 7 0 x 7 0 x 1 4 mm Figure 9 2 1 LQFP 32 Package Dimension...

Page 481: ...MS51 Nov 28 2019 Page 481 of 491 Rev 1 00 MS51 32K SERIES TECHNICAL REFERENCE MANUAL 9 3 TSSOP 28 pin 4 4 x 9 7 x 1 0 mm Figure 9 3 1 TSSOP 28 Package Dimension...

Page 482: ...MS51 Nov 28 2019 Page 482 of 491 Rev 1 00 MS51 32K SERIES TECHNICAL REFERENCE MANUAL 9 4 TSSOP 20 pin 4 4 x 6 5 x 0 9 mm Figure 9 4 1 TSSOP 20 Package Dimension...

Page 483: ...MS51 Nov 28 2019 Page 483 of 491 Rev 1 00 MS51 32K SERIES TECHNICAL REFERENCE MANUAL 9 5 QFN 20 pin 3 0 x 3 0 x 0 5mm Figure 9 5 1 QFN 20 Package Dimension...

Page 484: ...Hz Internal High Speed RC Oscillator IAP In Application Programming ICP In Circuit Programming ISP In System Programming LDO Low Dropout Regulator LIRC 10 kHz internal low speed RC oscillator LIRC LVR...

Page 485: ...called a one byte instruction In some cases more data is needed which is two or three byte instructions 11 1 Instruction Set And Addressing Modes Table 11 2 1 Instruction Set lists all instructions f...

Page 486: ...24 2 2 6 ADDC A Rn 38 3F 1 2 6 ADDC A direct 35 2 3 4 ADDC A Ri 36 37 1 4 3 ADDC A data 34 2 2 6 SUBB A Rn 98 9F 1 2 6 SUBB A direct 95 2 3 4 SUBB A Ri 96 97 1 4 3 SUBB A data 94 2 2 6 INC A 04 1 1 1...

Page 487: ...46 47 1 4 3 ORL A data 44 2 2 6 ORL direct A 42 2 4 3 ORL direct data 43 3 4 6 XRL A Rn 68 6F 1 2 6 XRL A direct 65 2 3 4 XRL A Ri 66 67 1 4 3 XRL A data 64 2 2 6 XRL direct A 62 2 4 3 XRL direct dat...

Page 488: ...F6 F7 1 3 4 MOV Ri direct A6 A7 2 4 6 MOV Ri data 76 77 2 3 6 MOV DPTR data16 90 3 3 8 MOVC A A DPTR 93 1 4 6 MOVC A A PC 83 1 4 6 MOVX A Ri 1 E2 E3 1 5 4 8 MOVX A DPTR 1 E0 1 4 6 MOVX Ri A 1 F2 F3 1...

Page 489: ...rel 70 2 3 8 JC rel 40 2 3 8 JNC rel 50 2 3 8 JB bit rel 20 3 5 4 8 JNB bit rel 30 3 5 4 8 JBC bit rel 10 3 5 4 8 CJNE A direct rel B5 3 5 4 8 CJNE A data rel B4 3 4 6 CJNE Rn data rel B8 BF 3 4 6 CJN...

Page 490: ...MS51 Nov 28 2019 Page 490 of 491 Rev 1 00 MS51 32K SERIES TECHNICAL REFERENCE MANUAL 12 REVISION HISTORY Date Revision Description 2019 11 28 1 00 Initial release...

Page 491: ...s but is not limited to equipment for surgical implementation atomic energy control instruments airplane or spaceship instruments the control or operation of dynamic brake or safety systems designed f...

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