MS51
Nov. 28, 2019
Page
307
of 491
Rev 1.00
MS51
32K
SE
RIES
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CHNICAL RE
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EREN
CE MA
N
UAL
CAPCON0
– Input Capture Control 0
Register
SFR Address
Reset Value
CAPCON0
92H, Page 0
0000_0000b
7
6
5
4
3
2
1
0
-
CAPEN2
CAPEN1
CAPEN0
-
CAPF2
CAPF1
CAPF0
-
R/W
R/W
R/W
-
R/W
R/W
R/W
Bit
Name
Description
7
-
Reserved
6
CAPEN2
Input capture 2 enable
0 = Input capture channel 2 Disabled.
1 = Input capture channel 2 Enabled.
5
CAPEN1
Input capture 1 enable
0 = Input capture channel 1 Disabled.
1 = Input capture channel 1 Enabled.
4
CAPEN0
Input capture 0 enable
0 = Input capture channel 0 Disabled.
1 = Input capture channel 0 Enabled.
3
-
Reserved
2
CAPF2
Input capture 2 flag
This bit is set by hardware if the determined edge of input capture 2 occurs. This bit should
cleared by software.
1
CAPF1
Input capture 1 flag
This bit is set by hardware if the determined edge of input capture 1 occurs. This bit should
cleared by software.
0
CAPF0
Input capture 0 flag
This bit is set by hardware if the determined edge of input capture 0 occurs. This bit should
cleared by software.