Revision 1.0
VU Computational Instructions
57
VU Computational Instructions
The VU computational instructions adhere to the general format of MIPS
Coprocessor Operate instructions (
COP2
).
Figure 3-7
VU Computational Instruction Format
Most VU computational instructions are three operand:
VD = VS
operation
VT
where each operand is one of 32 vector registers. The
vt
operand can also be
a scalar operand in some instructions, that is, one 16 bit element of the vector
register, as defined in the
element
field. The value written to
vd
is clamped
(saturated) to the minimum and maximum values of the element (-32768 and
+32767 for 16-bit signed elements), before being written.
A vector accumulator register (see “Accumulator” on page 36) is available to
accumulate results over several instructions. The accumulator is modified
by all multiply and some add instructions, but its contents are unchanged
after other VU instructions. The major types of VU computational
instructions are
multiply
,
add
,
select
,
logical
, and
divide
. The upper bits of
the
opcode
field select the instruction type, and are encoded as in Table 3-2.
Table 3-2
VU Computational Instruction Opcode Encoding
Opcode
Instruction
0 0
x x x x
Multiply
0 1
x x x x
Add
1 0 0
x x x
Select
1 0 1
x x x
Logical
1 1 0
x x x
Divide
0
6
11
16
21
25
31
vt
vs
vd
opcode
element
COP2
1
26
24
20
15
10
5
Summary of Contents for Ultra64
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Page 12: ...12 Figure 6 2 buildtask Operation 137 ...
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Page 80: ...80 Vector Unit Instructions vmadm dres_int dres_int vconst 3 vmadn dres_frac vconst vconst 0 ...
Page 104: ...104 RSP Coprocessor 0 ...
Page 150: ...150 Advanced Information ...
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Page 248: ...248 Exceptions None ...
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Page 316: ...316 Exceptions None ...