Nintendo Ultra64, Programmer'S Manual

Page: 54 / 331

54
Vector Unit Instructions
The alignment of various pack formats with VU short elements is shown in
the Figure 3-4
Figure 3-4
Packed Load and Store Alignment
Unsigned pack, half, and fourth items are intended to support unsigned
bytes for one, two, or four channel image data. Pack is a signed byte, for
example for 8 bit audio or geometric normal or difference vectors. The
alignment to the VU short MSB optimizes usage as signed or unsigned
fractions in subsequent VU multiplies.
Transpose
Transpose loads and stores can be used to transpose an 8 by 8 block of shorts
in 16 instructions.
The instructions are
stv, swv,
and
ltv.
Transpose loads and stores
move a 128 bit VU register to and from an aligned 128 bit memory word as
8 16 bit values, one from each VU slice. The VU register number of each slice
is computed as:
(VT & 0x18) | ((Slice + (Element >> 1)) & 0x7)
which is to say,
vt
specifies a base register of an 8 register group. Within that
group, the register address is a function of the slice number and the element
number treated as 0 to 7. A store gathers a diagonal vector of shorts from 8
VU registers into a memory word, or a load scatters a memory word into a
diagonal vector of shorts in 8 VU registers, without writing the other shorts
in each register. Wrap loads and stores perform a circular left shift of the 8
shorts by
(element >> 1)
, which is equivalent to:
0
Memory byte item
VU short element
Pack Upack, Half, Fourth
0 0 14 15 15 7 8
Zero
Zero