NEC VERSA P, Service Manual

Page: 30 / 177

Technical Information 1-15
The BIOS often changes after the product release to provide enhanced features or bug
fixes. To acquire the latest BIOS release, the ROM is flashed electronically allowing the
BIOS update to occur without removing the ROM. See Section 2, Setup and Operation, for
BIOS upgrade procedures.
Peripheral Controller
The PT86C718A chip controls the Peripheral Controller, IDE Interface, and Interrupt Mul-
tiplexer. The chip integrates performance and power-saving features while providing the
following:
n
8-level 64-bit write buffer to VL bus
n
interrupt multiplexing logic
n
reset logic.
VGA Controller
The video architecture is maintained using the C&T65545 Controller and support logic. The
controller supports video standards including EGA and CGA.
This powerful circuitry provides the following features for the system via the controller and
LCD:
n
1-MB VRAM
n
true-color and high-color display capability with 640 x 480 or 800 x 600 resolu-
tion
n
supports LCD resolutions up to 1024 x 768
n
hardware Bit Block Transfers (BITBLT)
n
programmable power management
n
simultaneous LCD/CRT display in 640 x 480 VGA display mode
n
256 color display
n
power management support.
Video Controller Architecture
The video controller architecture is broken down into several modules. The five significant
modules include the sequencer, CRT controller, graphics controller, attribute controller and
dithering engine.
For example, the sequencer manages CPU and display memory timing. The CRT controller
controls sync and timing signals. The graphics controller permits the flow of communication
between the CPU data bus and the 32-bit internal data bus. The attribute controller pro-
duces a 4-bit wide video data stream that refreshes the display.