NEC VERSA P, Service Manual

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1-14 Technical Information
ES688S ESS Technology Audio Controller 100-pin SQFP
System Logic
The PT86C868/PT86C718 Pico Power chips each consist of a 144-pin plastic quad flat-
package. This two-chip controller supports fast graphics and I/O processing. The system
logic controller adds the following features:
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built-in level 2 cache controller
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integrated active power management
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integrated battery management
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high performance DRAM controller.
Flash ROM
The N28F020 flash ROM is a 32-pin, plastic lead chip carrier (PLCC). The chip allows easy
updates to the system's BIOS if needed. More specifically, the ROM is flashed electroni-
cally, installing the latest BIOS revisions to the system. It is possible to reprogram the BIOS
up to 100,000 times. See Section 2, Setup and Operation, for BIOS update procedures.
The N28F020 provides the system upgrade capability as well as the following:
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2048-kilobit (kb) memory
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Quick-Pulse Programming Algorithm
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150 nanoseconds (ns) maximum access time
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ETOX Nonvolatile flash technology
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CMOS low power consumption
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low noise feature.
ROM BIOS
The system uses a Flash ROM known as the system's ROM BIOS to store machine lan-
guage programs. The BIOS size is 256 KB, which consists of 96 KB system utility
(PCMCIA, Auto Setup), 64 KB system BIOS, 32 KB video BIOS, 32 KB power manage-
ment and 32 KB reserved.
The BIOS programs execute the power-on self-test (POST), initialize CPU controllers, and
interact with the LCD indicator panel, diskette drive, hard drive, communication devices
and peripherals. The system BIOS also contains Auto Setup and provides VGA controller
support. The ROM BIOS is copied into RAM (shadowing) for optimum performance.
The ROM BIOS contains both the system and video BIOS. The system BIOS is located in
the upper portion of the device, video BIOS is located in the lower portion. System BIOS is
located between F000h-FFFFh.