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CHAPTER 3 SPECIFICATIONS OF PCI HOST BRIDGE MACRO

Application Note U17121EJ1V1AN

3.8 Timing

The timing for each interface of the PCI host bridge macro is shown below.

3.8.1 External bus interface timing

CPU write/CPU read access is performed from the CPU using the bus interface (Figures 3-6 and 3-7).

When accessing SDRAM from the PCI host bridge macro, bus hold is performed and the main memory is

write/read accessed (Figures 3-8 to 3-10).

Figure 3-6. CPU Write Access

I_CPU_CSx_B

I_CPU_WE_B

I_CPU_WAIT_B

I_CPU_ADR0 to

I_CPU_ADR19

I_CPU_DATA0 to

I_CPU_DATA31

I_CPU_BE_B0 to

I_CPU_BE_B3

I_PCLK

Valid

1111

0000

Remark x = 0 to 2

Figure 3-7. CPU Read Access

I_PCLK

I_CPU_CSx_B

I_CPU_OE_B

I_CPU_WAIT_B

I_CPU_ADR0 to

I_CPU_ADR19

I_CPU_DATA0 to

I_CPU_DATA31

EN_CPU_DATA

I_CPU_BE_B0 to

I_CPU_BE_B3

1111

0000

Valid

Remark x = 0 to 2

Summary of Contents for V850E/MA1

Page 1: ...1st edition Date Published September 2004 N CP K Printed in Japan 2004 V850E MA1 V850E MA2 V850E MA3 V850E ME2 µPD703103A µPD703108 µPD703131A µPD703111A µPD703105A µPD703131AY µPD703106A µPD703132A µPD703106A A µPD703132AY µPD703107A µPD703133A µPD703107A A µPD703133AY µPD70F3107A µPD703134A µPD70F3107A A µPD703134AY µPD70F3134A µPD70F3134AY ...

Page 2: ...Application Note U17121EJ1V1AN 2 MEMO ...

Page 3: ...s including work benches and floors should be grounded The operator should be grounded using a wrist strap Semiconductor devices must not be touched with bare hands Similar precautions need to be taken for PW boards with mounted semiconductor devices STATUS BEFORE INITIALIZATION Power on does not necessarily define the initial status of a MOS device Immediately after the power source is turned ON ...

Page 4: ...om the use of these circuits software and information While NEC Electronics endeavors to enhance the quality reliability and safety of NEC Electronics products customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely To minimize risks of damage to property or injury including death to persons arising from defects in NEC Electronics products customers mu...

Page 5: ...Branch Seoul Korea Tel 02 558 3737 NEC Electronics Shanghai Ltd Shanghai P R China Tel 021 5888 5400 NEC Electronics Taiwan Ltd Taipei Taiwan Tel 02 2719 2377 NEC Electronics Singapore Pte Ltd Novena Square Singapore Tel 6253 8311 J04 1 NEC Electronics Europe GmbH Duesseldorf Germany Tel 0211 65030 Sucursal en España Madrid Spain Tel 091 504 27 87 Vélizy Villacoublay France Tel 01 30 67 58 00 Succ...

Page 6: ...have general knowledge in the fields of electrical engineering logic circuits and microcontrollers For details of the hardware functions and electrical specifications of the V850E MA1 V850E MA2 V850E MA3 and V850E ME2 Refer to the Hardware User s Manual of each product For details of the instruction functions of the V850E MA1 V850E MA2 V850E MA3 and V850E ME2 Refer to the V850E1 Architecture User ...

Page 7: ...ent tools user s manuals Document Name Document No IE V850E MC IE V850E MC A In Circuit Emulator U14487E IE 703107 MC EM1 In Circuit Emulator Option Board U14481E IE V850E1 CD NW PCMCIA Card Type On Chip Debug Emulator U16647E Operation U16053E C Language U16054E CA850 Ver 2 50 C Compiler Package Assembly Language U16042E PM plus Ver 5 20 U16934E ID850 Ver 2 50 Integrated Debugger Operation U16217...

Page 8: ...r 36 3 4 3 PCI_CONTROL register 37 3 4 4 PCI_IO_BASE register 38 3 4 5 PCI_MEM_BASE register 38 3 4 6 PCI_INT_CTL register 39 3 4 7 PCI_ERR_ADD register 40 3 4 8 SYSTEM_MEM_BASE register 41 3 4 9 SYSTEM_MEM_RANGE register 41 3 4 10 SDRAM_CTL register 42 3 5 Address Map 44 3 6 Initializing PCI Host Bridge Macro 45 3 7 Bus Width of External Bus Interface 46 3 8 Timing 47 3 8 1 External bus interface...

Page 9: ...2 PCI bus interface timing parameters as constraint of PCI CLK 33 MHz 65 4 6 3 SDRAM interface timing 66 CHAPTER 5 APPLICATION EXAMPLES 67 5 1 Block Diagram of Evaluation Board 67 5 2 Specifications of Evaluation Board 68 5 3 Example of Evaluation Board Connection Circuit 69 5 4 Evaluation Board Memory Space 70 5 5 Sample Program Examples 72 5 5 1 Development tools 72 5 5 2 Program configuration 7...

Page 10: ...MA2 V850E MA3 and V850E ME2 are 32 bit single chip microcontrollers that integrate the V850E1 CPU which is a 32 bit RISC type CPU core for ASIC newly developed as the CPU core central to system LSI in the current age of system on chip These devices incorporate memory and various peripheral functions such as memory controllers a DMA controller timer counters serial interfaces and an A D converter f...

Page 11: ... ch TMQ 1 ch Interval timer 4 ch 4 ch 4 ch 4 ch 16 bit timer Up down counter 1 ch 2 ch Watchdog timer 1 ch CSI 1 ch 1 ch UART 1 ch 1 ch CSI UART 2 ch 2 ch 3 ch 1 ch Serial interface UART I 2 C 1 ch Note 2 10 bit A D converter 8 ch 4 ch 8 ch 8 ch 8 bit D A converter 2 ch DMA controller 4 ch 4 ch 4 ch 4 ch CMOS input 9 5 11 7 Ports CMOS I O 106 74 101 77 Debug functions Provided RUN break Provided R...

Page 12: ...k ROM 128 KB µPD703106AF1 xxx EN4 161 pin plastic FBGA 13 13 Mask ROM 128 KB µPD703107AGJ xxx UEN 144 pin plastic LQFP fine pitch 20 20 Mask ROM 256 KB µPD703107AGJ A xxx UEN 144 pin plastic LQFP fine pitch 20 20 Mask ROM 256 KB µPD703107AF1 xxx EN4 161 pin plastic FBGA 13 13 Mask ROM 256 KB µPD70F3107AGJ UEN 144 pin plastic LQFP fine pitch 20 20 Flash memory 512 KB µPD70F3107AGJ A UEN 144 pin pla...

Page 13: ... 20 Mask ROM 512 KB µPD703133AYF1 xxx EN4 161 pin plastic FBGA 13 13 Mask ROM 512 KB µPD703134AGJ xxx UEN 144 pin plastic LQFP fine pitch 20 20 Mask ROM 512 KB µPD703134AF1 xxx EN4 161 pin plastic FBGA 13 13 Mask ROM 512 KB µPD703134AYGJ xxx UEN 144 pin plastic LQFP fine pitch 20 20 Mask ROM 512 KB µPD703134AYF1 xxx EN4 161 pin plastic FBGA 13 13 Mask ROM 512 KB µPD70F3134AGJ UEN 144 pin plastic L...

Page 14: ...4 ANI4 P75 ANI5 P76 ANI6 P77 ANI7 V DD V SS TC3 INTP113 P27 TC2 INTP112 P26 TC1 INTP111 P25 TC0 INTP110 P24 TO02 P23 INTP021 P22 TI020 INTP020 P21 NMI P20 V DD V SS ADTRG INTP123 P37 INTP122 P36 INTP121 P35 RXD2 INTP120 P34 TXD2 INTP133 P33 SCK2 INTP132 P32 SI2 INTP131 P31 SO2 INTP130 P30 MODE1 MODE0 RESET CKSEL CV DD X2 X1 CV SS SCK1 P45 RXD1 SI1 P44 TXD1 SO1 P43 SCK0 P42 RXD0 SI0 P41 TXD0 SO0 P4...

Page 15: ...5 PAL5 B12 SDCLK PCD1 D6 A10 PAL10 A5 B13 CS1 RAS1 PCS1 D7 A14 PAL14 A6 A9 PAL9 B14 D8 A16 PAH0 A7 A12 PAL12 C1 D9 A20 PAH4 A8 A15 PAL15 C2 D9 PDL9 D10 A23 PAH7 A9 A17 PAH1 C3 D13 PDL13 D11 SDCKE PCD0 A10 C4 A1 PAL1 D12 CS0 PCS0 A11 A24 PAH8 C5 A7 PAL7 D13 CS5 IORD PCS5 A12 VDD C6 VDD D14 A13 LBE SDCAS PCD2 C7 A11 PAL11 E1 D5 PDL5 A14 UBE SDRAS PCD3 C8 VDD E2 D7 PDL7 B1 C9 A19 PAH3 E3 D8 PDL8 B2 D...

Page 16: ...4 OE PCT6 L8 SI2 INTP131 P31 N12 AVDD AVREF H1 DMARQ2 INTP102 P06 L9 RESET N13 AVSS H2 DMARQ1 INTP101 P05 L10 TXD1 SO1 P43 N14 H3 DMARQ0 INTP100 P04 L11 ANI7 P77 P1 VDD H4 D1 PDL1 L12 ANI4 P74 P2 VSS H11 REFRQ PCM4 L13 ANI3 P73 P3 TC1 INTP111 P25 H12 HLDRQ PCM3 L14 ANI2 P72 P4 INTP021 P22 H13 HLDAK PCM2 M1 P5 H14 CLKOUT BUSCLK PCM1 M2 INTP011 P12 P6 INTP121 P35 J1 TO00 P03 M3 TO01 P13 P7 SCK2 INTP...

Page 17: ... SDRAS PCS0 CS0 PCS3 CS3 PCS4 CS4 PCS7 CS7 PCT0 LWR LDQM PCT1 UWR UDQM PCT4 RD PCT5 WE PCM0 WAIT PCM1 CLKOUT PCM2 HLDAK PCM3 HLDRQ PCM4 REFRQ VSS VDD P70 ANI0 P71 ANI1 P72 ANI2 P73 ANI3 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 PAL2 A2 PAL3 A3 PAL4 A4 PAL5 A5 PAL6 A6 PAL7 A7 V SS V DD PAL8 A8 PAL9 A9 PAL10 A10 PAL11 A11 PAL12 A12 PAL13 A13 PAL14 A14 PAL15 A15 V SS...

Page 18: ... TOP21 P20 NMI P37 INTP137 ADTRG VSS VDD P70 ANI0 P71 ANI1 P72 ANI2 P73 ANI3 P74 ANI4 P75 ANI5 P76 ANI6 P77 ANI7 EV DD EV SS DMAAK3 PBD3 DMAAK2 PBD2 DMAAK1 PBD1 DMAAK0 PBD0 INTP022 TOP11 INTPP11 P22 INTP021 TOP10 EVTP1 TIP1 INTPP10 P21 INTP134 RXD3 SCL Note P34 INTP133 TXD3 SDA Note P33 INTP132 ASCK2 SCK2 P32 INTP131 RXD2 SI2 P31 INTP130 TXD2 SO2 P30 ASCK1 SCK1 P45 RXD1 SI1 P44 TXD1 SO1 P43 ASCK0 ...

Page 19: ...AD15 PDL15 B9 A18 PAH2 D2 AD10 PDL10 A3 A2 PAL2 B10 A21 PAH5 D3 AD14 PDL14 A4 A5 PAL5 B11 A25 PAH9 D4 A3 PAL3 A5 EVSS B12 SDCLK PCD1 D5 A6 PAL6 A6 A9 PAL9 B13 CS1 PCS1 D6 A10 PAL10 A7 A12 PAL12 B14 EVSS D7 A14 PAL14 A8 A15 PAL15 C1 EVSS D8 A16 PAH0 A9 A17 PAH1 C2 AD9 PDL9 D9 A20 PAH4 A10 C3 AD13 PDL13 D10 A23 PAH7 A11 A24 PAH8 C4 A1 PAL1 D11 SDCKE PCD0 A12 EVDD C5 A7 PAL7 D12 CS0 PCS0 A13 SDCAS PC...

Page 20: ...11 ANO1 P81 G12 WR WE PCT5 L7 ASCK1 SCK1 P45 N12 AVSS1 G13 BCYST PCT7 L8 TXD0 SO0 P40 N13 AVDD1 G14 ASTB PCT6 L9 MODE0 N14 H1 TOQB3 INTP115 EVTQ P15 L10 AVDD0 P1 EVDD H2 TOQB2 INTP114 TIQ P14 L11 ANI7 P77 P2 EVSS H3 TOQT3 INTP013 INTPQ3 TOQ3 P13 L12 ANI4 P74 P3 DMAAK1 PBD1 H4 AD1 PDL1 L13 ANI3 P73 P4 TOP10 INTPP10 EVTP1 TIP1 INTP021 P21 H11 REFRQ PCM4 L14 ANI2 P72 P5 EVSS H12 HLDRQ PCM3 M1 EVSS P6...

Page 21: ...1 PLLV SS PLLV DD OSCV SS X2 X1 OSCV DD UV DD UDM UDP P10 UCLK INTP10 IV SS IV DD PLLSEL P11 SCK0 INTP11 P12 RXD0 SI0 P13 TXD0 SO0 P20 NMI EV SS EV DD P21 RXD1 INTP21 P22 TXD1 INTP22 P23 SCK1 INTP23 P24 SI1 INTP24 P25 SO1 INTP25 DCK DMS DRST DDI DDO TRCCLK TRCEND TRCDATA0 TRCDATA1 IV SS IV DD TRCDATA2 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 7...

Page 22: ... U17121EJ1V1AN 22 240 pin plastic FBGA 16 16 µPD703111AF1 10 GA3 µPD703111AF1 13 GA3 µPD703111AF1 15 GA3 Bottom View Top View 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Index mark E F G H J K L M N P R T U V A B C D P N M L K J H G F E D C B A V U T R ...

Page 23: ...J5 D13 B4 D15 J14 B5 PCT3 UUWR UUBE UUDQM D16 PCS2 CS2 IOWR J15 P50 INTP50 DMARQ0 B6 PCT7 BCYST D17 PCS3 CS3 J16 P51 INTP51 DMAAK0 B7 A2 D18 EVDD J17 P52 INTP52 TC0 B8 E1 D3 J18 P53 INTPC00 TIC0 DMARQ1 B9 A8 E2 D2 K1 D14 B10 A12 E3 D1 K2 D15 B11 PAH0 A16 E4 K3 PDH0 D16 INTPD0 B12 E8 A3 K4 PDH1 D17 INTPD1 B13 E9 A5 K5 PDH2 D18 INTPD2 TOC4 B14 E10 A10 K14 P55 TOC0 TC1 B15 E11 PAH1 A17 K15 P54 INTPC0...

Page 24: ...RQ2 N18 ANI5 T3 U18 P1 T4 TRCDATA1 V1 P2 PDH11 D27 INTPD11 INTP111 TCLR11 T5 TRCEND V2 TRCDATA2 P3 PDH13 D29 INTPD13 TIUD11 T6 DDI V3 IVSS P4 T7 V4 TRCDATA0 P8 P23 INTP23 SCK1 T8 P21 INTP21 RXD1 V5 P9 P12 SI0 RXD0 T9 P20 NMI V6 DMS P10 T10 V7 P24 INTP24 SI1 P11 UVDD T11 UDP V8 P15 T12 X1 V9 P13 SO0 TXD0 P16 ANI0 T13 OSCVSS V10 PLLSEL P17 ANI1 T14 SSEL1 V11 P10 INTP10 UCLK P18 T15 P75 INTPC30 TIC3 ...

Page 25: ...P37 P21 to P27 P20 P10 to P13 P00 to P07 CG System controller BCU CLKOUT CKSEL X1 X2 CVDD CVSS MODE0 MODE1 MODE2 VPP Note 3 RESET VDD VSS UART0 CSI0 UART1 CSI1 UART2 CSI2 ADC SO0 TXD0 SI0 RXD0 SCK0 SO1 TXD1 SI1 RXD1 SCK1 TXD2 RXD2 PWM0 SO2 SI2 SCK2 ANI0 to ANI7 AVREF AVDD AVSS ADTRG Instruction queue MEMC HLDRQ HLDAK CS0 CS7 CS1 RAS1 CS3 RAS3 CS4 RAS4 CS6 RAS6 CS2 IORD CS5 IOWR SELFREF REFRQ BCYST...

Page 26: ...5 PAH0 to PAH8 PCS0 PCS3 PCS4 PCS7 PCT0 PCT1 PCT4 PCT5 PCM0 to PCM4 PCD0 to PCD3 PBD0 PBD1 P70 to P73 P40 to P45 P24 P20 P11 P12 P01 to P05 CG System controller BCU CLKOUT CKSEL X1 X2 CVDD CVSS MODE0 to MODE2 RESET VDD VSS UART0 CSI0 UART1 CSI1 ADC TXD0 SO0 RXD0 SI0 SCK0 TXD1 SO1 RXD1 SI1 SCK1 ANI0 to ANI3 AVREF AVDD AVSS Instruction queue MEMC HLDRQ HLDAK CS0 CS3 CS4 CS7 REFRQ LBE SDCAS UBE SDRAS...

Page 27: ...OP20 TOP21 TXD2 SO2 RXD2 SI2 ASCK2 SCK2 UARTA2 CSIB2 ADTRG TXD0 SO0 RXD0 SI0 ASCK0 SCK0 TXD1 SO1 RXD1 SI1 ASCK1 SCK1 AVDD0 AVSS0 AVDD1 AVSS1 Instruction queue MEMC WAIT HLDRQ HLDAK BUSCLK A0 to A25 AD0 to AD15 CS0 to CS7 BCYST RD UWR LWR UBE LBE WR ASTB IORD IOWR SDCLK SDCKE SDRAS SDCAS WE LDQM UDQM REFRQ SRAM ROM DMAC SDRAM WDT UARTA3 I2 CNote 3 TXD3 SDANote 3 RXD3 SCLNote 3 DMARQ0 to DMARQ3 DMAA...

Page 28: ...o DMARQ3 DMAAK0 to DMAAK3 TC0 to TC3 CS0 CS1 CS3 CS4 CS6 CS7 CS2 IOWR CS5 IORD BCYST RD ANI0 to ANI7 ADTRG AVREFP AVREFM AVDD AVSS RESET MODE0 MODE1 IVDD IVSS EVDD EVSS PWM0 PWM1 UDP UDM UCLK UVDD xxWR xxBE WR BUSCLK SDCKE SDRAS SDCAS WE xxDQM REFRQ SELFREF DDO TRCCLK TRCDATA0 to TRCDATA3 TRCEND INTP100 INTP110 INTP101 INTP111 INTP10 INTP11 INTP21 to INTP25 INTP50 to INTP52 INTP65 to INTP67 INTPD0...

Page 29: ...us interfaces to the PCI bus interface This chapter gives an outline of the PCI host bridge macro 2 1 Outline The PCI host bridge macro is a bridge control macro that connects V850E MA1 V850E MA2 V850E MA3 V850E ME2 external bus interfaces memory controller MEMC to the PCI bus interface The main memory SDRAM can be directly controlled when SDRAM is accessed from a PCI device ...

Page 30: ...st bridge macro selectable from the last accessed master PCI bus error processing An error interrupt is generated for master abort target abort PERR reception SERR reception The address immediately before an error occurs is retained PCI bus address conversion control PCI I O address and PCI memory address registers are supported to convert the physical addresses from the CPU to addresses for the P...

Page 31: ... a memory data transfer request from the PCI device and issues an access request to SDRAMC 3 SDRAMC External bus interface SDRAM controller This controller is connected to the SDRAM bus A memory request from the PCI device via the LS_BRIDGE block is transferred by activating the SDRAM bus When the bus width of SDRAM is 16 bits memory cycles of up to 8 bursts are started When the bus width is 32 bi...

Page 32: ...B O_DEVSEL_B EN_DEVSEL I_TRDY_B O_TRDY_B EN_TRDY I_STOP_B O_STOP_B EN_STOP I_PAR O_PAR EN_PAR I_PERR_B O_PERR_B EN_PERR I_SERR_B I_REQ_B1 to I_REQ_B7 O_GNT_B1 to O_GNT_B7 I_SRST_B I_CPU_CS0_B I_CPU_CS1_B I_CPU_CS2_B I_CPU_ADR0 to I_CPU_ADR19 I_CPU_DATA0 to I_CPU_DATA31 O_CPU_DATA0 to O_CPU_DATA31 EN_CPU_DATA I_CPU_BE_B0 to I_CPU_BE_B3 I_CPU_WE_B I_CPU_OE_B O_CPU_WAIT_B O_PCIHOST_INT I_MODE16 O_HOL...

Page 33: ...dge interrupt output Low I_MODE16 Input CPU data bus width select input Low 32 bit width High 16 bit width 3 3 2 SDRAM bus interface pins Pin Name I O Function Active O_HOLDREQ_B Output SDRAM bus hold request output Low I_HOLDACK_B Input SDRAM bus hold acknowledge input Low I_SDCLK Input SDRAM clock input O_SD_DATA0 to O_SD_DATA31 Output SDRAM data output I_SD_DATA0 to I_SD_DATA31 Input SDRAM data...

Page 34: ...w EN_IRDY Output PCI initiator ready output enable output Output buffer enable of O_IRDY_B High I_DEVSEL_B Input PCI device select input Low O_DEVSEL_B Output PCI device select output Low EN_DEVSEL Output PCI device select output enable output Output buffer enable of O_DEVSEL_B High I_TRDY_B Input PCI target ready input Low O_TRDY_B Output PCI target ready output Low EN_TRDY Output PCI target read...

Page 35: ...H PCI_MEM_BASE R W Sets base address of PCI bus memory space accessed from PCI memory area on CPU memory map 18H PCI_INT_CTL R W PCI error interrupt control 1CH PCI_ERR_ADD R PCI error generation address retention 20H to 3FH Reserved 40H SYSTEM_MEM_BASE R W Sets base address of system memory area mapped to PCI bus memory space 44H SYSTEM_MEM_RANGE R W Sets range of system memory area mapped to PCI...

Page 36: ...nal connected to the IDSEL pin of each PCI device is specified in this field For example if the AD31 signal is connected to the IDSEL pin of a PCI device access is enabled by setting bit 31 of CADD to 1 Function number Specifies the function number for a multifunction device Register number Specifies the number of the access target PCI configuration register b Type 1 PCI PCI bridge 31 24 23 16 15 ...

Page 37: ...rformed seven clocks after the bus status becomes IDLE The counter is started when FRAME High and IRDY High PCI_BPMODE R W Sets the bus parking master 0 Limited to this macro 1 Master accessed last PCI_REQ R W Enables disables the REQ signal I_REQ_B1 to I_REQ_B7 pins from the bus master Bit 0 of this field bit 8 of the PCI_CONTROL register is assigned to the PCI host bridge macro and is always 1 0...

Page 38: ...U_CS1_B pin becomes active from the CPU 3 4 5 PCI_MEM_BASE register When memory accessing the PCI bus memory space via the PCI memory area area in which the I_CPU_CS2_B pin becomes active 1 MB any area of the 4 GB PCI bus memory space can be accessed by setting this register However because the main memory SDRAM is mapped on the PCI bus memory space do not overlap the area set by the SYSTEM_MEM_BA...

Page 39: ...upt 1 Cleared CLR_MAB W Clears the PCI bus master abort interrupt 1 Cleared CLR_TAB W Clears the PCI bus target abort interrupt 1 Cleared MSK_SERR R W Sets the mask status of the PCI bus system error SERR reception interrupt 0 Not masked 1 Masked MSK_PERR R W Sets the mask status of the PCI bus parity error PERR reception interrupt 0 Not masked 1 Masked MSK_MAB R W Sets the mask status of the PCI ...

Page 40: ...t Target abort When the PCI_ERR_ADD register is read all the bits are cleared Once an error occurs and a value is set to the PCI_ERR_ADD register the first value is retained until read access is performed or a new error occurs and the value is updated This function is used only for debugging and is not used in normal operation After reset 00000000H R Offset address 1CH 31 0 ERR_ADR Bit Name R W Fu...

Page 41: ...5 0 S_BASE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Name R W Function S_BASE R W Sets the higher 16 bits bits 16 to 31 of the base address on the PCI bus memory space in which the main memory SDRAM is mapped 3 4 9 SYSTEM_MEM_RANGE register After reset 0000FFFFH R W Offset address 44H 31 16 15 0 S_RANGE 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit Name R W Function S_RANGE R W Sets the range of the PCI bus memor...

Page 42: ...uccessive main memory SDRAM accesses from the PCI device A latency of up to 7 650 ns can be set 00H No latency 01H 1 PCI clock 30 ns FFH 255 PCI clocks 7 650 ns BUS_SIZE R W Sets the bit width of the data bus 0 16 bit width 1 32 bit width CAS_LATENCY R W Sets the CAS latency 00 Setting prohibited 01 1 10 2 11 3 WAIT_STATE R W Sets the wait interval of ACT CMD PRE ACT and CMD ACT 00 Setting prohibi...

Page 43: ...16 15 14 13 12 11 11 11 bits 25 to 18 17 16 15 25 24 23 22 21 20 19 18 17 16 15 14 13 12 Table 3 2 Column Address Output Precharge Command Correspondence Between PCI Bus Address Signal and Main Memory SDRAM Address Pins O_SD_ADR1 to O_SD_ADR25 BUS_SIZE Bit Setting Value 25 to 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 16 bits 25 to 18 17 16 15 14 12 11 H 10 9 8 7 6 5 4 3 2 1 1 32 bits 25 to 18...

Page 44: ... O area FFFFH 0000H FFFF FFFFH IO_BASE 31 16 FFFFH IO_BASE 31 16 0000H 0000 0000H 64 KB PCI bus I O space 64 KB Figure 3 4 CPU Memory Space PCI Bus Memory Space Address Map PCI bus memory space CPU memory space I_CPU_CS2_B area Main memory SDRAM area Main memory space PCI memory area FFFFFH 00000H FFFF FFFFH M_BASE 31 16 FFFFFH M_BASE 31 16 00000H S_BASE 31 16 S_RANGE 31 16 FFFFH S_BASE 31 16 S_RA...

Page 45: ...ng PCI I O area setting PCI memory area setting PCI_MEM_BASE register Set any address to M_BASE field PCI_I O_BASE register Set any address to I O_BASE field PCI_CONTROL register Set MEM_EN and IO_EN bits to 11 SDRAM_CTL register Set bit width of column address to COLUMN_SIZE field Set number of wait clocks to WAIT_STATE field Set CAS latency to CAS_LATENCY field Set BUS_SIZE bit to bit width of d...

Page 46: ...face use the BUS_SIZE bit in 3 4 10 SDRAM_CTL register 3 The setting of the I_MODE16 pin should correspond with the external bus interface operation mode of the CPU 4 When 16 bit mode is set the access cycle is divided for 32 bit access on the external bus interface Accordingly access is divided similarly on the PCI bus interface Therefore when 16 bit mode is set because a 32 bit access cycle is n...

Page 47: ...RAM from the PCI host bridge macro bus hold is performed and the main memory is write read accessed Figures 3 8 to 3 10 Figure 3 6 CPU Write Access I_CPU_CSx_B I_CPU_WE_B I_CPU_WAIT_B I_CPU_ADR0 to I_CPU_ADR19 I_CPU_DATA0 to I_CPU_DATA31 I_CPU_BE_B0 to I_CPU_BE_B3 I_PCLK Valid Valid 1111 1111 0000 Remark x 0 to 2 Figure 3 7 CPU Read Access I_PCLK I_CPU_CSx_B I_CPU_OE_B I_CPU_WAIT_B I_CPU_ADR0 to I...

Page 48: ...RAM control signal output Figure 3 9 Main Memory SDRAM Write Access 8 Burst I_SDCLK O_HOLDREQ_B I_HOLDACK_B O_SD_CS_B O_SD_RAS_B O_SD_CAS_B O_SD_WR_B O_SD_DQM_B0 to O_SD_DQM_B3 O_SD_DATA0 to O_SD_DATA31 O_SD_ADR1 to O_SD_ADR25 1111 1111 RA WD0 WD1 CA1 CA0 CA2 CA3 CA4 CA5 CA6 CA7 WD2 WD3 WD4 WD5 WD6 WD7 Remark SDRAM_CTL register WAIT_STATE field 10 CAS_LATENCY field 10 ...

Page 49: ...ad Access 8 Burst I_SDCLK O_HOLDREQ_B I_HOLDACK_B O_SD_CS_B O_SD_RAS_B O_SD_CAS_B O_SD_WR_B O_SD_DQM_B0 to O_SD_DQM_B3 I_SD_DATA0 to I_SD_DATA31 O_SD_ADR1 to O_SD_ADR25 1111 1111 RA RD0 RD1 CA1 CA0 CA2 CA3 CA4 CA5 CA6 CA7 RD2 RD3 RD4 RD5 RD6 RD7 0000 Remark SDRAM_CTL register WAIT_STATE field 10 CAS_LATENCY field 10 ...

Page 50: ...rom the CPU to the PCI device is shown below a Configuration read write cycle I O read write cycle and memory read write cycle i Read cycle Timing type Configuration register read internal I O register read memory read Figure 3 11 Read Cycle AD H DEVSEL TRDY FRAME STOP IRDY PCICLK ii Write cycle Timing type Configuration register write internal I O register write memory write Figure 3 12 Write Cyc...

Page 51: ...e U17121EJ1V1AN 51 b Target abort cycle Timing type Target abort Figure 3 13 Target Abort Cycle AD H DEVSEL TRDY FRAME STOP IRDY PCICLK c Master abort cycle Timing type Master abort cycle Figure 3 14 Master Abort Cycle AD H H H DEVSEL TRDY PAR FRAME STOP IRDY PCICLK ...

Page 52: ...cycle data parity error Figure 3 15 Data Parity Error AD DEVSEL TRDY PAR FRAME STOP IRDY PCICLK PERR H 2 PCI bus slave cycle timing The timing of access from the PCI device to SDRAM is shown below a Memory single read cycle Timing type Memory single read cycle Figure 3 16 Single Read Cycle AD DEVSEL TRDY REQ FRAME STOP IRDY PCICLK GNT ...

Page 53: ...ingle write cycle Timing type Memory single write cycle Figure 3 17 Single Write Cycle AD DEVSEL TRDY REQ FRAME STOP IRDY PCICLK GNT c Burst read cycle Timing type Memory burst read cycle Not disconnect Figure 3 18 Burst Read Cycle AD 0 1 2 3 4 5 6 7 DEVSEL TRDY REQ FRAME STOP IRDY PCICLK GNT H ...

Page 54: ...ite cycle Timing type Memory burst write cycle Not disconnect Figure 3 19 Burst Write Cycle AD 0 1 2 3 4 5 6 7 DEVSEL TRDY REQ FRAME STOP IRDY PCICLK GNT H e Abort cycle Timing type Target abort cycle master abort cycle Figure 3 20 Abort Cycle AD DEVSEL TRDY REQ FRAME STOP IRDY PCICLK GNT SERR H ...

Page 55: ... data parity error 1 Timing type Single read cycle data parity error Figure 3 21 Read Data Parity Error AD DEVSEL TRDY PAR FRAME STOP IRDY PCICLK PERR H ii Read data parity error 2 Timing type Burst read cycle data parity error Figure 3 22 Read Data Parity Error 2 AD DEVSEL TRDY PAR FRAME STOP IRDY PCICLK PERR ...

Page 56: ...r 1 Timing type Single write cycle data parity error Figure 3 23 Write Data Parity Error 1 AD DEVSEL TRDY PAR FRAME STOP IRDY PCICLK PERR H SERR iv Write data parity error 2 Timing type Burst write cycle data parity error Figure 3 24 Write Data Parity Error 2 AD DEVSEL TRDY PAR FRAME STOP IRDY PCICLK PERR SERR ...

Page 57: ...select from the address before creation I_CPU_CS0_B PCI host bridge register chip select Offset address in 3 4 Registers I_CPU_CS1_B PCI I O area chip select See Figure 3 3 CPU Memory Space PCI Bus I O Space Address Map I_CPU_CS2_B PCI memory area chip select See Figure 3 4 CPU Memory Space PCI Bus Memory Space Address Map 2 Because the buffers of the address bus and data bus for the expansion bus...

Page 58: ...SD_ADR1 to O_SD_ADR25 CBE0 to CBE3 O_SD_DQM_B0 to O_SD_DQM_B3 O_SD_CKE O_SD_CS_B O_SD_RAS_B O_SD_CAS_B O_SD_WR_B EN_SD_CTL I_SD_DATA0 to I_SD_DATA31 O_CPU_DATA0 to O_CPU_DATA31 O_SD_DATA0 to O_SD_DATA31 EN_CPU_DATA I_CPU_BE_B0 to I_CPU_BE_B3 I_CPU_DATA0 to I_CPU_DATA31 I_REQ_B1 REQ1 O_GNT_B3 to O_GNT_B7 EN_FRAME I_FRAME_B O_FRAME_B FRAME I_SERR_B SERR I_REQ_B2 REQ2 I_REQ_B3 to I_REQ_B7 EN_IRDY I_I...

Page 59: ... Input CPU data byte enable input WRZ Input CPU data write enable input RDZ Input CPU data read enable input WAITZ Output CPU data wait output INT0 Output PCI host bridge interrupt output 4 4 2 SDRAM bus interface pins Pin Name I O Function HLDREQZ Output SDRAM bus hold request output HLDACKZ Input SDRAM bus hold acknowledge input SDCLK Input SDRAM clock input SDCKE Output SDRAM clock enable outpu...

Page 60: ...31 I O PCI address data I O CBE0 to CBE3 I O PCI command byte enable I O FRAME I O PCI frame I O IRDY I O PCI initiator ready I O DEVSEL I O PCI device select I O TRDY I O PCI target ready I O STOP I O PCI stop I O PAR I O PCI parity I O PERR I O PCI parity error I O SERR Input PCI system error input REQ1 REQ2 Input PCI request input GNT1 GNT2 Output PCI grant output INT1 INT2 Output PCI INTA INTB...

Page 61: ...0 RA1 to RA25 External bus interface A0 Selector Address decoder O_SD_ADR1 to O_SD_ADR25 I_CPU_DATA0 to I_CPU_DATA31 I_SD_DATA0 to I_SD_DATA31 O_CPU_DATA0 to O_CPU_DATA31 O_SD_DQM_B0 to O_SD_DQM_B3 I_CPU_BE_B0 to I_CPU_BE_B3 O_SD_DATA0 to O_SD_DATA31 I_CPU_OE_B O_SD_WR_B O_CPU_WAIT_B I_HOLDACK_B I_SDCLK O_PCIHOST_INT O_HOLDRQ_B O_SD_CKE O_SD_CS_B O_SD_RAS_B O_SD_CAS_B EN_SD_CTL Selector EN_CPU_DAT...

Page 62: ...to O_CBE3 I_REQ_B1 I_REQ_B2 I_REQ_B3 to I_REQ_B7 O_GNT_B3 to O_GNT_B7 EN_FRAME I_FRAME_B O_FRAME_B CLK PCLK I_SERR_B SERR SERR C BE0 to C BE3 CBE0 to CBE3 PCIRST RST AD0 to AD31 AD0 to AD31 FRAME FRAME EN_IRDY I_IRDY_B O_IRDY_B IRDY IRDY EN_DEVSEL I_DEVSEL_B O_DEVSEL_B DEVSEL DEVSEL EN_TRDY I_TRDY_B O_TRDY_B TRDY TRDY EN_STOP I_STOP_B O_STOP_B STOP STOP EN_PAR I_PAR O_PAR PAR PAR GNT1 GNT2 GNT1 GN...

Page 63: ...M2 RA2 to RA14 RA24 RA25 RD0 to RD31 BENZ0 to BENZ3 WRZ SDCKE SDCS SDRASZ SDCASZ SDCLK RDZ WAITZ INT0 HLDRQZ HLDAKZ RESET V850E ME2 HLDAK HLDRQ INTPxxx WAIT RD A0 to A22 A24 A25 D0 to D31 xxBE xxDQM WR WE SDCKE CSx SDRAS SDCAS BUSCLK A0 to A12 BA0 BA1 DQ0 to DQ31 DQM0 DQM1 WE CKE CS RAS CAS CLK DQM2 DQM3 Remarks 1 This is an example using two SDRAMs of 4 M words 16 bits 4 banks row address 13 bits...

Page 64: ...t bridge PCI device 1 AD00 to AD31 CBE0 to CBE3 PCIRST FRAME IRDY DEVSEL TRDY STOP PAR PERR SERR REQ1 GNT1 AD00 to AD31 IDSELNote C BE0 to C BE3 RST FRAME IRDY DEVSEL TRDY STOP PAR PERR SERR REQ GNT CLK AD00 to AD31 IDSELNote C BE0 to C BE3 RST FRAME IRDY DEVSEL TRDY STOP PAR PERR SERR REQ GNT REQ2 GNT2 Note Connect one of the AD31 to AD11 signals to the IDSEL pin of each PCI device ...

Page 65: ...3 3 V PCI GNT1 output 3 3 V PCI GNT2 output 3 3 V PCI IRDY bidir 3 3 V PCI TRDY bidir 3 3 V PCI STOP bidir 3 3 V PCI PCIRST output 3 3 V PCI AD0 to AD31 bidir 3 3 V PCI CBE0 to CBE3 bidir 3 3 V PCI PAR bidir 3 3 V PCI PERR bidir 3 3 V PCI SERR input 3 3 V PCI 2 Determine the pin assignment taking equal length wiring into consideration for the PCI bus interface pins 3 Specify the PCLK and SDCLK sig...

Page 66: ...LK TH TSU Input Inputs valid Table 4 1 33 MHz Timing Parameters Symbol Parameter MIN ns MAX ns TVAL CLK to signal valid delay bused signals 2 11 TVAL ptp CLK to signal valid delay point to point signals 2 12 TSU Input setup time to CLK bused signals 7 TSU ptp Input setup time to CLK point to point signals 10 TH Input hold time from CLK 0 4 6 3 SDRAM interface timing The timing for interfacing with...

Page 67: ...ith an IDE controller mounted on the PCI connecter 5 1 Block Diagram of Evaluation Board A block diagram of the evaluation board is shown below Figure 5 1 Block Diagram of Evaluation Board PCI host evaluation board MEMC bus MEMC bus PCI bus PCI bus PCI host bridge macro PCI connector Hard disk drive PCI IDE controller Flash memory 7 segment SW V850E ME2 176 pin LQFP SRAM 1 MB SDRAM 64 MB ROM socke...

Page 68: ...d memory Flash memory CSZ0 area 32 bit width 8 MB SRAM CSZ1 area 32 bit width 1 MB SDRAM CSZ3 area 32 bit width 64 MB Evaluation board peripheral I O PCI host bridge CSZ6 area 32 bit width PCI Rev 2 1 compliant host interface 33 MHz Other 7 segment display 7 segment display 2 can be controlled by V850E ME2 general purpose port The device numbers of the PCI bus are assigned as follows Table 5 2 IDS...

Page 69: ...to A12 BA0 BA12 D0 to D31 CLK RAS CAS WE CKE CS DQM0 DQM1 DQM2 DQM3 SDRAM SDRAM CSZ6 VBESTZ RA0 to RA25 RD0 to RD25 BENZ0 to BENZ3 WRZ0 to WRZ3 RDZ WAITZ INT0 INT1 INT2 HLDRQZ HLDAKZ DQM0 to DQM3 SDCLK SDCKE SDCS SDRASZ SDCASZ SDWEZ PCLK PCIRST IRDY DEVSEL TRDY STOP PAR PERR SERR REQ1 GNT1 INTA CBE0 to CBE3 FRAME AD0 to AD31 FPGA PCI host bridge RST AD0 to AD31 IDSEL FRAME IRDY DEVSEL TRDY STOP PA...

Page 70: ... CSZ3 External SRAM area 64 MB CSZ6 PCI host bridge area 8 MB SRAM area 56 MB Flash memory area 7 MB Access prohibited area On chip instruction RAM area 1 MB 3FF B000H 3FF EFFFH On chip peripheral I O mirror 4 KB SDRAM area area 1 64 MB Reserved area area 2 64 MB On chip data RAM mirror 16 KB 3FF F000H 3FF FFFFH FFF 8000H FFF 7FFFH FFF AFFFH Access prohibited area FFF B000H FFF EFFFH On chip perip...

Page 71: ...00H FFFF FFFFH SYSTEM_MEM_BASE SYSTEM_MEM_BASE CC0 0000H CFF FFFFH PCI_MEM_BASE 31 22 00 0000H PCI_MEM_BASE 31 22 3F FFFFH SYSTEM_MEM_BASE SYSTEM_MEM_BASE Main memory area SDRAM PCI memory area CS6 area 4 MB CPU memory space Main memory area SDRAM PCI memory area Figure 5 5 Comparison Between CPU Memory Space and PCI I O Space PCI I O space 0000 0000H FFFF FFFFH CA0 0000H C80 0000H CBF FFFFH PCI_M...

Page 72: ...I memory space and CPU memory space the interrupts from PCI and access control from the CPU to the PCI memory space are set by the PCI host bridge macro registers 2 PCI configuration space access sample program list When initialization of the PCI host bridge macro ends initialization of each PCI device connected to the PCI bus is performed Initialization is performed mainly by setting the configur...

Page 73: ...ne BASE_ADDRESS_PCI_BRIDGE_IO BASE_ADDRESS_ME2PCIIF 0x00200000 define BASE_ADDRESS_PCI_MEM BASE_ADDRESS_ME2PCIIF 0x00400000 define BASE_ADDRESS_SDRAM 0x04000000 define RANGE_SDRAM 0x03FFFFFF 64MB PCI Host Bridge Macro register address definition define PHBMR_PCI_CONFIG_DATA BASE_ADDRESS_PCI_BRIDGE_IO 0x00 define PHBMR_PCI_CONFIG_ADD BASE_ADDRESS_PCI_BRIDGE_IO 0x04 define PHBMR_PCI_CONTROL BASE_ADD...

Page 74: ...1 Set time for shifting to bus parking to 7 bit 15 08 PCI_REQ 1 Enable I_REQ_B0 bit 4 PCI_RESET bit 1 Release PCI bus reset V850EME2_REGW PHBMR_PCI_IO_BASE BASE_ADDRESS_PCI_IO PCI_IO_BASE register Set PCI I O space base address to C800000H V850EME2_REGW PHBMR_PCI_MEM_BASE BASE_ADDRESS_PCI_MEM PCI_MEM_BASE register Set PCI memory space base address to CC00000H V850EME2_REGW PHBMR_PCI_CONTROL 0x0700...

Page 75: ...Y 10B Set CAS latency to 2 bit 05 04 WAIT_STATE 01B Set wait interval of ACT CMD PRE ACT and CMD ACT to 1 clock bit 01 00 COLUMN_SIZE 01B Set bit width of column address to 9 bits V850EME2_REGW PHBMR_PCI_CONTROL 0x07000717 bit 31 24 PCI_PARKCNT 1 Set time for shifting to bus parking to 7 bit 15 08 PCI_REQ 1 Enable I_REQ_B0 bit 4 PCI_RESET bit 1 Release PCI bus reset bit 1 PCI_MEM_EN bit 1 Enable a...

Page 76: ...ridge Macro This procedure is combined in functions PCI_ConfigRead and PCI_ConfigWrite shown below Function PCI_Config_BaseAddressInit uses function PCI_ConfigWrite to set base address register in configuration space Type declaration typedef char BYTE typedef short int HWORD typedef int WORD typedef unsigned char UBYTE typedef unsigned short int UHWORD typedef unsigned int UWORD typedef volatile u...

Page 77: ...alue None Details Sets base address register of offset 10H to 24H in configuration space of PCI device connected to AD30 signal by IDSEL as follows ATA Command Register Base Address 10H 0C80_0000H ATA Control Register Base Address 14H 0C80_0008H Bus Master Control Register Base Address 18H 0C80_0010H void PCI_Config_BaseAddressInit void UWORD ConfigAddress UWORD ConfigData ATA Command Register Bas...

Page 78: ...Bus Master Control Register Base Address ConfigAddress 0x40000018 bit 31 11 IDSEL specification 010000000000000000000b Select PCI device connected to AD30 bit 10 08 Function number 00b bit 07 02 Register number 6 000110b Bus Master Control Register Base Address In the case of PCI IDE ASIC board used in this application bit 01 00 00b fixed PCI_ConfigWrite ConfigAddress 0x0C800010 return Function na...

Page 79: ...sfer and DMA transfer are available This sample program is provided with device selection protocol and four transfer protocols as functions Corresponding transfer protocol function is called from function processing each ATA command PCI IDE ASIC board register address definition IDE Command Area define IDEREG_DATA VUWORD BASE_ADDRESS_PCI_IO 0x00 define IDEREG_ERROR VUBYTE BASE_ADDRESS_PCI_IO 0x01 ...

Page 80: ...BSY0 3 define STATUS_TIMEOUT_INTRQ 4 define STATUS_TIMEOUT_BMEND 5 define STATUS_IDE_ERROR IDE_ERROR_REG 0x10000000 UWORD IDE_ERROR_REG Transfer mode timing setting value definition See IDE specifications for details of transfer mode timing setting values shown below Setting value passed to SET_FEATURES command in Set_Transfer_mode define PIO_MODE0 0x08 define UDMA_MODE0 0x40 Setting value of timi...

Page 81: ...ion Function name PCI_Config_ModeInit Function Sets initialization of PCI IDE ASIC board Argument None Return value None Details Sets handling of interrupts and errors coding and then resets IDE bus void PCI_Config_ModeInit void UWORD ConfigAddress UWORD ConfigData Setting of PCI functions ConfigAddress 0x40000004 bit 31 11 IDSEL specification 010000000000000000000b Select PCI device connected to ...

Page 82: ...00b fixed IDE Bus Master Control Disable DES Set bit16 des_on to 0 ConfigData PCI_ConfigRead ConfigAddress PCI_ConfigWrite ConfigAddress ConfigData 0xFFFEFFFF Setting of Interrupt Control register IDEREG_INTERRUPT_CONTROL 0xFFFCFFFF bit 17 PCI Bus Master End Interrupt Mask 0b Interrupt enabled bit 16 PCI I F Interrupt Mask 0b Interrupt enabled Setting of Device Command register IDEREG_DEVICE_CONTR...

Page 83: ...ELECTION DEVICE SELECTION error end STATUS_TIMEOUT_DRDY1 DRDY 1 timeout error end STATUS_TIMEOUT_INTRQ INTRQ timeout error end STATUS_IDE_ERROR Error end after command execution int Set_Transfer_Mode int dev_num UBYTE mode status ATA_Set_Features dev_num 0x03 mode return status Function name Set_PIO_Timing Function Setting of PIO Timing register Argument pio_timing Value set to PIO Timing register...

Page 84: ...udma_timing2 UWORD ConfigAddress UWORD ConfigData ConfigAddress 0x4000004C bit 31 11 IDSEL specification 010000000000000000000b Select PCI device connected to AD30 bit 10 08 Function number 00b bit 07 02 Register number 19 010011b UltraDMA Timing1 In the case of PCI IDE ASIC board used in this application bit 01 00 00b fixed PCI_ConfigWrite ConfigAddress udma_timing11 ConfigAddress 0x40000050 bit ...

Page 85: ... features sub_cmd Features register ac sector_count mode SectorCount register ac sector_number 0x00 SectorNumber register ac cylinder_low 0x00 CylinderLow register ac cylinder_high 0x00 CylinderHigh register ac device_head dev_num 4 Device Head register ac command 0xEF Command register status ATA_PIO_nondata ac return status Function name ATA_Idle_Immediate Function Executes IDLE IMMEDIATE command...

Page 86: ...selection 0 Master 1 Slave buff Buffer pointer Return value STATUS_SUCCESS Normal end STATUS_TIMEOUT_DEVICE_SELECTION DEVICE SELECTION error end STATUS_TIMEOUT_DRDY1 DRDY 1 timeout error end STATUS_TIMEOUT_INTRQ INTRQ timeout error end STATUS_IDE_ERROR Error end after command execution int ATA_Identify_Device int dev_num void buff ATA_COMMAND ac int status ac features 0x00 Features register ac sec...

Page 87: ... sector_number lba 0xFF SectorNumber register ac cylinder_low lba 8 0xFF CylinderLow register ac cylinder_high lba 16 0xFF CylinderHigh register ac device_head 0x40 dev_num 4 lba 24 0x0F Device Head register ac command 0x20 Command register status ATA_PIO_datain ac sec_cnt buff return status Function name ATA_Write_Sector Function Executes WRITE SECTOR S command Protocol PO Command 30h Argument de...

Page 88: ...lba LBA sec_cnt Number of sectors Return value STATUS_SUCCESS Normal end STATUS_TIMEOUT_DEVICE_SELECTION DEVICE SELECTION error end STATUS_TIMEOUT_BSY0_DRQ0 BSY 0 DRQ 0 timeout error end STATUS_TIMEOUT_DRDY1 DRDY 1 timeout error end STATUS_TIMEOUT_INTRQ INTRQ timeout error end STATUS_TIMEOUT_BMEND BM timeout error end STATUS_IDE_ERROR Error end after command execution int ATA_Read_DMA int dev_num ...

Page 89: ...ror end after command execution int ATA_Write_DMA int dev_num UWORD lba UHWORD sec_cnt int status ATA_COMMAND ac ac features 0x00 Features register ac sector_count sector_count SectorCount register ac sector_number lba 0xFF SectorNumber register ac cylinder_low lba 8 0xFF CylinderLow register ac cylinder_high lba 16 0xFF CylinderHigh register ac device_head 0x40 dev_num 4 lba 24 0x0F Device Head r...

Page 90: ...MAND structure pointer sector_count Number of sectors buff Buffer pointer Return value STATUS_SUCCESS Normal end STATUS_TIMEOUT_DEVICE_SELECTION DEVICE SELECTION error end STATUS_TIMEOUT_DRDY1 DRDY 1 timeout error end STATUS_TIMEOUT_INTRQ INTRQ timeout error end STATUS_IDE_ERROR Error end after command execution int ATA_PIO_datain ATA_COMMAND atacom UHWORD sector_count void buff UBYTE dev idestat ...

Page 91: ...gister read INTRQ clear for j 0 j 128 j Data read buffp IDEREG_DATA buffp idestat IDEREG_ALTERNATE_STATUS Alt Status register empty read idestat IDEREG_STATUS Status register read if idestat IDEREG_ERROR_ERR_BIT return STATUS_IDE_ERROR IDEREG_ERROR Error end after command execution return STATUS_SUCCESS Normal end Function name ATA_PIO_dataout Function Executes PIO data out command protocol Argume...

Page 92: ...er SectorNumber register IDEREG_CYLINDER_LOW atacom cylinder_low CylinderLow register IDEREG_CYLINDER_HIGH atacom cylinder_high CylinderHigh register status Wait_IDE_DRDY1 Loop until DRDY 1 if status 0 return STATUS_TIMEOUT_DRDY1 DRDY timeout IDEREG_COMMAND atacom command Command register wait TIMER400ns Wait 400 ns status Wait_IDE_BSY0_DRQ0 Wait until BSY 0 DRQ 0 if status 0 return STATUS_TIMEOUT...

Page 93: ...AND atacom int status UBYTE dev idestat dev atacom device_head 4 1 status ATA_Device_Selection dev DEVICE SELECTION if status 0 return STATUS_TIMEOUT_DEVICE_SELECTION DEVICE SELECTION timeout IDEREG_FEATURES atacom features Features register IDEREG_SECTOR_COUNT atacom sector_count SectorCount register IDEREG_SECTOR_NUMBER atacom sector_number SectorNumber register IDEREG_CYLINDER_LOW atacom cylind...

Page 94: ...eout error end STATUS_TIMEOUT_INTRQ INTRQ timeout error end STATUS_TIMEOUT_BMEND BM timeout error end STATUS_IDE_ERROR Error end after command execution int ATA_DMA ATA_COMMAND atacom int status UBYTE dev idestat dev atacom device_head 4 1 status ATA_Device_Selection dev DEVICE SELECTION if status 0 return STATUS_TIMEOUT_DEVICE_SELECTION DEVICE SELECTION timeout IDEREG_FEATURES atacom features Fea...

Page 95: ...ster empty read idestat IDEREG_STATUS Status register read if idestat IDEREG_ERROR_ERR_BIT return STATUS_IDE_ERROR IDEREG_ERROR Error end after command execution return STATUS_SUCCESS Normal end Function name ATA_Soft_Reset Function Performs software reset Argument None Return value STATUS_SUCCESS Normal end STATUS_TIMEOUT_BSY0 BSY 0 timeout error end int ATA_soft_reset void int status IDEREG_DEVI...

Page 96: ...ands int main void int status UBYTE wbuff 4096 rbuff 4096 DISCRIPTOR_TABLE dsc_tbl System initialization Initializes PCI Host Bridge Macro PCI_HBM_Init Sets initialization of PCI IDE ASIC board PCI_Config_BaseAddressInit PCI_Config_ModeInit ATA_soft_reset void Soft reset Issue ATA command to IDE HDD IDLE IMMEDIATE ATA_Idle_Immediate 0 Issues IDLE IMMEDIATE command IDENTIFY DEVICE ATA_Identify_Devi...

Page 97: ...ctor Issues READ SECTOR command 0 Master Device 0 LBA 0 1 1 Sector rbuff Buffer storing read results status memcmp wbuff rbuff 512 if status 0 printf Verify Error WRITE SECTOR S READ SECTOR S n UltraDMA transfer preparation Sets transfer mode to UltraDMA transfer Mode0 using SET_FEATURE command Set_Transfer_Mode 0 UDMA_MODE0 Sets UltraDMA Timing1 and UltraDMA Timing2 registers of configuration reg...

Page 98: ...Write_DMA 0 Master Device 0 LBA 0 8 8 Sector PCI IDE UltraDMA transfer Sets descriptor table referenced by device during UltraDMA transfer dsc_tbl transfer_address BASE_ADDRESS_SDRAM 0x01000000 dsc_tbl transfer_byte 0x1000 4096byte 8Sector dsc_tbl next_table_address 0x00000001 Last table IDEREG_DSCTBL_START_ADDRESS dsc_tbl Sets transfer direction of UltraDMA transfer IDEREG_BUSMASTER_START_STOP 0x...

Page 99: ... HDD Transfer address 0400 0000H Bus master transfer of 8 sectors 4096 bytes is performed from 400 0000H SDRAM area to LBA0 of IDE HDD Figure 5 7 IDE_Read_DMA Function 400 0000H 4096 bytes Descriptor table 500 0000H 600 0000H 3FF FFFFH 4FF FFFFH 5FF FFFFH 700 0000H 6FF FFFFH 000 0000H IDE HDD READ DMA Data transfer from IDE HDD to SDRAM Bus master transfer of 8 sectors 4096 bytes is performed from...

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