CHAPTER 3 SPECIFICATIONS OF PCI HOST BRIDGE MACRO
Application Note U17121EJ1V1AN
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3.4.4 PCI_IO_BASE register
When I/O accessing the PCI bus I/O space via the PCI I/O area (area in which the I_CPU_CS1_B pin becomes
active: 64 KB), any area of the 4 GB PCI bus I/O space can be accessed by setting this register.
After reset: 00000000H R/W Offset address: 10H
31
16 15
0
IO_BASE
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit Name
R/W
Function
IO_BASE R/W
Sets the higher 16 bits (bits 16 to 31) of the PCI bus I/O space base address when accessing the
PCI I/O area (area in which the I_CPU_CS1_B pin becomes active) from the CPU.
3.4.5 PCI_MEM_BASE register
When memory accessing the PCI bus memory space via the PCI memory area (area in which the I_CPU_CS2_B
pin becomes active: 1 MB), any area of the 4 GB PCI bus memory space can be accessed by setting this register.
However, because the main memory (SDRAM) is mapped on the PCI bus memory space, do not overlap the area
set by the SYSTEM_MEM_BASE register and SYSTEM_MEM_RANGE register described later.
After reset: 80000000H R/W Offset address: 14H
31
20 19
0
M_BASE
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit Name
R/W
Function
M_BASE R/W
Sets the higher 12 bits (bits 20 to 31) of the PCI bus memory space base address when accessing
the PCI memory area (area in which the I_CPU_CS2_B pin becomes active) from the CPU.
