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CHAPTER 16 INTERRUPT FUNCTIONS

292

User’s Manual U15331EJ4V1UD

Table 16-2. Interrupt Sources (

PD789489, 78F9489)

Interrupt Source

Interrupt Type

Priority

Note 1

Name Trigger

Internal/
External

Vector Table

Address

Basic

Configuration

Type

Note 2

Non-maskable

−

INTWDT

Watchdog timer overflow (with
watchdog timer mode 1 selected)

(A)

INTWDT

Watchdog timer overflow (with
interval timer mode selected)

Internal 0004H

(B)

INTP0

Pin (INTP0) input edge detection

0006H

INTP1

Pin (INTP1) input edge detection

0008H

INTP2

Pin (INTP2) input edge detection

000AH

INTP3

Pin (INTP3) input edge detection

External

000CH

(C)

INTRIN

Remote controller edge detection

000EH

INTSR20

UART reception completion

INTCSI20

End of 3-wire SIO transfer for serial
interface 20

0010H

INTCSI10

End of 3-wire SIO transfer for serial
interface 1A0

0012H

INTST20

End of UART transmission for serial
interface 20

0014H

INTWTI

Reference time interval signal of
watch timer (WT)

0016H

INTTM20

Match between TM20 and CR20

0018H

INTTM50

Match between TM50 and CR50

001AH

INTTM60

Match between TM60 and CR60
(in 8-bit counter mode), and
between TM50, TM60 and CR50,
CR60 (in 16-bit timer mode)

001CH

INTTM61

Match between TM61 and CR61

001EH

INTAD0

End of A/D conversion

0020H

INTWT

Watch timer (WT) overflow

Internal

0022H

(B)

INTKR00

Key return signal detection

External

0024H

(C)

INTRERR

Remote controller reception error
occurrence

0026H

INTGP

Remote controller guide pulse
detection

0028H

INTREND

Remote controller data reception
completion

002AH

INTDFULL

Read request for remote controller
8-bit shift data

Internal

002CH

(B)

Maskable

INTKR01

Key return signal detection

External

002EH

(C)

Notes 1.

Priority is the priority order when more than one maskable interrupt request is generated at the same

time. 0 is the highest priority and 21 is the lowest.

Basic configuration types (A), (B), and (C) correspond to (A), (B), and (C) in Figure 16-1.

Remark

Only one of the two watchdog timer interrupt (INTWDT) sources, non-maskable or maskable (internal),

can be selected.

Summary of Contents for PD789488

Page 1: ...User s Manual µPD789488 µPD789489 µPD78F9488 µPD78F9489 µPD789489 Subseries 8 Bit Single Chip Microcontrollers Printed in Japan Document No U15331EJ4V1UD00 4th edition Date Published July 2005 NS CP K ...

Page 2: ...2 User s Manual U15331EJ4V1UD MEMO ...

Page 3: ... including work benches and floors should be grounded The operator should be grounded using a wrist strap Semiconductor devices must not be touched with bare hands Similar precautions need to be taken for PW boards with mounted semiconductor devices STATUS BEFORE INITIALIZATION Power on does not necessarily define the initial status of a MOS device Immediately after the power source is turned ON d...

Page 4: ...a trademark of International Business Machines Corporation HP9000 series 700 and HP UX are trademarks of Hewlett Packard Company SPARCstation is a trademark of SPARC International Inc Solaris and SunOS are trademarks of Sun Microsystems Inc These commodities technology or software must be exported in accordance with the export administration regulations of the exporting country Diversion contrary ...

Page 5: ...eof cannot be eliminated entirely To minimize risks of damage to property or injury including death to persons arising from defects in NEC Electronics products customers must incorporate sufficient safety measures in their design such as redundancy fire containment and anti failure features NEC Electronics products are classified into the following three quality grades Standard Special and Specifi...

Page 6: ...anch Seoul Korea Tel 02 558 3737 NEC Electronics Shanghai Ltd Shanghai P R China Tel 021 5888 5400 NEC Electronics Taiwan Ltd Taipei Taiwan Tel 02 2719 2377 NEC Electronics Singapore Pte Ltd Novena Square Singapore Tel 6253 8311 J05 6 NEC Electronics Europe GmbH Duesseldorf Germany Tel 0211 65030 Sucursal en España Madrid Spain Tel 091 504 27 87 Vélizy Villacoublay France Tel 01 30 67 58 00 Succur...

Page 7: ... to 157 Modification of the mode name in 7 4 4 PWM output mode operation timer 50 pp 158 159 Modification of the mode name in 7 4 5 PPG output mode operation timer 60 and 61 p 160 Modification of 1 Error on starting timer in 7 5 Cautions on Using 8 Bit Timers 50 60 and 61 p 174 Modification of Figure 10 1 Block Diagram of 10 bit A D converter p 182 Modification of 1 Current consumption in standby ...

Page 8: ...cal specifications CPU function Instruction set Instruction description How to Use This Manual It is assumed that the readers of this manual have general knowledge of electrical engineering logic circuits and microcontrollers To understand the overall functions of the µPD789489 Subseries Read this manual in the order of the CONTENTS How to read register formats The name of a bit whose number is en...

Page 9: ...er s Manual U11047E Documents Related to Development Software Tools User s Manuals Document Name Document No Operation U17391E Language U17390E RA78K0S Assembler Package Structured Assembly Language U17389E Operation U16654E CC78K0S C Compiler Language U16655E Operation U17246E SM System Simulator User Open Interface U17247E Operation U16768E SM78K Series Ver 2 52 System Simulator External Part Us...

Page 10: ...ages X13769X Semiconductor Device Mount Manual Note Quality Grades on NEC Semiconductor Devices C11531E NEC Semiconductor Device Reliability Quality Control System C10983E Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge ESD C11892E Note See the Semiconductor Device Mount Manual website http www necel com pkg en mount index html Caution The related documents listed abov...

Page 11: ...4 Port 3 41 2 2 5 P50 to P53 Port 5 41 2 2 6 P60 to P67 Port 6 42 2 2 7 P70 to P73 Port 7 42 2 2 8 P80 to P87 Port 8 42 2 2 9 S0 to S27 42 2 2 10 COM0 to COM3 42 2 2 11 VLC0 to VLC2 42 2 2 12 CAPH CAPL 42 2 2 13 RESET 43 2 2 14 X1 X2 43 2 2 15 XT1 XT2 43 2 2 16 AVDD 43 2 2 17 AVSS 43 2 2 18 VDD 43 2 2 19 VSS 43 2 2 20 VPP flash memory version only 43 2 2 21 IC0 mask ROM version only 44 2 3 Pin I O...

Page 12: ...3 3 4 6 Based addressing 74 3 4 7 Stack addressing 74 CHAPTER 4 PORT FUNCTIONS 75 4 1 Port Functions 75 4 2 Port Configuration 76 4 2 1 Port 0 77 4 2 2 Port 1 78 4 2 3 Port 2 79 4 2 4 Port 3 84 4 2 5 Port 5 86 4 2 6 Port 6 87 4 2 7 Port 7 89 4 2 8 Port 8 90 4 3 Registers Controlling Port Function 91 4 4 Port Function Operation 94 4 4 1 Writing to I O port 94 4 4 2 Reading from I O port 94 4 4 3 Ar...

Page 13: ...mpare register 20 118 CHAPTER 7 8 BIT TIMERS 50 60 AND 61 120 7 1 Functions of 8 Bit Timers 50 60 and 61 120 7 2 Configuration of 8 Bit Timers 50 60 and 61 122 7 3 Control Registers for 8 Bit Timers 50 60 and 61 128 7 4 Operation of 8 Bit Timers 50 60 and 61 134 7 4 1 Operation as 8 bit timer counter 134 7 4 2 Operation as 16 bit timer counter 143 7 4 3 Operation as carrier generator 150 7 4 4 PWM...

Page 14: ... stop mode 197 11 4 2 Asynchronous serial interface UART mode 199 11 4 3 3 wire serial I O mode 211 CHAPTER 12 SERIAL INTERFACE 1A0 216 12 1 Function of Serial Interface 1A0 216 12 2 Configuration of Serial Interface 1A0 217 12 3 Control Registers for Serial Interface 1A0 219 12 4 Serial Interface 1A0 Operation 224 12 4 1 Operation stop mode 224 12 4 2 3 wire serial I O mode 225 12 4 3 3 wire seri...

Page 15: ...t Function Types 290 16 2 Interrupt Sources and Configuration 290 16 3 Registers Controlling Interrupt Function 294 16 4 Interrupt Servicing Operation 301 16 4 1 Non maskable interrupt request acknowledgment operation 301 16 4 2 Maskable interrupt request acknowledgment operation 303 16 4 3 Multiple interrupt servicing 304 16 4 4 Putting interrupt requests on hold 306 CHAPTER 17 STANDBY FUNCTION 3...

Page 16: ...342 CHAPTER 23 CHARACTERISTICS CURVES OF LCD CONTROLLER DRIVER 362 CHAPTER 24 PACKAGE DRAWINGS 364 CHAPTER 25 RECOMMENDED SOLDERING CONDITIONS 366 APPENDIX A DEVELOPMENT TOOLS 369 A 1 Software Package 371 A 2 Language Processing Software 371 A 3 Control Software 372 A 4 Flash Memory Writing Tools 372 A 5 Debugging Tools Hardware 373 A 6 Debugging Tools Software 374 APPENDIX B NOTES ON TARGET SYSTE...

Page 17: ...ster Configuration 61 4 1 Port Types 75 4 2 Block Diagram of P00 to P07 77 4 3 Block Diagram of P10 and P11 78 4 4 Block Diagram of P20 79 4 5 Block Diagram of P21 80 4 6 Block Diagram of P22 and P25 81 4 7 Block Diagram of P23 82 4 8 Block Diagram of P24 83 4 9 Block Diagram of P30 to P33 84 4 10 Block Diagram of P34 85 4 11 Block Diagram of P50 to P53 86 4 12 Block Diagram of P60 to P67 87 4 13 ...

Page 18: ...Diagram of Timer 60 124 7 4 Block Diagram of Timer 61 125 7 5 Block Diagram of Output Controller Timer 60 126 7 6 Format of 8 Bit Timer Mode Control Register 50 128 7 7 Format of 8 Bit Timer Mode Control Register 60 130 7 8 Format of Carrier Generator Output Control Register 60 131 7 9 Format of 8 Bit Timer Mode Control Register 61 132 7 10 Format of Port Mode Register 3 133 7 11 Timing of Interva...

Page 19: ...ch Timer 161 8 2 Format of Watch Timer Mode Control Register 163 8 3 Format of Watch Timer Interrupt Time Selection Register 164 8 4 Watch Timer Interval Timer Operation Timing 166 9 1 Block Diagram of Watchdog Timer 168 9 2 Format of Watchdog Timer Clock Selection Register 169 9 3 Format of Watchdog Timer Mode Register 170 10 1 Block Diagram of 10 Bit A D Converter 174 10 2 Format of A D Converte...

Page 20: ...art 237 12 9 Buffer RAM Operation in 6 Byte Transmission Reception in Basic Transmit Receive Mode 238 12 10 Basic Transmit Mode Operation Timing 240 12 11 Basic Transmit Mode Flowchart 241 12 12 Buffer RAM Operation in 6 Byte Transmission in Basic Transmit Mode 242 12 13 Repeat Transmit Mode Operation Timing 244 12 14 Repeat Transmit Mode Flowchart 245 12 15 Buffer RAM Operation in 6 Byte Transmis...

Page 21: ...ion Operation Example 288 16 1 Basic Configuration of Interrupt Function 293 16 2 Format of Interrupt Request Flag Registers 295 16 3 Format of Interrupt Mask Flag Registers 296 16 4 Format of External Interrupt Mode Registers 297 16 5 Program Status Word Configuration 298 16 6 Format of Key Return Mode Register 00 299 16 7 Block Diagram of Falling Edge Detector 299 16 8 Format of Key Return Mode ...

Page 22: ...Conflict Input Pin of Serial Interface 325 19 6 Abnormal Operation of Other Device 325 19 7 Signal Conflict RESET Pin 326 19 8 Wiring Example for Flash Writing Adapter with 3 Wire Serial I O 327 19 9 Wiring Example for Flash Writing Adapter with 3 Wire Serial I O with Handshake 328 19 10 Wiring Example for Flash Writing Adapter with UART 329 A 1 Development Tools 370 B 1 Distance Between In Circui...

Page 23: ...Settings of Capture Edge 116 7 1 Operation Modes 120 7 2 Configuration of 8 Bit Timers 50 60 and 61 122 7 3 Interval Time of Timer 50 135 7 4 Interval Time of Timer 60 135 7 5 Interval Time of Timer 61 135 7 6 Square Wave Output Range of Timer 50 141 7 7 Square Wave Output Range of Timer 60 142 7 8 Square Wave Output Range of Timer 61 142 7 9 Interval Time with 16 Bit Resolution 144 7 10 Square Wa...

Page 24: ... Pixels 250 13 2 Configuration of LCD Controller Driver 250 13 3 Frame Frequencies Hz 255 13 4 COM Signals 258 13 5 Select and Deselect Voltages COM0 to COM2 260 13 6 Select and Deselect Voltages COM0 to COM3 263 13 7 Output Voltages of VLC0 to VLC2 Pins 265 15 1 Remote Controller Receiver Configuration 271 15 2 Noise Elimination Width 287 16 1 Interrupt Sources µPD789488 78F9488 291 16 2 Interrup...

Page 25: ...15331EJ4V1UD 25 LIST OF TABLES 3 3 Table No Title Page 21 1 Operand Identifiers and Description Methods 332 25 1 Surface Mounting Type Soldering Conditions 366 B 1 Distance Between IE System and Conversion Adapter 375 ...

Page 26: ...ck and ultra low speed 122 µs 32 768 kHz operation with subsystem clock A circuit to multiply the subsystem clock by 4 is selectable 15 26 µs 131 kHz operation 32 768 kHz subsystem clock 4 I O ports 45 N ch open drain 4 Timer 6 channels Serial interface 2 channels 10 bit resolution A D converter 8 channels LCD controller driver on chip voltage booster Segment signals 28 common signals 4 On chip mu...

Page 27: ... QFP 14 14 Flash memory µPD78F9489GK 9EU 80 pin plastic TQFP fine pitch 12 12 Flash memory µPD789488GC 8BT A 80 pin plastic QFP 14 14 Mask ROM µPD789488GK 9EU A 80 pin plastic TQFP fine pitch 12 12 Mask ROM µPD78F9488GC 8BT A 80 pin plastic QFP 14 14 Flash memory µPD78F9488GK 9EU A 80 pin plastic TQFP fine pitch 12 12 Flash memory µPD789489GC 8BT A 80 pin plastic QFP 14 14 Mask ROM µPD789489GK 9EU...

Page 28: ...S12 S13 S14 S15 P70 S16 Note 1 P71 S17 Note 1 P72 S18 Note 1 P73 S19 Note 1 P80 S20 Note 2 P81 S21 Note 2 P82 S22 Note 2 P83 S23 Note 2 P84 S24 Note 2 P85 S25 Note 2 P86 S26 Note 2 P87 S27 Note 2 AV DD P67 ANI7 KR17 P66 ANI6 KR16 P50 P51 P52 P53 RESET X2 X1 V SS V DD XT2 XT1 IC0 V PP P00 KR00 P01 KR01 P02 KR02 P03 KR03 P04 KR04 P05 KR05 P06 KR06 P07 KR07 21 22 23 24 25 26 27 28 29 30 31 32 33 34 3...

Page 29: ...COM0 COM1 COM2 COM3 S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 P10 P11 P20 SCK20 ASCK20 P21 SO20 TxD20 P22 SI20 RxD20 P23 SCK10 P24 SO10 P25 SI10 P30 INTP0 TO50 TMI60 P31 INTP1 TO60 P32 INTP2 TMI61 TO61 P33 INTP3 CPT20 TO20 P34 RIN AVSS P60 ANI0 KR10 P61 ANI1 KR11 P62 ANI2 KR12 P63 ANI3 KR13 P64 ANI4 KR14 P65 ANI5 KR15 S11 S12 S13 S14 S15 P70 S16 Note 1 P71 S17 Note 1 P72 S18 Note 1 P73 S19 Note 1 P80 S20 ...

Page 30: ...ANI0 to ANI7 Analog input ASCK20 Asynchronous serial input AVDD Analog power supply AVSS Analog ground CAPH CAPL LCD power supply capacitance control COM0 to COM3 Common output CPT20 Capture trigger input IC0 Internally connected INTP0 to INTP3 External interrupt input KR0 to KR7 Key return KR00 to KR07 Key return KR10 to KR17 Key return P00 to P07 Port 0 P10 P11 Port 1 P20 to P25 Port 2 P30 to P3...

Page 31: ...167 with enhanced A D converter 10 bits PD789104A with enhanced timer PD789124A with enhanced A D converter 10 bits RC oscillation version of the PD789104A PD789104A with enhanced A D converter 10 bits PD789026 with added 8 bit A D converter and multiplier PD789177Y PD789167Y Y Subseries products support SMB 88 pin PD789830 PD789835B 144 pin UART and dot LCD 40 16 UART 8 bit A D and dot LCD Total ...

Page 32: ...9167 16 KB to 24 KB 3 ch 1 ch 8 ch 31 µPD789134A 4 ch µPD789124A 4 ch RC oscillation version µPD789114A 4 ch Small scale package general purpose applications and A D converter µPD789104A 2 KB to 8 KB 1 ch 1 ch 1 ch 4 ch 1 ch UART 1 ch 20 1 8 V µPD789835B 24 KB to 60 KB 6 ch 3 ch 37 1 8 V Note µPD789830 24 KB 1 ch 1 ch UART 1 ch 30 2 7 V Dot LCD supported µPD789489 32 KB to 48 KB 8 ch µPD789479 24 ...

Page 33: ... 2 ch 31 On chip bus controller µPD789850A 16 KB 1 ch 1 ch 1 ch 4 ch 2 ch UART 1 ch 18 4 0 V µPD789861 RC oscillation version on chip EEPROM µPD789860 4 KB 2 ch 14 Keyless entry µPD789862 16 KB 1 ch 2 ch 1 ch 1 ch UART 1 ch 22 1 8 V On chip EEPROM µPD789864 On chip EEPROM Sensor µPD789863 4 KB 1 ch Note 2 1 ch 4 ch 5 1 9 V RC oscillation version on chip EEPROM VFD drive µPD789871 4 KB to 8 KB 3 ch...

Page 34: ...ontrol INTP0 P30 to INTP3 P33 RAM space for LCD data 8 bit timer 50 TMI60 P30 TMI61 TO61 P32 Remote control signal receiverNote 4 Note 4 RIN P34 Serial interface 1A0 SCK10 P23 SI10 P25 SO10 P24 Note 1 S16 to S19 Note 2 S20 to S27 Multiplier CAPH CAPL Notes 1 Whether to use these pin as input ports P70 to P73 or segment outputs S16 to S19 can be selected in 1 bit units by means of a mask option in ...

Page 35: ...its 8 bits 16 bits I O ports Total 45 Note 2 CMOS I O 29 CMOS input 12 N ch open drain I O 4 Timers 16 bit timer 1 channel 8 bit timer 3 channels Watch timer 1 channel Watchdog timer 1 channel Timer outputs 4 Serial interface UART 3 wire serial I O mode 1 channel 3 wire serial I O mode with automatic transfer function 1 channel A D converter 10 bit resolution 8 channels LCD controller driver Segme...

Page 36: ...Timer Interval timer 1 channel 1 channel 1 channel 1 channel Note 1 1 channel Note 2 Operation mode External event counter 1 channel 1 channel Timer outputs 1 output 1 output 1 output 1 output Square wave outputs 1 output 1 output 1 output Capture 1 input Function Interrupt sources 1 1 1 1 2 2 Notes 1 The watch timer can perform both watch timer and interval timer functions at the same time 2 The ...

Page 37: ...P22 SI20 RxD20 P23 SCK10 P24 SO10 P25 I O Port 2 6 bit I O port Input output can be specified in 1 bit units When used as an input port an on chip pull up resistor can be specified in 1 bit units by pull up resistor option register B2 PUB2 Input SI10 P30 INTP0 TO50 TMI60 P31 INTP1 TO60 P32 INTP2 TMI61 TO61 P33 INTP3 CPT20 TO20 P34 I O Port 3 5 bit I O port Input output can be specified in 1 bit un...

Page 38: ...valid edge rising edge falling edge or both rising and falling edges can be specified Input P33 CPT20 TO20 KR0 to KR7 Note 1 Input Key return signal detection Input P00 to P07 KR00 to KR07 Note 2 P00 to P07 KR10 to KR17 Note 2 Input Key return signal detection Input P60 ANI0 to P67 ANI7 TO20 Output 16 bit timer 20 output Input P33 INTP3 CPT20 CPT20 Output Capture edge input of 16 bit timer 20 Inpu...

Page 39: ...ation XT1 Input XT2 Connecting crystal resonator for subsystem clock oscillation RESET Input System reset input Input VDD Positive power supply VSS Ground potential IC0 Internally connected Connect directly to VSS VPP Sets flash memory programming mode Used to apply high voltage when a program is written or verified Notes 1 Whether to use these pins as input ports pins P70 to P73 or segment output...

Page 40: ... to P25 Port 2 These pins constitute a 6 bit I O port In addition these pins enable serial interface data I O and serial clock I O Port 2 can be specified in the following operation modes in 1 bit units 1 Port mode In this mode P20 to P25 function as a 6 bit I O port Port 2 can be set in the input or output port mode in 1 bit units by port mode register 2 PM2 When used as an input port use of an o...

Page 41: ...ction as timer I O external interrupt input and remote control receive data inputNote a TMI60 TMI61 These are the external clock input pins of timers 60 and 61 b TO20 TO50 TO60 TO61 These are the timer output pins of timers 20 50 60 and 61 c CPT20 This is the capture edge input pin of 16 bit timer 20 d INTP0 to INTP3 These are external interrupt input pins for which valid edges rising edge falling...

Page 42: ... by a mask option in the µPD789488 789489 or by a port function register in the µPD78F9488 78F9489 2 2 8 P80 to P87 Port 8 These pins constitute an 8 bit I O port Port 8 can be set in the input or output mode in 1 bit units by port mode register 8 PM8 This port can be used only when the port function is selected by a mask option in the µPD789488 789489 or by a port function register in the µPD78F9...

Page 43: ...erter is not used 2 2 17 AVSS This is the ground potential pin of the A D converter Always use the same potential as that of the VSS pin even when the A D converter is not used 2 2 18 VDD This is the positive power supply pin 2 2 19 VSS This is the ground pin 2 2 20 VPP flash memory version only A high voltage should be applied to this pin when the flash memory programming mode is set and when the...

Page 44: ...ode before shipment In the normal operation mode directly connect this pin to the VSS pin with as short a wiring length as possible If there is a potential difference between the IC0 pin and VSS pin due to a long wiring length or external noise superimposed on the IC0 pin the user program may not run correctly Directly connect the IC0 pin to the VSS pin VSS IC0 Keep short ...

Page 45: ...61 P33 INTP3 CPT20 TO20 P34 Note 1 P34 RIN Note 2 8 A Input Independently connect to VSS via a resistor Output Leave open P50 to P53 mask ROM version 13 W P50 to P53 flash memory version 13 V I O Input Independently connect to VDD via a resistor Output Leave open P60 ANI0 to P67 ANI7 Note 1 P60 ANI0 KR10 to P67 ANI7 KR17 Note 2 9 C P70 to P73 Note 3 2 H Input Connect to VDD or VSS P80 to P87 Note ...

Page 46: ...kΩ pull down resistor or connect directly to VSS Figure 2 1 I O Circuit Types 1 2 Type 2 Type 2 H Schmitt triggered input with hysteresis characteristics IN Input enable IN Type 5 A Type 5 K Pull up enable VDD P ch P ch IN OUT Data Output disable Input enable VDD N ch VSS Data Output disable Input enable VDD P ch IN OUT N ch Type 8 A Type 9 C Pull up enable VDD P ch Data VDD P ch Output disable IN...

Page 47: ... disable Input enable IN OUT N ch VSS Mask option VDD Middle voltage input buffer Data Output disable Input enable IN OUT N ch VSS Middle voltage input buffer Type 17 Type 18 P ch N ch P ch N ch N ch N ch data OUT VLC0 VLC1 SEG VLC2 P ch P ch P ch N ch P ch N ch P ch N ch P ch N ch data P ch N ch VLC1 VLC0 VLC2 OUT COM ...

Page 48: ... Special function registers 256 8 bits Internal high speed RAM 1024 8 bits LCD display RAM 28 4 bits F F F F H F F 0 0 H F E F F H F B 0 0 H F A F F H 0 0 0 0 H Program memory space Data memory space 7 F F F H 0 0 0 0 H Program area 0 0 8 0 H 0 0 7 F H Program area 0 0 4 0 H 0 0 3 F H CALLT table area Reserved 0 0 2 E H 0 0 2 D H Vector table area Internal ROM 32768 8 bits F A 1 C H F A 1 B H F A ...

Page 49: ...ed RAM 1024 8 bits LCD display RAM 28 4 bits F F F F H F F 0 0 H F E F F H F B 0 0 H F A F F H 0 0 0 0 H Program memory space Data memory space 7 F F F H 0 0 0 0 H Program area 0 0 8 0 H 0 0 7 F H Program area 0 0 4 0 H 0 0 3 F H CALLT table area Reserved 0 0 2 E H 0 0 2 D H Vector table area Flash memory 32768 8 bits F A 1 C H F A 1 B H F A 0 0 H F 9 F F H Reserved ...

Page 50: ...le area Vector table area Special function registers 256 8 bits Internal high speed RAM 1024 8 bits Internal low speed 512 8 bits LCD display RAM 28 4 bits Internal ROM 49152 8 bits Reserved Reserved Reserved Program memory space Data memory space F 7 0 0 H F 6 F F H F 5 0 0 H F 4 F F H C 0 0 0 H B F F F H F F F F H F F 0 0 H F E F F H F B 0 0 H F A F F H 0 0 0 0 H F A 1 C H F A 1 B H F A 0 0 H F ...

Page 51: ... H F A F F H 0 0 0 0 H F A 1 C H F A 1 B H F A 0 0 H F 9 F F H F 7 0 0 H F 6 F F H C 0 0 0 H B F F F H F 5 0 0 H F 4 F F H Program area Program area CALLT table area Vector table area Special function registers 256 8 bits Internal high speed RAM 1024 8 bits LCD display RAM 28 4 bits Reserved Reserved Internal low speed RAM 512 8 bits Reserved Flash memory 49152 8 bits Program memory space Data mem...

Page 52: ... area stores program start addresses to be used when branching by RESET input or interrupt request generation Of a 16 bit program address the lower 8 bits are stored in an even address and the higher 8 bits are stored in an odd address Table 3 2 Vector Table Vector Table Address Interrupt Request Vector Table Address Interrupt Request 0000H RESET input 0018H INTTM20 0004H INTWDT 001AH INTTM50 0006...

Page 53: ...e internal low speed RAM cannot be used as a stack Table 3 3 Internal High Speed RAM Internal Low Speed RAM Capacity Part Number Internal High Speed RAM Internal Low Speed RAM µPD789488 µPD78F9488 µPD789489 1024 8 bits µPD78F9489 512 8 bits 2 LCD display RAM LCD display RAM is incorporated in the area between FA00H and FA1BH The LCD display RAM can also be used as ordinary RAM 3 1 3 Special functi...

Page 54: ...area such as the special function registers are available Figures 3 5 to 3 8 show the data memory addressing modes Figure 3 5 Data Memory Addressing µPD789488 Special function registers 256 8 bits Internal high speed RAM 1024 8 bits LCD display RAM 28 4 bits F F F F H 8 0 0 0 H 7 F F F H 0 0 0 0 H Direct addressing Register indirect addressing Based addressing F F 0 0 H F E F F H F F 2 0 H F F 1 F...

Page 55: ... speed RAM 1024 8 bits LCD display RAM 28 4 bits F F F F H 8 0 0 0 H 7 F F F H 0 0 0 0 H Direct addressing Register indirect addressing Based addressing F F 0 0 H F E F F H F F 2 0 H F F 1 F H F E 2 0 H F E 1 F H SFR addressing Short direct addressing F B 0 0 H F A F F H F A 1 C H F A 1 B H Reserved F A 0 0 H F 9 F F H Reserved Flash memory 32768 8 bits ...

Page 56: ...ressing F F F F H 0 0 0 0 H F F 0 0 H F E F F H F F 2 0 H F F 1 F H F E 2 0 H F E 1 F H F B 0 0 H F A F F H F A 1 C H F A 1 B H F 5 0 0 H F 4 F F H C 0 0 0 H B F F F H F A 0 0 H F 9 F F H F 7 0 0 H F 6 F F H Special function registers SFR 256 8 bits Internal high speed RAM 1024 8 bits LCD display RAM 28 4 bits Internal low speed RAM 512 8 bits Reserved Reserved Reserved Internal ROM 49152 8 bits ...

Page 57: ...t addressing F F F F H C 0 0 0 H B F F F H 0 0 0 0 H F F 0 0 H F E F F H F F 2 0 H F F 1 F H F E 2 0 H F E 1 F H F B 0 0 H F A F F H F A 1 C H F A 1 B H F 7 0 0 H F 6 F F H F A 0 0 H F 9 F F H F 5 0 0 H F 4 F F H Special function registers 256 8 bits Internal high speed RAM 1024 8 bits LCD display RAM 28 4 bits Internal low speed 512 8 bits Reserved Reserved Reserved Flash memory 49152 8 bits ...

Page 58: ...bytes of the instruction to be fetched When a branch instruction is executed immediate data or register contents are set RESET input sets the reset vector table values at addresses 0000H and 0001H to the program counter Figure 3 9 Program Counter Configuration 0 15 PC14 PC15 PC PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 2 Program status word PSW The program status word is an 8 bit...

Page 59: ...orresponding interrupt source IE is reset 0 upon DI instruction execution or interrupt acknowledgment and is set 1 upon EI instruction execution b Zero flag Z When the operation result is zero this flag is set 1 It is reset 0 in all other cases c Auxiliary carry flag AC If the operation result has a carry from bit 3 or a borrow at bit 3 this flag is set 1 It is reset 0 in all other cases d Carry f...

Page 60: ... restores data as shown in Figures 3 12 and 3 13 Caution Since RESET input makes the SP contents undefined be sure to initialize the SP before instruction execution Figure 3 12 Data to Be Saved to Stack Memory Interrupt PSW PC15 to PC8 PC15 to PC8 PC7 to PC0 Lower register pairs SP SP _ 2 SP _ 2 CALL CALLT instructions PUSH rp instruction SP _ 1 SP SP SP _ 2 SP _ 2 SP _ 1 SP PC7 to PC0 SP _ 3 SP _...

Page 61: ...s in pairs can be used as a 16 bit register AX BC DE and HL General purpose registers can be described in terms of function names X A C B E D L H AX BC DE or HL or absolute names R0 to R7 and RP0 to RP3 Figure 3 14 General Purpose Register Configuration a Absolute names R0 15 0 7 0 16 bit processing 8 bit processing RP3 RP2 RP1 RP0 R1 R2 R3 R4 R5 R6 R7 b Function names X 15 0 7 0 16 bit processing...

Page 62: ...rand sfr This manipulation can also be specified with an address 16 bit manipulation Describe the symbol reserved by the assembler for the 16 bit manipulation instruction operand When addressing an address describe an even address Table 3 4 lists the special function registers The meanings of the symbols in this table are as follows Symbol Indicates the addresses of the implemented special functio...

Page 63: ...t register 1A0 SIO1A0 R W 00H FF12H 16 bit multiplication result store register L MUL0L FF13H 16 bit multiplication result store register H MUL0H MUL0 Undefined FF14H FF15H A D conversion result register 0 ADCRL0 R 0000H FF16H FF17H 16 bit compare register 20 CR20 W FFFFH FF18H FF19H 16 bit timer counter 20 TM20 0000H FF1AH FF1BH 16 bit capture register 20 TCP20 R Undefined FF20H Port mode registe...

Page 64: ...GPHS compare register Note 2 RMGPHS FF67H Remote controller receive GPHL compare register Note 2 RMGPHL FF68H Remote controller receive DLS compare register Note 2 RMDLS FF69H Remote controller receive DLL compare register Note 2 RMDLL FF6AH Remote controller receive DH0S compare register Note 2 RMDH0S FF6BH Remote controller receive DH0L compare register Note 2 RMDH0L FF6CH Remote controller rece...

Page 65: ...al interface buffer memory D SBMEMD FFAEH Serial interface buffer memory E SBMEME FFAFH Serial interface buffer memory F SBMEMF Undefined FFB0H LCD mode register 0 LCDM0 FFB2H LCD clock control register 0 LCDC0 FFB3H LCD voltage boost control register 0 LCDVA0 R W 00H FFD0H Multiplication data register A0 MRA0 FFD1H Multiplication data register B0 MRB0 W Undefined FFD2H Multiplier control register...

Page 66: ...dressing Function The value obtained by adding 8 bit immediate data displacement value jdisp8 of an instruction code to the start address of the following instruction is transferred to the program counter PC and branched The displacement value is treated as signed two s complement data 128 to 127 and bit 7 becomes a sign bit This means that information is relatively branched to a location between ...

Page 67: ...transferred to the program counter PC and branched This function is carried out when the CALL addr16 or BR addr16 instruction is executed CALL addr16 and BR addr16 instructions can be branched to any location in the memory space Illustration In case of CALL addr16 and BR addr16 instructions 15 0 PC 8 7 7 0 CALL or BR Low Addr High Addr ...

Page 68: ...ted The instruction enables a branch to any location in the memory space by referring to the addresses stored in the memory table at 40H to 7FH Illustration 15 1 15 0 PC 7 0 Low Addr High Addr Memory Table Effective address 1 Effective address 0 1 0 0 0 0 0 0 0 0 8 7 8 7 6 5 0 0 0 0 1 7 6 5 1 0 ta4 0 Instruction code 3 3 4 Register addressing Function The register pair AX contents to be specified ...

Page 69: ...nstruction execution 3 4 1 Direct addressing Function The memory indicated with immediate data in an instruction word is directly addressed Operand format Identifier Description addr16 Label or 16 bit immediate data Description example MOV A FE00H When setting addr16 to FE00H Instruction code 0 0 1 0 1 0 0 1 OP code 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 00H FEH Illustration 7 0 OP code addr16 Lower addr...

Page 70: ...r event counter are mapped in this area and these SFRs can be manipulated with a small number of bytes and clocks When 8 bit immediate data is at 20H to FFH bit 8 of an effective address is set to 0 When it is at 00H to 1FH bit 8 is set to 1 See Illustration below Operand format Identifier Description saddr Label or FE20H to FF1FH immediate data saddrp Label or FE20H to FF1FH immediate data even a...

Page 71: ... word This addressing is applied to the 256 byte space FF00H to FFFFH However the SFRs mapped at FF00H to FF1FH can also be accessed with short direct addressing Operand format Identifier Description sfr Special function register name Description example MOV PM0 A When selecting PM0 for sfr Instruction code 1 1 1 0 0 1 1 1 0 0 1 0 0 0 0 0 Illustration 15 0 SFR Effective Address 1 1 1 1 1 1 1 8 7 0...

Page 72: ...rand format is executed When an 8 bit register is specified one of the eight registers is specified with 3 bits in the instruction code Operand format Identifier Description r X A C B E D L H rp AX BC DE HL r and rp can be described with absolute names R0 to R7 and RP0 to RP3 as well as function names X A C B E D L H AX BC DE and HL Description example MOV A C When selecting the C register for r I...

Page 73: ...The register pair to be accessed is specified by the register pair specification code in an instruction code This addressing can be carried out for all the memory spaces Operand format Identifier Description DE HL Description example MOV A DE When selecting register pair DE Instruction code 0 0 1 0 1 0 1 1 Illustration 15 0 8 D 7 E 0 7 7 0 A DE Addressed memory contents are transferred Memory addr...

Page 74: ...s Operand format Identifier Description HL byte Description example MOV A HL 10H When setting byte to 10H Instruction code 0 0 1 0 1 1 0 1 0 0 0 1 0 0 0 0 3 4 7 Stack addressing Function The stack area is indirectly addressed with the stack pointer SP contents This addressing method is automatically employed when the PUSH POP subroutine call and return instructions are executed or the register is ...

Page 75: ...merous other functions are provided that can be used in addition to the digital I O port functions For more information on these additional functions see CHAPTER 2 PIN FUNCTIONS Figure 4 1 Port Types P50 P00 Port 0 Port 5 P53 P07 P25 Port 6 P60 P67 P10 Port 1 P11 Port 2 P20 P34 Port 3 P30 P70 Port 7 P73 Port 8 P80 P87 Remark Ports 7 and 8 are used when the port function is selected by a mask optio...

Page 76: ...ort 6 P60 to P67 Input port Port 7 Note 1 P70 to P73 Input port only when input port is selected by mask option or port function register Port 8 Note 2 P80 to P87 I O port only when I O port is selected by mask option or port function register Notes 1 Whether to use these pins as input port pins P70 to P73 or segment outputs S16 to S19 can be selected in 1 bit units by means of a mask option in th...

Page 77: ... is also used for key return signal input RESET input sets this port to input mode Figure 4 2 shows a block diagram of port 0 Figure 4 2 Block Diagram of P00 to P07 WRKRM00 VDD P00 KR0 to P07 KR7Note 1 or P00 KR00 to P07 KR07Note 2 WRPUO RD WRPORT WRPM PUB00 to PUB07 PM00 to PM07 KRM000 KRM004 to KRM007 P ch Internal bus Selector Output latch P00 to P07 Alternate function KRM00 Key return mode reg...

Page 78: ...ut port pins on chip pull up resistors can be connected in 1 bit units by using pull up resistor option register B1 PUB1 RESET input sets this port to input mode Figure 4 3 shows a block diagram of port 1 Figure 4 3 Block Diagram of P10 and P11 PUB1 Pull up resistor option register B1 PM Port mode register RD Port 1 read signal WR Port 1 write signal WRPU0 RD WRPORT WRPM PUB10 PUB11 PM10 PM11 VDD ...

Page 79: ...put sets this port to input mode Figures 4 4 to 4 8 show block diagrams of port 2 Caution When using the pins of port 2 as the serial interface the I O or output latch must be set according to the function to be used For how to set the latches see Table 11 2 Serial Interface 20 Operation Mode Settings and 12 3 1 Serial operation mode register 1A0 CSIM1A0 Figure 4 4 Block Diagram of P20 Internal bu...

Page 80: ...D Figure 4 5 Block Diagram of P21 Internal bus VDD P21 SO20 TxD20 WRPUB2 RD WRPORT WRPM PUB21 Alternate function Output latch P21 PM21 Selector P ch PUB2 Pull up resistor option register B2 PM Port mode register RD Port 2 read signal WR Port 2 write signal ...

Page 81: ...ck Diagram of P22 and P25 P22 SI20 RxD20 P25 SI10 WRPUB2 RD WRPORT WRPM PUB22 PUB25 Alternate function Output latch P22 P25 PM22 PM25 VDD P ch Internal bus Selector PUB2 Pull up resistor option register B2 PM Port mode register RD Port 2 read signal WR Port 2 write signal ...

Page 82: ...e 4 7 Block Diagram of P23 Internal bus VDD P ch P23 SCK10 WRPUB2 RD WRPORT WRPM PUB23 Alternate function Output latch P23 PM23 Alternate function Selector PUB2 Pull up resistor option register B2 PM Port mode register RD Port 2 read signal WR Port 2 write signal ...

Page 83: ...D 83 Figure 4 8 Block Diagram of P24 Internal bus VDD P24 SO10 WRPUB2 RD WRPORT WRPM PUB24 Alternate function Output latch P24 PM24 Selector P ch PUB2 Pull up resistor option register B2 PM Port mode register RD Port 2 read signal WR Port 2 write signal ...

Page 84: ... used for external interrupt input capture input timer I O and remote control receive data inputNote RESET input sets this port to input mode Figures 4 9 and 4 10 show block diagrams of port 3 Note µ PD789489 and 78F9489 only Figure 4 9 Block Diagram of P30 to P33 PUB3 Pull up resistor option register B3 PM Port mode register RD Port 3 read signal WR Port 3 write signal P30 INTP0 TO50 TMI60 P31 IN...

Page 85: ...RPUB3 RD WRPORT WRPM PUB34 PM34 VDD P ch Internal bus Selector Output latch P34 b When µPD789489 78F9489 is used P34 RIN WRPUB3 RD WRPORT WRPM PUB34 PM34 VDD P ch Internal bus Selector Output latch P34 Alternate function PUB3 Pull up resistor option register B3 PM Port mode register RD Port 3 read signal WR Port 3 write signal ...

Page 86: ... of an on chip pull up resistor can be specified by a mask option RESET input sets this port to input mode Figure 4 11 shows a block diagram of port 5 Figure 4 11 Block Diagram of P50 to P53 Internal bus Selector RD PM50 to PM53 P50 to P53 N ch WRPORT Output latch P50 to P53 WRPM VDD Mask option resistor Mask ROM version only For a flash memory version a pull up resistor is not incorporated PM Por...

Page 87: ...his port is also used for the analog input of an A D converter and key return signal input Note Figure 4 12 shows a block diagram of port 6 Note µPD789489 and 78F9489 only Figure 4 12 Block Diagram of P60 to P67 1 2 a When µPD789488 78F9488 is used VREF RD A D converter P60 ANI0 to P67 ANI7 Internal bus ...

Page 88: ...1UD Figure 4 12 Block Diagram of P60 to P67 2 2 b When µPD789489 78F9489 is used VREF RD Alternate function P60 ANI0 KR10 to P67 ANI7 KR17 KRM010 KRM014 to KRM017 WRKRM01 A D converter Internal bus KRM01 Key return mode register 01 RD Port 6 read signal ...

Page 89: ... the bits for which the port function is selected can be used by using a mask option in the µPD789488 and 789489 or port function register 7 PF7 in the µPD78F9488 and 78F9489 Figure 4 13 shows a block diagram of port 7 Figure 4 13 Block Diagram of P70 to P73 P70 to P73 RD Internal bus RD Port 7 read signal ...

Page 90: ... port function register 8 PF8 in the µPD78F9488 and 78F9489 Port 8 can be specified in the input or output mode in 1 bit units by using port mode register 8 PM8 RESET input sets this port to input mode Figure 4 14 shows a block diagram of port 8 Figure 4 14 Block Diagram of P80 to P87 RD WRPORT WRPM Output latch P80 to P87 PM80 to PM87 P80 to P87 Internal bus Selector PM Port mode register RD Port...

Page 91: ...rrupt inputs when the output level changes after the output mode of the port function is specified the interrupt request flag will be inadvertently set Therefore be sure to preset the interrupt mask flag PMK0 to PMK3 before using the port in output mode Figure 4 15 Port Mode Register Format Symbol 7 6 5 4 3 2 1 0 Address After reset R W PM0 PM07 PM06 PM05 PM04 PM03 PM02 PM01 PM00 FF20H FFH R W PM1...

Page 92: ...nput 1 P31 TO60 Output 0 0 INTP2 Input 1 TMI61 Input 1 P32 TO61 Output 0 0 INTP3 Input 1 CPT20 Input 1 P33 TO20 Output 0 0 P34 RIN µPD789489 78F9489 only Input 1 Remark don t care PM Port mode register P Port output latch Caution When port 2 is used for the interface I O and output latch settings must be made in accordance with the function used For the setting method refer to Table 11 2 Serial In...

Page 93: ...1 PUB10 FF31H 00H R W 7 6 5 4 3 2 1 0 PUB2 0 0 PUB25 PUB24 PUB23 PUB22 PUB21 PUB20 FF32H 00H R W 7 6 5 4 3 2 1 0 PUB3 0 0 0 PUB34 PUB33 PUB32 PUB31 PUB30 FF33H 00H R W PUBmn Pmn on chip pull up resistor selection m 0 to 3 n 0 to 7 0 An on chip pull up resistor is not connected 1 An on chip pull up resistor is connected 3 Port function registers PF7 and PF8 µPD78F9488 78F9489 only These registers s...

Page 94: ...h of the pin that is set in the input mode and not subject to manipulation become undefined 4 4 2 Reading from I O port 1 In output mode The status of an output latch can be read by using a transfer instruction The contents of the output latch are not changed 2 In input mode The status of a pin can be read by using a transfer instruction The contents of the output latch are not changed 4 4 3 Arith...

Page 95: ...cillator This circuit oscillates at 32 768 kHz Oscillation can be stopped by the suboscillation mode register SCKM Also a circuit to multiply the subsystem clock by 4 can be used by setting a mask option or the subclock selection register SSCK 5 2 Clock Generator Configuration The clock generator includes the following hardware Table 5 1 Configuration of Clock Generator Item Configuration Control ...

Page 96: ...ller Mask option STOP MCC PCC1 CLS Internal bus CSS0 FRC SCC Internal bus Timer 50 Watch timer LCD controller driver Clock to peripheral hardware CPU clock fCPU Subclock control register CSS Processor clock control register PCC Subclock oscillation mode register SCKM Subsystem clock oscillator Subsystem clock oscillator 4 multiplication circuit 2 multiplication circuit Selector Remark fXTT fXT or ...

Page 97: ...lock to peripheral hardware Timer 50 Watch timer LCD controller driver CPU clock fCPU Standby controller Wait controller Selector STOP MCC PCC1 CLS CSS0 Internal bus Subclock oscillation mode register SCKM FRC SCC Internal bus Subclock control register CSS Processor clock control register PCC 4 multiplication circuit 2 multiplication circuit Selector Subclock selection register SSCK SCT fXTT 8fXT ...

Page 98: ... 0 Address After reset R W PCC MCC 0 0 0 0 0 PCC1 0 FFFBH 02H R W MCC Main system clock oscillator operation control 0 Operation enabled 1 Operation stopped Minimum instruction execution time 2 fCPU CSS0 PCC1 CPU clock fCPU selection Note fX 5 0 MHz or fXT 32 768 kHz 0 0 fX 0 4 µs 0 1 fX 2 2 1 6 µs 1 fXT 2 4fXT when 4 multiplication circuit is used 122 µs 15 26 µs when 4 multiplication circuit is ...

Page 99: ...e mid point of the supply voltage When the subclock is not used the power consumption in STOP mode can be further reduced by setting FRC 1 Caution Bits 2 to 7 must be set to 0 3 Subclock control register CSS CSS specifies whether the main system or subsystem clock oscillator is to be selected It also specifies the CPU clock operation status CSS is set with a 1 bit or 8 bit memory manipulation inst...

Page 100: ...g no operational effect Figure 5 6 Subclock Selection Register Format Symbol 7 6 5 4 3 2 1 0 Address After reset R W SSCK 0 0 0 0 0 0 0 SCT FF46H Retained Not e R W SCT Control of 4 subsystem clock multiplication circuit 0 Operation stopped subsystem clock source 32 768 kHz supplied to the CPU 1 Operation enabled clock that is the subsystem clock multiplied by 8 262 kHz supplied to the CPU Note Th...

Page 101: ...Main System Clock Oscillator a Crystal or ceramic oscillation b External clock Crystal or ceramic resonator VSS X2 X1 External clock X1 X2 Caution When using the main system clock oscillator wire as follows in the area enclosed by the broken lines in Figure 5 7 to avoid an adverse effect from wiring capacitance Keep the wiring length as short as possible Do not cross the wiring with the other sign...

Page 102: ...ernal clock XT1 XT2 Caution When using the main system or subsystem clock oscillator wire as follows in the area enclosed by the broken lines in Figures 5 7 and 5 8 to avoid an adverse effect from wiring capacitance Keep the wiring length as short as possible Do not cross the wiring with the other signal lines Do not route the wiring near a signal line through which a high fluctuating current flow...

Page 103: ...or Connection 1 2 a Too long wiring b Crossed signal line VSS X1 X2 VSS X1 X2 PORTn n 0 to 3 5 c Wiring near high fluctuating current d Current flowing through ground line of oscillator potential at points A B and C fluctuates VSS X1 X2 High current VSS X1 A B C Pmn VDD High current X2 Remark When using the subsystem clock read X1 and X2 as XT1 and XT2 respectively and connect a resistor to XT2 in...

Page 104: ...e the XT1 and XT2 pins as follows XT1 Connect to VSS XT2 Leave open In this case however a small current leaks via the on chip feedback resistor in the subsystem clock oscillator when the main system clock is stopped To avoid this set bit 1 FRC of the subclock oscillation mode register SCKM so that the on chip feedback resistor will not be used Also in this case handle the XT1 and XT2 pins as stat...

Page 105: ...ection register SSCK in the µPD78F9488 and 78F9489 15 26 µs a circuit to multiply the subsystem clock by 4 is used c Two standby modes STOP and HALT can be used with the main system clock selected In a system where the subsystem clock is not used setting bit 1 FRC of SCKM so that the on chip feedback resistor cannot be used reduces current consumption in STOP mode In a system where the subsystem c...

Page 106: ...y after the setting of PCC has been changed the old clock is used for the duration of several instructions after that see Table 5 2 Table 5 2 Maximum Time Required for Switching CPU Clock Set Value Before Switching Set Value After Switching CSS0 PCC1 CSS0 PCC1 CSS0 PCC1 CSS0 PCC1 0 0 0 1 1 x 0 0 4 clocks 2fX fXT clocks 306 clocks 1 2 clocks fX 2fXT clocks 76 clocks 1 x 2 clocks 2 clocks Remarks 1 ...

Page 107: ...5 0 MHz operation 2 After the time required for the VDD voltage to rise to the level at which the CPU can operate at high speed has elapsed bit 1 PCC1 of the processor clock control register PCC and bit 4 CSS0 of the subclock control register CSS are rewritten so that high speed operation can be selected 3 A drop of the VDD voltage is detected with an interrupt request signal The clock is switched...

Page 108: ...pare value match 3 Count value capture The count value of 16 bit timer counter 20 TM20 is latched into a capture register in synchronization with the capture trigger and retained 6 2 16 Bit Timer 20 Configuration 16 bit timer 20 includes the following hardware Table 6 1 16 Bit Timer 20 Configuration Item Configuration Timer counters 16 bits 1 TM20 Registers Compare register 16 bits 1 CR20 Capture ...

Page 109: ...H can be set RESET input sets this register to FFFFH Caution To rewrite CR20 during a count operation first set interrupt mask flag register 0 MK0 to disable interrupts Also set inversion inhibited for the timer output data in 16 bit timer mode control register 20 TMC20 If CR20 is rewritten while interrupts are enabled an interrupt request may be issued at the point of rewrite 2 16 bit timer count...

Page 110: ...er 20 16 bit timer 20 is controlled by the following three registers 16 bit timer mode control register 20 TMC20 Port mode register 3 PM3 Port 3 P3 1 16 bit timer mode control register 20 TMC20 16 bit timer mode control register 20 TMC20 controls the setting of the count clock capture edge etc TMC20 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets TMC20 to 00H ...

Page 111: ...s of CPT20 pin TOC20 Timer output data inversion control 0 Inversion disabled 1 Inversion enabled TCL201 TCL200 Selection of count clock for 16 bit timer counter 20 0 0 Timer 61 interrupt signal 0 1 fX 5 0 MHz Notes 2 3 1 0 fX 2 2 1 25 MHz Note 4 1 1 fX 2 5 156 25 kHz Note 4 TOE20 Output control for 16 bit timer counter 20 0 Output disabled port mode 1 Output enabled Notes 1 Bit 7 is read only 2 I...

Page 112: ...When using the above pin as a timer output TO20 set the PM33 and P33 output latches to 0 PM3 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets this register to FFH Figure 6 3 Format of Port Mode Register 3 Symbol 7 6 5 4 3 2 1 0 Address After reset R W PM3 1 1 1 PM34 PM33 PM32 PM31 PM30 FF23H FFH R W PM33 Selection of P33 pin I O mode 0 Output mode output buffer is on 1...

Page 113: ... flags are set to 0 the capture edge operation is prohibited When the count value of 16 bit timer counter 20 TM20 matches the value set in CR20 counting of TM20 continues and an interrupt request signal INTTM20 is generated Table 6 2 shows interval time and Figure 6 5 shows timing of timer interrupt operation Caution When rewriting the value in CR20 during a count operation be sure to execute the ...

Page 114: ...31EJ4V1UD Figure 6 5 Timing of Timer Interrupt Operation CR20 INTTM20 TO20 TOF20 N N N N N t 0000H N FFFFH N 0000H 0001H 0001H Count clock TM20 count value Interrupt acknowledgement Interrupt acknowledgement Overflow flag set Remark N 0000H to FFFFH ...

Page 115: ... 0 1 0 1 0 1 1 0 1 0 1 1 TOD20 TOF20 CPT201 CPT200 TOC20 TCL201 TCL200 TOE20 TMC20 Setting of count clock see Table 6 2 Inverse enable of timer output data TO20 output enable Caution If both the CPT201 flag and CPT200 flag are set to 0 the capture edge operation is prohibited When the count value of 16 bit timer counter 20 TM20 matches the value set in CR20 the output status of the TO20 pin is inv...

Page 116: ...ected and latches and retains the count value of 16 bit timer 20 TCP20 fetches the count value within 2 clocks and retains the count value until the next capture edge detection Table 6 3 and Figure 6 9 show the settings of the capture edge and the capture operation timing respectively Table 6 3 Settings of Capture Edge CPT201 CPT200 Capture Edge Selection 0 0 Capture operation prohibited 0 1 CPT20...

Page 117: ...nd TM20 starts free running Figure 6 10 shows the timing of 16 bit timer counter 20 readout Cautions 1 The count value after releasing stop becomes undefined because the count operation is executed during the oscillation stabilization time 2 Though TM20 is designed for a 16 bit transfer instruction an 8 bit transfer instruction can also be used When using an 8 bit transfer instruction execute it b...

Page 118: ...l of timer output TOC20 0 2 First rewrite the higher byte of CR20 16 bits 3 Then rewrite the lower byte of CR20 16 bits 4 Clear the interrupt request flag TMIF20 5 Enable timer interrupts timer output inversion after half a cycle or more of the count clock has elapsed from the start of the interrupt Program example A count clock 32 fX CPU clock fX TM20_VCT SET1 TMMK20 Disable timer interrupts 6 cl...

Page 119: ...sion Program example B count clock 32 fX CPU clock fX TM20_VCT SET1 TMMK20 Disable timer interrupts CLR1 TMC20 3 Disable timer output inversion MOVW A xxyyH Set the rewrite value of CR20 MOVW CR20 AX Rewrite CR20 NOP NOP 16 NOP instructions wait for 32 fX Note NOP NOP CLR1 TMIF20 Clear the interrupt request flag CLR1 TMMK20 Enable timer interrupts SET1 TMC20 3 Enable timer output inversion Note Cl...

Page 120: ...ble Available 1 Mode to use 8 bit timer event counter as discrete unit stand alone mode The following functions can be used in this mode Timer 50 Interval timer with 8 bit resolution Square wave output with 8 bit resolution Timer 60 and 61 Interval timer with 8 bit resolution External event counter with 8 bit resolution Square wave output with 8 bit resolution 2 Mode to use timer 50 and timer 60 c...

Page 121: ... 1 Select the timer 61 interrupt signal for the count clock of 16 bit timer 20 TCL201 0 TCL200 0 2 Set timer 61 in stand alone mode TMD611 0 Select the external clock input from pin TMI61 for the count clock of timer 61 TCL612 0 TCL611 1 or TCL612 1 TCL611 0 3 Set CR61 to FFH 4 Read the current count value of 16 bit timer 20 16 bit timer 20 does not have a count clear function and is counting cons...

Page 122: ... Timers 50 60 and 61 Item Configuration Timer counter 8 bits 3 TM50 TM60 TM61 Registers Compare registers 8 bits 5 CR50 CR60 CRH60 CR61 CRH61 Timer outputs 3 TO50 TO60 TO61 Control registers 8 bit timer mode control register 50 TMC50 8 bit timer mode control register 60 TMC60 Carrier generator output control register 60 TCA60 8 bit timer mode control register 61 TMC61 Port mode register 3 PM3 Port...

Page 123: ...e connection INTTM50 fX 23 fX 27 Timer 60 interrupt request signal from Figure 7 3 B Carrier clock from Figure 7 3 C Cascade connection mode Match Timer 60 match signal from Figure 7 3 E in cascade connection mode Internal bus OVF Bit 7 of TM60 from Figure 7 3 A A B C TOE50 P30 output latch PM30 Timer 50 match signal to Figure 7 3 F in cascade connection mode Timer 50 match signal to Figure 7 3 G ...

Page 124: ... bit compare register 60 CR60 Selector Output controllerNote To Figure 7 2 D D E F G C A B count clock signal input to TM50 INTTM60 To Figure 7 2 A Bit 7 of TM60 in cascade connection mode Timer counter match signal from timer 50 in Figure 7 2 G in carrier generator mode From Figure 7 2 F To Figure 7 2 E Match TO60 INTP1 P31 To Figure 7 2 C carrier clock Reset PPG mode Cascade connection mode 8 bi...

Page 125: ... Clear 8 bit compare register 61 CR61 Selector INTTM61 Match TO61 TMI61 INTP2 P32 Reset PPG mode 8 bit H width compare register 61 CRH61 Internal bus Selector Timer 61 interrupt request signal in 24 bit event counter mode To timer 20 count clock input signal in Figure 6 1 fX fX 24 TMI61 TO61 INTP2 P32 fTMI 2 fTMI 22 fTMI 23 fTMI Prescaler P32 output latch PM32 Figure 7 4 Block Diagram of Timer 61 ...

Page 126: ... TOE50 has been cleared 2 If both edges have been selected as the valid edge of the count clock in PWM output mode TEG50 1 do not set CR50 to 00H 01H or FFH Also if the rising edge has been selected as the valid edge TEG50 0 do not set CR50 to 00H 2 8 bit compare register 60 CR60 When connected to TM50 via a cascade connection and using as a 16 bit timer event counter the interrupt request INTTM60...

Page 127: ... RESET input sets these register values to 00H TM50 TM60 and TM61 are cleared to 00H under the following conditions a Stand alone mode After reset When TCEmn bit 7 of 8 bit timer mode control register mn TMCmn is cleared to 0 When a match occurs between TMmn and CRmn When the TMmn count value overflows Remark mn 50 60 61 b Cascade connection mode TM50 and TM60 are simultaneously cleared to 00H Aft...

Page 128: ...ol 7 6 5 4 3 2 1 0 Address After reset R W TMC50 TCE50 TEG50 TCL502 TCL501 TCL500 TMD501 TMD500 TOE50 FF4DH 00H R W TCE50 Control of TM50 count operation Note 1 0 Clear TM50 count value and stop operation 1 Start count operation TEG50 Selection of valid edge of TM50 count clock 0 Count at the rising edge of the count clock 1 Count at both edges of the count clock Note 2 TCL502 TCL501 TCL500 Select...

Page 129: ... combination of the TMC50 and TMC60 registers 4 Since timer 50 output is disabled in cascade connection mode set TOE50 to 0 Cautions 1 In cascade connection mode the timer 60 output signal is forcibly selected for the count clock 2 To manipulate TMC50 follow the setting procedure below 1 Set the TM50 count operation to stop 2 Set the operation mode and count clock 3 The count operation starts Rema...

Page 130: ... TMD501 TMD500 TMD601 TMD600 Selection of operation mode for timer 60 Note 2 0 0 0 Stand alone mode 8 bit counter mode 0 1 0 1 16 bit counter mode cascade connection mode 0 0 1 1 Carrier generator mode 0 1 0 PPG output mode Other than above Setting prohibited TOE600 Control of timer output 0 Output disabled 1 Output enabled Notes 1 Since the count operation is controlled by TCE60 bit 7 of TMC60 in...

Page 131: ... pin NRZB60 This is the bit that stores the next data to be output to NRZ60 When a match signal occurs for a match with timer 50 the data is output to NRZ60 NRZ60 No return zero data 0 Output low level signal carrier clock is stopped 1 Output carrier pulse or high level signal Note Bit 0 is write only Cautions 1 At the count start input the values of the data reloaded from NRZB60 to NRZ60 For NRZB...

Page 132: ... TCL610 Selection of timer 61 count clock Note 0 0 0 fX 5 0 MHz 0 0 1 fX 2 4 313 kHz 0 1 0 fTMI 0 1 1 fTMI 2 1 0 0 fTMI 2 2 1 0 1 fTMI 2 3 Other than above Setting prohibited TMD611 TMD610 Selection of operation mode for timer 61 Note 0 0 Stand alone mode 8 bit counter mode 1 0 PPG output mode Other than above Setting prohibited TOE610 Control of timer output 0 Output disabled 1 Output enabled Not...

Page 133: ... timer output TO60 set PM31 and the P31 output latch to 0 When using the P32 INTP2 TO61 TMI61 pin as a timer input TMI61 set PM32 to 1 When used as a timer output TO61 set PM32 and the P32 output latch to 0 PM3 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets this register to FFH Figure 7 10 Format of Port Mode Register 3 Symbol 7 6 5 4 3 2 1 0 Address After reset R W ...

Page 134: ...ttings must be made in the following sequence 1 Disable operation of 8 bit timer counter nm TMnm TCEnm 0 2 For timer 50 disable timer output of TO50 TOE50 0 For timer 60 disable timer output of TO60 TOE600 0 For timer 61 disable timer output of TO61 TOE610 0 3 Set a count value in CRnm 4 Set the operation mode of timer nm to 8 bit timer counter mode see Figures 7 6 7 7 and 7 9 5 Set the count cloc...

Page 135: ... µs 1 fX 0 2 µs 0 0 1 2 2 fX 0 8 µs 2 10 fX 204 µs 2 2 fX 0 8 µs 0 1 0 fTMI input cycle fTMI input cycle 2 8 fTMI input cycle 0 1 1 fTMI 2 input cycle fTMI 2 input cycle 2 8 fTMI 2 input cycle 1 0 0 fTMI 2 2 input cycle fTMI 2 2 input cycle 2 8 fTMI 2 2 input cycle 1 0 1 fTMI 2 3 input cycle fTMI 2 3 input cycle 2 8 fTMI 2 3 input cycle Remarks 1 fX Main system clock oscillation frequency 2 fTMI E...

Page 136: ...m N 00H 01H N 00H 01H N 00H 00H 01H 00H 01H Clear Clear Clear Count start Interrupt acknowledgement Interrupt acknowledgement Interrupt acknowledgement Interval time Interval time Remarks 1 Interval time N 1 t N 00H to FFH 2 nm 50 60 61 Figure 7 12 Timing of Interval Timer Operation with 8 Bit Resolution When CRnm Is Set to 00H Count clock CRnm TCEnm INTTMnm TOnm 00H TMnm 00H Count start Remark nm...

Page 137: ...FFH 00H 01H 00H 01H 00H FFH 00H 01H FFH FFH 00H Clear Clear Clear Count start Remark nm 50 60 61 Figure 7 14 Timing of Interval Timer Operation with 8 Bit Resolution When CRnm Changes from N to M N M Count clock CRnm TCEnm INTTMnm TOnm TMnm N 00H 00H N 00H 01H 00H 01H M N M N M Clear Clear Clear Count start Interrupt acknowledgement Interrupt acknowledgement CRnm overwritten Remark 00H N M FFH nm ...

Page 138: ...ure 7 15 Timing of Interval Timer Operation with 8 Bit Resolution When CRnm Changes from N to M N M Count clock CRnm TCEnm INTTMnm TOnm TMnm 00H 00H 00H N 1 N M N M N M 00H FFH M H Clear Clear Clear TMnm overflows because M N CRnm overwritten Remark 00H M N FFH nm 50 60 61 ...

Page 139: ...ion When Timer 60 Match Signal Is Selected for Timer 50 Count Clock Timer 60 count clock CR60 TCE60 INTTM60 TO60 TM60 N 00H M 00H 00H 01H M N M 00H M 00H 00H 01H Y 1 Y 00H Y 00H Y Input clock to timer 50 timer 60 match signal TO50 INTTM50 TCE50 CR50 TM50 Clear Clear Clear Clear Count start Count start Remark 00H N M FFH Y 00H to FFH ...

Page 140: ...ck for timer 6m see Figures 7 7 and 7 9 5 Set the operation mode of timer 6m to 8 bit timer counter mode see Figures 7 7 and 7 9 6 Set a count value in CR6m 7 Enable the operation of TM6m TCE6m 1 Each time the valid edge is input the value of TM6m is incremented When the count value of TM6m matches the value set in CR6m TM6m is cleared to 00H and continues counting At the same time an interrupt re...

Page 141: ...l be inverted Through application of this mechanism square waves of any frequency can be output As soon as a match occurs TMnm is cleared to 00H and continues counting At the same time an interrupt request signal INTTMnm is generated The square wave output is cleared to 0 by setting TCEnm to 0 Tables 7 6 to 7 8 show the square wave output range and Figure 7 18 shows the timing of square wave outpu...

Page 142: ...r 61 TCL612 TCL611 TCL610 Minimum Pulse Width Maximum Pulse Width Resolution 0 0 0 1 fX 0 2 µs 2 8 fX 51 2 µs 1 fX 0 2 µs 0 0 1 2 4 fX 3 2 µs 2 12 fX 819 µs 2 4 fX 3 2 µs 0 1 0 fTMI input cycle fTMI input cycle 2 8 fTMI input cycle 0 1 1 fTMI 2 input cycle fTMI 2 input cycle 2 8 fTMI 2 input cycle 1 0 0 fTMI 2 2 input cycle fTMI 2 2 input cycle 2 8 fTMI 2 2 input cycle 1 0 1 fTMI 2 3 input cycle f...

Page 143: ...ollowing sequence 1 Disable operation of 8 bit timer counter 50 TM50 and 8 bit timer counter 60 TM60 TCE50 0 TCE60 0 2 Disable timer output of TO60 TOE600 0 3 Set the count clock for timer 60 see Figure 7 7 4 Set the operation mode of timer 50 and timer 60 to 16 bit timer counter mode see Figures 7 6 and 7 7 5 Set a count value in CR50 and CR60 6 Enable the operation of TM50 and TM60 TCE60 1Note N...

Page 144: ...2 18 fX 52 4 ms 2 2 fX 0 8 µs 0 1 0 fTMI input cycle fTMI input cycle 2 16 fTMI input cycle 0 1 1 fTMI 2 input cycle fTMI 2 input cycle 2 16 fTMI 2 input cycle 1 0 0 fTMI 2 2 input cycle fTMI 2 2 input cycle 2 16 fTMI 2 2 input cycle 1 0 1 fTMI 2 3 input cycle fTMI 2 3 input cycle 2 16 fTMI 2 3 input cycle Remarks 1 fX Main system clock oscillation frequency 2 fTMI External input clock frequency 3...

Page 145: ...pulse TM50 00H X X 1 01H CR50 X X X 7FH 80H FFH 00H N 00H N N N X X 1 00H t Not cleared because TM50 does not match Cleared because TM50 and TM60 match simultaneously Count start Interrupt not generated because TM50 does not match Interrupt acknowledgement Interrupt acknowledgement Remark Interval time 256X N 1 t X 00H to FFH N 00H to FFH Figure 7 19 Timing of Interval Timer Operation with 16 Bit ...

Page 146: ...nd timer 60 to 16 bit timer counter mode see Figures 7 6 and 7 7 6 Set a count value in CR50 and CR60 7 Enable the operation of TM50 and TM60 TCE60 1Note Note Start and clear of the timer in the 16 bit timer counter mode are controlled by TCE60 the value of TCE50 is invalid Each time the valid edge is input the values of TM50 and TM60 are incremented When the count values of TM50 and TM60 simultan...

Page 147: ...t pulse TM50 00H X 01H CR50 X X X 7FH 80H FFH 00H N 00H N N N X X 1 00H X 1 Not cleared because TM50 does not match Cleared because TM50 and TM60 match simultaneously Count start Interrupt not generated because TM50 does not match Interrupt acknowledgement Interrupt acknowledgement Remark X 00H to FFH N 00H to FFH Figure 7 20 Timing of External Event Counter Operation with 16 Bit Resolution ...

Page 148: ... Through application of this mechanism square waves of any frequency can be output As soon as a match occurs TM50 and TM60 are cleared to 00H and continue counting At the same time an interrupt request signal INTTM60 is generated INTTM50 is not generated The square wave output is cleared to 0 by setting TCE60 to 0 Table 7 10 shows the square wave output range and Figure 7 21 shows timing of square...

Page 149: ...1H CR50 X X X 7FH 80H FFH 00H N 00H N N N X X 1 00H Not cleared because TM50 does not match Cleared because TM50 and TM60 match simultaneously Count start Interrupt not generated because TM50 does not match Interrupt acknowledgement Interrupt acknowledgement Note The initial value of TO60 is low level when output is enabled Remark X 00H to FFH N 00H to FFH Figure 7 21 Timing of Square Wave Output ...

Page 150: ...TTM60 is generated and output of timer 60 is inverted which makes the compare register switch from CR60 to CRH60 2 After that when the count value of TM60 matches the value set in CRH60 an interrupt request signal INTTM60 is generated and output of timer 60 is inverted again which makes the compare register switch from CRH60 to CR60 3 The carrier clock is generated by repeating 1 and 2 above 4 Whe...

Page 151: ...M M N TM60 count clock TM60 count value CR60 TCE60 INTTM60 M 00H N 00H 01H N CRH60 M N 00H Carrier clock N 00H 00H N M 00H 01H L L 00H 01H L 00H 01H L 00H L 00H 01H TM50 count value CR50 TCE50 INTTM50 TM50 count clock 0 1 0 1 0 0 1 0 1 0 NRZB60 NRZ60 TO60 Carrier clock Clear Clear Clear Clear Count start Remark 00H N M FFH L 00H to FFH ...

Page 152: ...0 M M N TM60 count clock TM60 count value CR60 TCE60 INTTM60 N 00H N L CRH60 M Carrier clock N 00H 00H 01H L 00H 01H L 00H 01H L 00H L 00H 01H TM50 count value CR50 TCE50 INTTM50 TM50 count clock 0 1 0 1 0 0 1 0 1 0 NRZB60 NRZ60 TO60 Carrier clock M 00H M M 00H M 00H Clear Clear Clear Clear Count start Remark 00H M N FFH L 00H to FFH ...

Page 153: ...TM60 count clock TM60 count value CR60 TCE60 INTTM60 N 00H 00H 00H N CRH60 N N Carrier clock 00H 00H N N 00H 01H L 00H 01H L 00H 01H L 00H L 00H 01H TM50 count value CR50 TCE50 INTTM50 TM50 count clock 0 1 0 1 0 0 1 0 1 0 NRZB60 NRZ60 TO60 Carrier clock N N 00H Clear Clear Clear Clear Clear Count start L Remark N 00H to FFH L 00H to FFH ...

Page 154: ...latch to 0 and enable timer output of TO50 TOE50 1 7 Enable the operation of TM50 TCE50 1 The operation in the PWM output mode is as follows 1 When the count value of TM50 matches the value set in CR50 an interrupt request signal INTTM50 is generated and a low level is output by the TO50 The TM50 continues counting without being cleared 2 TO50 outputs a high level when the TM50 overflows A pulse o...

Page 155: ... clock CR50 TCE50 INTTM50 TO50 N TM50 N 00H 00H 00H 01H FFH M FFH 01H M Overflow Overflow Overflow Count start CR50 overwrite 2 When setting CR50 TM50 after overflow Count clock CR50 TCE50 INTTM50 TO50 N TM50 N 00H 00H 00H 01H FFH FFH 01H 01H 02H 01H Overflow Overflow Overflow Count start CR50 overwrite Overflow occurs but no change takes place because TO50 is high level Remark N M 00H to FFH ...

Page 156: ...0 2N TM50 2N 00H 00H 01H FFH FFH 2N 02H FEH 01H 02H FEH Overflow Overflow Count start 2 When CR50 Odd number Count clock CR50 TCE50 INTTM50 TO50 2N 1 TM50 2N 1 00H 00H 01H FFH FFH 2N 1 01H 01H 00H Overflow Overflow Overflow Count start Caution When both edges are selected do not set CR50 to 00H 01H and FFH If CR50 is set to these values PWM output may not be performed normally Remark N 00H to FFH ...

Page 157: ...igure 7 28 Operation Timing in PWM Output Mode When Both Edges Are Selected When CR50 Is Overwritten Count clock CR50 TCE50 INTTM50 TO50 2N 1 TM50 2N 00H 00H 00H 01H FFH FFH 01H 2N 1 01H 02H FEH 2N Overflow Overflow Overflow Count start CR50 overwrite Remark N 00H to FFH ...

Page 158: ...nd the P32 output latch to 0 respectively 7 Enable timer output of TO6m TOE6m0 1 8 Enable the operation of TM6m TCE6m 1 The operation in the PPG output mode is as follows 1 When the count value of TM6m matches the value set in CR6m an interrupt request signal INTTM6m is generated and output of timer 6m is inverted which makes the compare register switch from CR6m to CRH6m 2 A match between TM6m an...

Page 159: ...r Clear Count start Note The initial value of TO6m is low level when output is enabled TOE6m0 1 Remark N M 00H to FFH m 0 1 Figure 7 30 PPG Output Mode Timing When CR6m and CRH6m Are Overwritten Count clock TM6m count value CR6m TCE6m INTTM6m 00H N 00H 01H N CRH6m M N TO6mNote M X Y 00H 00H X 00H X Y M Clear Clear Clear Clear Count start Note The initial value of TO6m is low level when output is e...

Page 160: ...s 8 bit timer counter n0 TMn0 Count pulse Clear signal Selected clock TCEn0 Delay A Delay B Selected clock TCEn0 Clear signal Count pulse TMn0 counter value 00H 01H 02H 03H Delay A Delay B An error of up to 1 5 clocks occurs if the timer is started when the selected clock is high and delay A delay B Remark nm 50 60 61 2 Setting of 8 bit compare register nm 8 bit compare register nm CRnm can be set...

Page 161: ...used at the same time Figure 8 1 shows a block diagram of the watch timer Figure 8 1 Block Diagram of Watch Timer fX 27 fXT 2 fXT Selector Selector fW fW 24 fW 25 fW 26 fW 27 fW 28 fW 29 Clear 9 bit prescaler Selector Clear 5 bit counter INTWT INTWTI WTM7 WTS WTM6 WTM5 WTM4 WTM1 WTM0 Watch timer mode control register WTM Watch timer interrupt time selection register WTIM Internal bus 1 2 ...

Page 162: ... occurs at preset intervals Table 8 1 Interval Time of Interval Timer Interval Time At fX 5 0 MHz At fX 4 19 MHz At fXT 32 768 kHz At fXT 2 16 384 kHz 2 4 1 fW 409 6 µs 488 µs 488 µs 976 µs 2 5 1 fW 819 2 µs 977 µs 977 µs 1 95 ms 2 6 1 fW 1 64 ms 1 95 ms 1 95 ms 3 90 ms 2 7 1 fW 3 28 ms 3 91 ms 3 91 ms 7 82 ms 2 8 1 fW 6 55 ms 7 81 ms 7 81 ms 15 6 ms 2 9 1 fW 13 1 ms 15 6 ms 15 6 ms 31 2 ms Remark...

Page 163: ...M6 WTM5 WTM4 0 0 WTM1 WTM0 FF4AH 00H R W WTM7 Selection of watch timer count clock fW 0 fX 2 7 39 1 kHz 1 fXT 32 768 kHz or fXT 2 16 384 kHz Note WTM6 WTM5 WTM4 Selection of prescaler interval time 0 0 0 2 4 fW 0 0 1 2 5 fW 0 1 0 2 6 fW 0 1 1 2 7 fW 1 0 0 2 8 fW 1 0 1 2 9 fW Other than above Setting prohibited WTM1 Control of 5 bit counter operation 0 Cleared after stopping operation 1 Start WTM0 ...

Page 164: ...is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets this register to 00H Figure 8 3 Format of Watch Timer Interrupt Time Selection Register Symbol 7 6 5 4 3 2 1 0 Address After reset R W WTIM 0 0 0 0 0 0 0 WTS FF4BH 00H R W WTS Selection of watch timer interrupt time Note 0 0 5 s fXT 1 1 0 s fXT 2 Note The selection is only available when bit 7 WTM7 of the watch timer mod...

Page 165: ... at the same time In this case however an error of up to 29 1 fW seconds may occur in the overflow INTWT after the zero second start of the watch timer because the 9 bit prescaler is not cleared to 0 8 4 2 Operation as interval timer The interval timer is used to repeatedly generate an interrupt request at the interval specified by a preset count value The interval can be selected by bits 4 to 6 W...

Page 166: ... and 5 bit counter operation is enabled by setting bit 0 WTM0 of the watch timer mode control register WTM to 1 the interval until the first interrupt request INTWT is generated after the register is set does not exactly match the watch timer interrupt time 0 5 s This is because there is a delay of one 9 bit pre scaler output cycle until the 5 bit counter starts counting Subsequently however the I...

Page 167: ... program loop is detected a non maskable interrupt or the RESET signal can be generated Table 9 1 Watchdog Timer Program Loop Detection Time Program Loop Detection Time At fX 5 0 MHz 2 11 1 fX 410 µs 2 13 1 fX 1 64 ms 2 15 1 fX 6 55 ms 2 17 1 fX 26 2 ms fX Main system clock oscillation frequency 2 Interval timer The interval timer generates an interrupt at an arbitrary preset interval Table 9 2 In...

Page 168: ...chdog timer clock selection register WDCS Watchdog timer mode register WDTM Figure 9 1 Block Diagram of Watchdog Timer Internal bus Internal bus Prescaler Selector Controller fX 26 fX 28 fX 210 3 7 bit counter WDTIF WDTMK WDCS2 WDCS1 WDCS0 Watchdog timer clock selection register WDCS Watchdog timer mode register WDTM Clear WDTM4 RUN WDTM3 INTWDT Maskable interrupt request RESET INTWDT Non maskable...

Page 169: ... manipulation instruction RESET input sets WDCS to 00H Figure 9 2 Format of Watchdog Timer Clock Selection Register WDCS2 0 0 1 1 WDCS1 0 1 0 1 fX 24 fX 26 fX 28 fX 210 312 5 kHz 78 1 kHz 19 5 kHz 4 88 kHz WDCS0 0 0 0 0 Setting prohibited Other than above Watchdog timer count clock selection 211 fX 213 fX 215 fX 217 fX 410 s 1 64 ms 6 55 ms 26 2 ms Interval µ 0 0 0 0 0 WDCS2 WDCS1 WDCS0 WDCS 7 6 5...

Page 170: ... 2 a reset operation is started upon overflow occurrence 0 0 RUN 0 0 WDTM4 WDTM3 0 0 0 WDTM 7 6 5 4 Symbol Address After reset R W FFF9H 00H R W 3 2 1 0 Notes 1 Once RUN has been set 1 it cannot be cleared 0 by software Therefore when counting is started it cannot be stopped by any means other than RESET input 2 Once WDTM3 and WDTM4 have been set 1 they cannot be cleared 0 by software 3 The watchd...

Page 171: ...e program loop detection time is exceeded a system reset signal or a non maskable interrupt is generated depending on the value of bit 3 WDTM3 of WDTM The watchdog timer continues operation in HALT mode but stops in STOP mode Therefore first set RUN to 1 to clear the watchdog timer before executing the STOP instruction Cautions 1 The actual program loop detection time may be up to 0 8 shorter than...

Page 172: ...rupt mask flag WDTMK is valid and a maskable interrupt INTWDT can be generated The priority of INTWDT is set as the highest of all the maskable interrupts The interval timer continues operation in HALT mode but stops in STOP mode Therefore first set RUN to 1 to clear the interval timer before executing the STOP instruction Cautions 1 Once bit 4 WDTM4 of WDTM is set to 1 when watchdog timer mode is...

Page 173: ...to ANI7 is selected for A D conversion A D conversion is performed repeatedly with an interrupt request INTAD0 being issued each time A D conversion is complete 10 2 10 Bit A D Converter Configuration The 10 bit A D converter includes the following hardware Table 10 1 Configuration of 10 Bit A D Converter Item Configuration Analog inputs 8 channels ANI0 to ANI7 Registers Successive approximation r...

Page 174: ...rom the series resistor string starting from the most significant bit MSB Upon receiving all the bits down to the least significant bit LSB that is upon the completion of A D conversion the SAR sends its contents to A D conversion result register 0 ADCRL0 2 A D conversion result register 0 ADCRL0 ADCRL0 is a 16 bit register that holds the result of A D conversion The lower 6 bits are fixed to 0 Ea...

Page 175: ... supply the ANI0 to ANI7 pins with voltages that fall outside the rated range If a voltage greater than or equal to AVDD or less than or equal to AVSS even if within the absolute maximum rating is applied to any of these pins the conversion value for the corresponding channel will be undefined Furthermore the conversion values for the other channels may also be affected 7 AVSS pin The AVSS pin is ...

Page 176: ...ode Register 0 A D conversion control ADCS0 0 1 A D conversion time selectionNote 1 FR02 0 0 0 1 1 1 144 fX 120 fX 96 fX 72 fX 60 fX 48 fX FR01 0 0 1 0 0 1 28 8 s 24 s 19 2 s 14 4 s Setting prohibitedNote 2 Setting prohibitedNote 2 µ µ µ FR00 0 1 0 0 1 0 Other than above Conversion disabled Conversion enabled Control of band gap circuit ADCE0 0 1 Band gap circuit stopped Band gap circuit operating...

Page 177: ...next A D conversion 3 Always set bits 1 2 and 6 to 0 Remarks 1 fX Main system clock oscillation frequency 2 The parenthesized values apply to operation at fX 5 0 MHz 2 Analog input channel specification register 0 ADS0 ADS0 specifies the port used to input the analog voltage to be converted to a digital signal ADS0 is set with a 1 bit or 8 bit memory manipulation instruction RESET input clears ADS...

Page 178: ...r than half of AVDD the MSB of SAR is left set If it is lower than half of AVDD the MSB is reset 7 Bit 8 of SAR is set automatically and comparison shifts to the next stage The next tap voltage of the series resistor string is selected according to bit 9 which reflects the previous comparison result as follows Bit 9 1 Three quarters of AVDD Bit 9 0 One quarter of AVDD The tap voltage is compared w...

Page 179: ...is case A D conversion is restarted from the beginning if ADCS0 is set 1 RESET input clears A D conversion result register 0 ADCRL0 to 0000H 10 4 2 Input voltage and conversion result The relationship between the analog input voltage at the analog input pins ANI0 to ANI7 and the A D conversion result A D conversion result register 0 ADCRL0 is represented by ADCRL0 INT 1 024 0 5 or ADCRL0 0 5 VIN A...

Page 180: ... Figure 10 5 Relationship Between Analog Input Voltage and A D Conversion Result 1 023 1 022 1 021 3 2 1 0 A D conversion result ADCRL0 1 2 048 1 1 024 3 2 048 2 1 024 5 2 048 3 1 024 2 043 2 048 1 022 1 024 2 045 2 048 1 023 1 024 2 047 2 048 1 Input voltage AVDD ...

Page 181: ...log input channel specification register 0 ADS0 Upon completion of A D conversion the conversion result is saved to A D conversion result register 0 ADCRL0 At the same time an interrupt request signal INTAD0 is generated Once A D conversion is activated and completed another session of A D conversion is started A D conversion is repeated until new data is written to ADML0 If data where ADCS0 is 1 ...

Page 182: ... channels 3 Conflict 1 Conflict between writing to A D conversion result register 0 ADCRL0 at the end of conversion and reading from ADCRL0 using instruction Reading from ADCRL0 takes precedence After reading the new conversion result is written to ADCRL0 2 Conflict between writing to ADCRL0 at the end of conversion and writing to A D converter mode register 0 ADML0 or analog input channel specifi...

Page 183: ...s been stopped stop the A D conversion operation before the next conversion operation is completed Figures 10 8 and 10 9 show the timing at which the conversion result is read Figure 10 8 Conversion Result Read Timing if Conversion Result Is Undefined End of A D conversion End of A D conversion Normal conversion result Undefined value Normal conversion result is read A D conversion stops Undefined...

Page 184: ...I7 has been selected for A D conversion do not execute input instructions for the ports otherwise the conversion resolution may be reduced If a digital pulse is applied to a pin adjacent to the analog input pins during A D conversion coupling noise may occur that prevents an A D conversion result from being obtained as expected Avoid applying a digital pulse to pins adjacent to the analog input pi...

Page 185: ...DCRL0 INTAD0 Rewriting ADML0 to begin conversion for ANIn Rewriting ADML0 to begin conversion for ANIm ADIF0 has been set but conversion for ANIm has not been completed ANIn ANIn ANIm ANIm ANIn ANIn ANIm ANIm Remarks 1 n 0 to 7 2 m 0 to 7 10 AVDD pin The AVDD pin is used to supply power to the analog circuit It is also used to supply power to the ANI0 to ANI7 input circuit If your application is d...

Page 186: ...SO20 As it supports simultaneous transmission and reception 3 wire serial I O mode requires less processing time for data transmission than asynchronous serial interface mode Because in 3 wire serial I O mode it is possible to select whether 8 bit data transmission begins with the MSB or LSB serial interface 20 can be connected to any device regardless of whether that device is designed for MSB fi...

Page 187: ...0 4 Parity detection Detection of stop bit Receive data counter Parity operation Addition of stop bit Transmit data counter SL20 CL20 PS200 PS201 Reception enable Receive clock Detection clock Detection of start bit Port mode register PM20 CSIE20 CSCK20 SCK20 P20 ASCK20 Receive detection Internal clock output External clock input Transmit receive clock control Baud rate generatorNote 4 TPS203 TPS2...

Page 188: ...eceive detection TXE20 RXE20 CSIE20 1 2 1 2 Transmit clock counter 3 bits Receive clock counter 3 bits 4 fX 2 fX 23 fX 24 fX 25 fX 26 fX 27 fX 28 fX 22 ASCK20 SCK20 P20 TPS203 TPS202 TPS201 TPS200 Baud rate generator control register 20 BRGC20 Internal bus Selector Selector Selector Figure 11 2 Block Diagram of Baud Rate Generator 20 ...

Page 189: ...m 3 Receive buffer register 20 RXB20 RXB20 holds receive data New receive data is transferred from receive shift register 20 RXS20 at every 1 byte data reception When the data length is seven bits the receive data is sent to bits 0 to 6 of RXB20 in which the MSB is always fixed to 0 RXB20 can be read with an 8 bit memory manipulation instruction but cannot be written RESET input makes RXB20 undefi...

Page 190: ...nstruction RESET input sets CSIM20 to 00H Figure 11 3 Format of Serial Operation Mode Register 20 CSIE20 0 1 3 wire serial I O mode operation control CSIE20 0 0 0 0 DIR20 CSCK20 0 CSIM20 Symbol Address After reset R W FF72H 00H R W 7 6 5 4 3 2 1 0 Operation disabled Operation enabled DIR20 0 1 First bit specification MSB LSB CSCK20 0 1 3 wire serial I O mode clock selection External clock input to...

Page 191: ...R W FF70H 00H R W 7 6 5 4 3 2 1 0 Transmit operation stopped Transmit operation enabled RXE20 0 1 Receive operation control Receive operation stopped Receive operation enabled PS201 0 0 1 1 Parity bit specification PS200 0 1 0 1 No parity Always add 0 parity at transmission Parity check is not performed at reception no parity error is generated Odd parity Even parity CL20 0 1 Transmit data charact...

Page 192: ...ock SCK20 output 0 1 External clock SCK20 input 0 0 1 1 1 1Note 2 Note 2 0 1 0 1 LSB Internal clock SI20Note 2 SO20 CMOS output SCK20 output Other than above Setting prohibited 3 Asynchronous serial interface mode ASIM20 CSIM20 TXE20 RXE20 CSIE20 DIR20 CSCK20 PM22 P22 PM21 P21 PM20 P20 First Bit Shift Clock P22 SI20 RxD20 Pin Function P21 SO20 TxD20 Pin Function P20 SCK20 ASCK20 Pin Function 1 Ext...

Page 193: ...7 6 5 4 3 2 1 0 No parity error occurred A parity error occurred when the transmit parity and receive parity did not match FE20 0 1 Framing error flag No framing error occurred A framing error occurred when stop bit was not detected Note 1 OVE20 0 1 Overrun error flag No overrun error occurred An overrun error occurredNote 2 when the next receive operation was completed before the data was read fr...

Page 194: ...ibited 2 5 MHz 1 25 MHz 625 kHz 313 kHz 156 kHz 78 1 kHz 39 1 kHz 19 5 kHz Other than above TPS201 0 0 1 1 0 0 1 1 0 TPS200 0 1 0 1 0 1 0 1 0 n 1 2 3 4 5 6 7 8 Note An external clock can be used only in UART mode Cautions 1 When writing to BRGC20 during a communication operation the output of the baud rate generator is disrupted and communications cannot be performed normally Be sure not to write ...

Page 195: ...ate of a clock generated from the system clock is estimated by using the following expression Baud rate bps fX Main system clock oscillation frequency n Values in Figure 11 6 determined by the values of TPS200 to TPS203 2 n 8 Table 11 3 Example of Relationship Between System Clock and Baud Rate Error Baud Rate bps n BRGC20 Set Value fX 5 0 MHz fX 4 9152 MHz 1 200 8 70H 2 400 7 60H 4 800 6 50H 9 60...

Page 196: ... Input Frequency and Baud Rate When BRGC20 Is Set to 80H Baud Rate bps ASCK20 Pin Input Frequency kHz 75 1 2 150 2 4 300 4 8 600 9 6 1 200 19 2 2 400 38 4 4 800 76 8 9 600 153 6 19 200 307 2 31 250 500 0 38 400 614 4 c Generation of serial clock from system clock in 3 wire serial I O The serial clock is generated by dividing the system clock The frequency of the serial clock can be obtained by the...

Page 197: ... TxD20 and P22 SI20 RxD20 pins can be used as normal I O ports 1 Register setting Operation stop mode is set by serial operation mode register 20 CSIM20 and asynchronous serial interface mode register 20 ASIM20 a Serial operation mode register 20 CSIM20 CSIM20 is set with a 1 bit or 8 bit memory manipulation instruction RESET input clears CSIM20 to 00H CSIE20 0 1 Operation control in 3 wire serial...

Page 198: ...ation instruction RESET input sets ASIM20 to 00H TXE20 0 1 Transmit operation control Transmit operation stopped Transmit operation enabled Receive operation stopped Receive operation enabled RXE20 0 1 Receive operation control TXE20 RXE20 PS201 PS200 CL20 SL20 0 0 ASIM20 7 6 5 4 Symbol Address After reset R W FF70H 00H R W 3 2 1 0 Caution Bits 0 and 1 must be set to 0 ...

Page 199: ...nterface mode register 20 ASIM20 asynchronous serial interface status register 20 ASIS20 baud rate generator control register 20 BRGC20 port mode register 2 PM2 and port 2 P2 a Serial operation mode register 20 CSIM20 CSIM20 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets CSIM20 to 00H Set CSIM20 to 00H when UART mode is selected CSIE20 0 1 3 wire serial I O mode oper...

Page 200: ...1 0 1 0 0 0 1 0 1 1 1 No parity Always add 0 parity at transmission Parity check is not performed at reception no parity error is generated Odd parity Even parity Receive operation control PS201 Parity bit specification PS200 CL20 0 1 SL20 Character length specification 7 bits 8 bits 1 bit 2 bits Transmit data stop bit length specification TXE20 RXE20 PS201 PS200 CL20 SL20 0 0 ASIM20 7 6 5 4 Symbo...

Page 201: ...No overrun error occurred An overrun error occurredNote 2 when the next receive operation was completed before data was read from reception buffer register 20 FE20 0 1 0 1 Framing error flag Overrun error flag OVE20 0 0 0 0 0 PE20 FE20 OVE20 ASIS20 7 6 5 4 Symbol Address After reset R W FF71H 00H R 3 2 1 0 Notes 1 Even when the stop bit length is set to 2 bits by setting bit 2 SL20 of asynchronous...

Page 202: ...annot be performed normally Be sure not to write to BRGC20 during a communication operation 2 Be sure not to select n 1 during operation at fX 2 5 MHz because the resulting baud rate exceeds the rated range 3 When the external input clock is selected set input mode by setting bit 0 of port mode register 2 PM2 to 1 Remarks 1 fX Main system clock oscillation frequency 2 n Values determined by the se...

Page 203: ...ion of baud rate transmit receive clock from external clock input to ASCK20 pin The transmit receive clock is generated by dividing the clock input from the ASCK20 pin The baud rate of a clock generated from the clock input to the ASCK20 pin is estimated by using the following expression Baud rate bps fASCK Frequency of clock input to ASCK20 pin Table 11 6 Relationship Between ASCK20 Pin Input Fre...

Page 204: ... Transmit Receive Data D0 D1 D2 D3 D4 D5 D6 D7 Parity bit Stop bit Start bit One data frame Start bits 1 bit Character bits 7 bits 8 bits Parity bits Even parity odd parity 0 parity no parity Stop bits 1 bit 2 bits When 7 bits are selected as the number of character bits only the lower 7 bits bits 0 to 6 are valid in transmission the most significant bit bit 7 is ignored and in reception the most ...

Page 205: ...ing parity bit is counted and if the number is odd a parity error occurs ii Odd parity At transmission Opposite to even parity the parity bit is determined so that the number of bits with a value of 1 in the transmit data including parity bit is odd The parity bit value should be as follows The number of bits with a value of 1 is an odd number in transmit data 0 The number of bits with a value of ...

Page 206: ...ransmission Completion Interrupt Timing a Stop bit length 1 STOP Parity D7 D6 D2 D1 D0 START TxD20 output INTST20 b Stop bit length 2 STOP Parity D7 D6 D2 D1 D0 START TxD20 output INTST20 Caution Do not rewrite asynchronous serial interface mode register 20 ASIM20 during a transmit operation If the ASIM20 register is rewritten during transmission subsequent transmission may not be able to be perfo...

Page 207: ...tected after the start bit reception of one frame of data ends When one frame of data has been received the receive data in the shift register is transferred to receive buffer register 20 RXB20 and a reception completion interrupt INTSR20 is generated If an error occurs the receive data in which the error occurred is still transferred to RXB20 and INTSR20 is generated If the RXE20 bit is reset 0 d...

Page 208: ...e 11 7 Receive Error Causes Receive Errors Receive Errors Value of ASIS20 Parity error Parity at transmission and reception do not match 04H Framing error Stop bit not detected 02H Overrun error Reception of next data is completed before data is read from receive buffer register 01H Figure 11 10 Receive Error Timing a Parity error occurrence STOP Parity D7 D6 D2 D1 D0 START RxD20 input INTSR20 b F...

Page 209: ...reception has stopped RXE20 0 read using either of the following methods a Read after setting RXE20 0 after waiting for one cycle or more of the source clock selected by BRGC20 b Read after bit 2 DIR20 of serial operation mode register 20 CSIM20 is set 1 Program example of a BRGC20 00H source clock fx 2 INTREX Reception completion interrupt routine NOP 2 clocks CLR1 RXE20 Reception stopped MOV A R...

Page 210: ...6 RXE20 of asynchronous serial interface mode register 20 ASIM20 is cleared during reception receive buffer register 20 RXB20 and the receive completion interrupt INTSR20 are as follows Parity RxD20 pin RXB20 INTSR20 3 1 2 When RXE20 is set to 0 at the time indicated by 1 RXB20 holds the previous data and INTSR20 is not generated When RXE20 is set to 0 at the time indicated by 2 RXB20 renews the d...

Page 211: ...l register 20 BRGC20 port mode register 2 PM2 and port 2 P2 a Serial operation mode register 20 CSIM20 CSIM20 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets CSIM20 to 00H CSIE20 0 1 3 wire serial I O mode operation control CSIE20 0 0 0 0 DIR20 CSCK20 0 CSIM20 Symbol Address After reset R W FF72H 00H R W 7 6 5 4 3 2 1 0 Operation disabled Operation enabled DIR20 0 1 F...

Page 212: ...ve operation enabled RXE20 0 1 0 1 0 0 0 1 0 1 1 1 No parity Always add 0 parity at transmission Parity check is not performed at reception no parity error occurs Odd parity Even parity Receive operation control PS201 Parity bit specification PS200 CL20 0 1 SL20 Transmit data character length specification 7 bits 8 bits 1 bit 2 bits Transmit data stop bit length specification TXE20 RXE20 PS201 PS2...

Page 213: ...ion When writing to BRGC20 during a communication operation the baud rate generator output is disrupted and communications cannot be performed normally Be sure not to write to BRGC20 during a communication operation Remarks 1 fX Main system clock oscillation frequency 2 n Values determined by the settings of TPS200 to TPS203 1 n 8 3 The parenthesized values apply to operation at fX 5 0 MHz If the ...

Page 214: ...lock SCK20 Then transmit data is held in the SO20 latch and output from the SO20 pin Also receive data input to the SI20 pin is latched in receive buffer register 20 RXB20 SIO20 on the rise of SCK20 At the end of an 8 bit transfer the operation of TXS20 SIO20 and RXS20 stops automatically and the interrupt request signal INTCSI20 is generated Figure 11 11 3 Wire Serial I O Mode Timing 1 2 i Master...

Page 215: ...is output 3 Transfer start Serial transfer is started by setting transfer data to transmit shift register 20 TXS20 SIO20 when the following two conditions are satisfied Bit 7 CSIE20 of serial operation mode register 20 CSIM20 1 Internal serial clock is stopped or SCK20 is high after 8 bit serial transfer Caution If CSIE20 is set to 1 after data is written to TXS20 SIO20 transfer does not start Ter...

Page 216: ...wire serial I O mode it is possible to select whether 8 bit data transfer will start with the MSB or LSB so any device can be connected regardless of whether that device is designed for MSB first or LSB first transfers 3 wire serial I O mode is useful for connecting peripheral I O circuits and display controllers with conventional clocked serial interfaces such as those found in the 75XL Series 78...

Page 217: ...ster 2 PM2 Port 2 P2 Figure 12 1 Block Diagram of Serial Interface 1A0 RE0 ARLD 0 TRF0 Internal bus Automatic data transmit receive control register 0 ADTC0 Serial operation mode register 1A0 CSIM1A0 ADTI 07 ADTI 04 ADTI 03 ADTI 02 ADTI 01 ADTI 00 5 bit counter Serial I O shift register 1A0 SIO1A0 Hand shake Serial clock counter Selector SO10 P24 PM24 P24 output latch DIR 10 DIR 10 Buffer RAM Auto...

Page 218: ... the serial input SI10 to SIO1A0 RESET input sets SIO1A0 to 00H Caution Do not write data to SIO1A0 while the automatic transmit receive function is activated 2 Automatic data transmit receive address pointer 0 ADTP0 This register stores value of transmit data byte 1 while the automatic transmit receive function is activated As data is transferred received it is automatically decremented ADTP0 is ...

Page 219: ...enable disable CSIM1A0 is set via a 1 bit or 8 bit memory manipulation instruction RESET input sets this register to 00H Caution Set the port mode register 2 PM2 in the 3 wire serial I O mode or 3 wire serial I O mode with automatic transmit receive function as follows In the case of serial clock output master transmission or master reception Set the SCK10 P23 pin to output mode PM23 0 and clear t...

Page 220: ...3 wire serial mode with automatic transmit receive function LSCK10 Chip enable control of SCK10 pin 0 SCK10 is used as port P23 when CSIE10 0 SCK10 is used for clock output when CSIE10 1 1 SCK10 is fixed to high level output when CSIE10 0 SCK10 is used for clock output when CSIE10 1 SCL101 SCL100 Selection of serial clock fSCK 0 0 External clock input to SCK10 pin 0 1 fX 22 1 25 MHz 1 0 fX 23 625 ...

Page 221: ...ic transmit receive function 0 Reception disabled Note 2 1 Reception enabled ARLD0 Selection of operation mode for automatic transmit receive function 0 One shot mode 1 Repeat mode TRF0 Status of automatic transmission reception function Note 3 0 Detection of termination of automatic transmission reception this bit is set to 0 upon suspension of automatic transmission reception or when ARLD0 0 1 A...

Page 222: ...1 ADTI00 FF7BH 00H R W ADTI07 Data transfer interval control 0 No control of interval by ADTI00 to ADTI04 Note 1 1 Control of interval by ADTI00 to ADTI04 ADTI04 ADTI03 ADTI02 ADTI01 ADTI00 Data transfer interval specification fX 5 0 MHz fSCK 1 25 MHz Note 2 n 0 0 0 0 0 0 0 0 0 0 1 1 60 µs 0 5 fSCK 1 0 0 0 1 0 2 40 µs 0 5 fSCK 2 0 0 0 1 1 3 20 µs 0 5 fSCK 3 0 0 1 0 0 4 00 µs 0 5 fSCK 4 0 0 1 0 1 4...

Page 223: ...1 1 0 1 1 0 18 4 µs 0 5 fSCK 22 1 0 1 1 1 19 2 µs 0 5 fSCK 23 1 1 0 0 0 20 0 µs 0 5 fSCK 24 1 1 0 0 1 20 8 µs 0 5 fSCK 25 1 1 0 1 0 21 6 µs 0 5 fSCK 26 1 1 0 1 1 22 4 µs 0 5 fSCK 27 1 1 1 0 0 23 2 µs 0 5 fSCK 28 1 1 1 0 1 24 0 µs 0 5 fSCK 29 1 1 1 1 0 24 8 µs 0 5 fSCK 30 1 1 1 1 1 25 6 µs 0 5 fSCK 31 Notes 1 The interval time depends only on the CPU processing 2 The data transfer interval time is ...

Page 224: ...ting Operation stop mode is set by serial operation mode register 1A0 CSIM1A0 a Serial operation mode register 1A0 CSIM1A0 CSIM1A0 is set with a 1 bit or 8 bit memory manipulation instruction RESET input clears CSIM1A0 to 00H Symbol 7 6 5 4 3 2 1 0 Address After reset R W CSIM1A0 CSIE10 DIR10 ATE0 LSCK10 0 0 SCL101 SCL100 FF78H 00H R W Specification of operation enable disable CSIE10 Shift registe...

Page 225: ...2 and port 2 P2 a Serial operation mode register 1A0 CSIM1A0 CSIM1A0 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets CSIM1A0 to 00H Caution Set the port mode register 2 PM2 in the 3 wire serial I O mode as follows In the case of serial clock output master transmission or master reception Set the SCK10 P23 pin to output mode PM23 0 and clear the output latch of P23 to ...

Page 226: ...tomatic transmit receive function LSCK10 Chip enable control of SCK10 pin 0 SCK10 is used as port P23 when CSIE10 0 SCK10 is used for clock output when CSIE10 1 1 SCK10 is fixed to high level output when CSIE10 0 SCK10 is used for clock output when CSIE10 1 SCL101 SCL100 Selection of serial clock 0 0 External clock input to SCK10 pin 0 1 fX 22 1 25 MHz 1 0 fX 23 625 kHz 1 1 fX 24 313 kHz Note When...

Page 227: ...serial clock SCK10 Then transmit data is held in the SO10 latch and output from the SO10 pin Also receive data input to the SI10 pin is latched in the SIO1A0 on the rise of SCK10 At the end of an 8 bit transfer the operation of SIO1A0 stops automatically and the interrupt request signal INTCSI10 is generated Figure 12 5 3 Wire Serial I O Mode Timing 1 2 i Master operation timing 1 2 3 4 5 6 7 8 DO...

Page 228: ...4V1UD Figure 12 5 3 Wire Serial I O Mode Timing 2 2 ii Slave operation timing 1 2 3 4 5 6 7 8 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 SCK10 SI10 Note SO10 SIO1A0 write INTCSI10 Note The value of the last bit previously output is output ...

Page 229: ... register 1A0 SIO1A0 Read write gate SO10 SCK10 D Q SO1 latch Start bit switching is realized by switching the bit order for data write to SIO1A0 The SIO1A0 shift order remains unchanged Thus switching between MSB first and LSB first must be performed before writing data to the shift register 4 Transfer start Serial transfer is started by setting transfer data to serial I O shift register 1A0 SIO1...

Page 230: ...ceive interval specification register 0 ADTI0 port mode register 2 PM2 and port 2 P2 a Serial operation mode register 1A0 CSIM1A0 CSIM1A0 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets CSIM1A0 to 00H Caution Set port mode register 2 PM2 in the 3 wire serial I O mode with automatic transmit receive function as follows In the case of serial clock output master transmis...

Page 231: ...tomatic transmit receive function LSCK10 Chip enable control of SCK10 pin 0 SCK10 is used as port P23 when CSIE10 0 SCK10 is used for clock output when CSIE10 1 1 SCK10 is fixed to high level output when CSIE10 0 SCK10 is used for clock output when CSIE10 1 SCL101 SCL100 Selection of serial clock 0 0 External clock input to SCK10 pin 0 1 fX 22 1 25 MHz 1 0 fX 23 625 kHz 1 1 fX 24 313 kHz Note When...

Page 232: ...tion mode for automatic transmit receive function 0 One shot mode 1 Repeat mode TRF0 Status of automatic transmit receive function Note 3 0 Detection of termination of automatic transmission reception this bit is set to 0 upon suspension of automatic transmission reception or when ARLD0 0 1 Automatic transmission reception in progress this bit is set to 1 when data is written to SIO1A0 Notes 1 Bit...

Page 233: ... to ADTI04 Note 1 1 Control of interval by ADTI00 to ADTI04 ADTI04 ADTI03 ADTI02 ADTI01 ADTI00 Data transfer interval specification fX 5 0 MHz fSCK 1 25 MHz Note 2 n 0 0 0 0 0 0 0 0 0 0 1 1 60 µs 0 5 fSCK 1 0 0 0 1 0 2 40 µs 0 5 fSCK 2 0 0 0 1 1 3 20 µs 0 5 fSCK 3 0 0 1 0 0 4 00 µs 0 5 fSCK 4 0 0 1 0 1 4 80 µs 0 5 fSCK 5 0 0 1 1 0 5 60 µs 0 5 fSCK 6 0 0 1 1 1 6 40 µs 0 5 fSCK 7 0 1 0 0 0 7 20 µs 0...

Page 234: ... µs 0 5 fSCK 23 1 1 0 0 0 20 0 µs 0 5 fSCK 24 1 1 0 0 1 20 8 µs 0 5 fSCK 25 1 1 0 1 0 21 6 µs 0 5 fSCK 26 1 1 0 1 1 22 4 µs 0 5 fSCK 27 1 1 1 0 0 23 2 µs 0 5 fSCK 28 1 1 1 0 1 24 0 µs 0 5 fSCK 29 1 1 1 1 0 24 8 µs 0 5 fSCK 30 1 1 1 1 1 25 6 µs 0 5 fSCK 31 Notes 1 The interval time depends only on the CPU processing 2 The data transfer interval time is found from the following expressions n Value s...

Page 235: ...ic data transmit receive interval specification register 0 ADTI0 4 Write any value to serial I O shift register 1A0 SIO1A0 transfer start trigger Caution Writing any value to SIO1A0 orders the start of automatic transmission reception operation the written value has no meaning The following operations are automatically carried out when a and b are carried out After the buffer RAM data specified by...

Page 236: ...mit receive mode operation timing and Figure 12 8 shows the operation flowchart Figure 12 9 shows buffer RAM operation at 6 byte transmission Figure 12 7 Basic Transmit Receive Mode Operation Timing SCK10 SO10 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 CSIIF10 TRF0 SI10 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Interval Cautions 1 Because in the basic transmit receive mode the automatic...

Page 237: ... receive control register 0 ADTC0 Start Write transmit data in buffer RAM Set ADTP0 to the value pointer value obtained by subtracting 1 from the number of transmit data bytes Set the transmission reception operation interval time in ADTI0 Write any data to SIO1A0 Start trigger Write transmit data from buffer RAM to SIO1A0 Transmission reception operation Write receive data from SIO1A0 to buffer R...

Page 238: ...rom the buffer RAM to SIO1A0 ii 4th byte transmit receive point refer to Figure 12 9 b Transmission reception of the third byte is completed and transmit data 4 T4 is transferred from the buffer RAM to SIO1A0 When transmission of the fourth byte is completed receive data 4 R4 is transferred from SIO1A0 to the buffer RAM and ADTP0 is decremented iii Completion of transmission reception refer to Fig...

Page 239: ...mission reception Receive data 1 R1 Receive data 2 R2 Receive data 3 R3 Transmit data 4 T4 Transmit data 5 T5 Transmit data 6 T6 FFAFH FFA5H FFA0H Receive data 4 R4 SIO1A0 0 CSIIF10 2 ADTP0 _1 c Completion of transmission reception Receive data 1 R1 Receive data 2 R2 Receive data 3 R3 Receive data 4 R4 Receive data 5 R5 Receive data 6 R6 FFAFH FFA5H FFA0H SIO1A0 1 CSIIF10 0 ADTP0 ...

Page 240: ...Figure 12 10 shows the basic transmit mode operation timing and Figure 12 11 shows the operation flowchart Figure 12 12 shows buffer RAM operation when repeatedly transmitting 6 bytes Figure 12 10 Basic Transmit Mode Operation Timing SCK10 SO10 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 CSIIF10 TRF0 Interval Cautions 1 Because in the basic transmit mode the automatic transmit receive function...

Page 241: ... automatic data transmit receive control register 0 ADTC0 Start Write transmit data in buffer RAM Set ADTP0 to the value pointer value obtained by subtracting 1 from the number of transmit data bytes Set the transmission reception operation interval time in ADTI0 Write any data to SIO1A0 Start trigger Write transmit data from buffer RAM to SIO1A0 Transmission operation Pointer value 0 No TRF0 0 No...

Page 242: ...is transferred from the buffer RAM to SIO1A0 ii 4th byte transmission point refer to Figure 12 12 b Transmission of the third byte is completed and transmit data 4 T4 is transferred from the buffer RAM to SIO1A0 When transmission of the fourth byte is completed ADTP0 is decremented iii Completion of transmission reception refer to Figure 12 12 c When transmission of the sixth byte is completed the...

Page 243: ...ssion point Transmit data 1 T1 Transmit data 2 T2 Transmit data 3 T3 Transmit data 4 T4 Transmit data 5 T5 Transmit data 6 T6 FFAFH FFA5H FFA0H SIO1A0 0 CSIIF10 5 ADTP0 _1 c Completion of transmission reception Transmit data 1 T1 Transmit data 2 T2 Transmit data 3 T3 Transmit data 4 T4 Transmit data 5 T5 Transmit data 6 T6 FFAFH FFA5H FFA0H SIO1A0 1 CSIIF10 0 ADTP0 ...

Page 244: ...P0 again and the buffer RAM contents are transmitted again When a reception operation is not performed the P25 SI10 pin can be used as a normal I O port The repeat transmit mode operation timing is shown in Figure 12 13 and the operation flowchart in Figure 12 14 Figure 12 13 Repeat Transmit Mode Operation Timing Caution Because in the repeat transmit mode a read is performed on the buffer RAM aft...

Page 245: ...bytes Set the transmission reception operation interval time in ADTI0 Write any data to SIO1A0 Start trigger Write transmit data from buffer RAM to SIO1A0 Transmission operation Pointer value 0 No Yes Decrement pointer value Software execution Hardware execution Reset ADTP0 Remark ADTP0 Automatic data transmit receive address pointer 0 ADTI0 Automatic data transmit receive interval specification r...

Page 246: ...uffer RAM to SIO1A0 ii Upon completion of transmission of 6 bytes refer to Figure 12 15 b When transmission of the sixth byte is completed the interrupt request flag CSIIF10 is not set The previous pointer value is assigned to the ADTP0 iii 7th byte transmission point refer to Figure 12 15 c Transmit data 1 T1 is transferred from the buffer RAM to SIO1A0 again When transmission of the first byte i...

Page 247: ... transmission of 6 bytes Transmit data 1 T1 Transmit data 2 T2 Transmit data 3 T3 Transmit data 4 T4 Transmit data 5 T5 Transmit data 6 T6 FFAFH FFA5H FFA0H SIO1A0 0 CSIIF10 0 ADTP0 d 7th byte transmission point Transmit data 1 T1 Transmit data 2 T2 Transmit data 3 T3 Transmit data 4 T4 Transmit data 5 T5 Transmit data 6 T6 FFAFH FFA5H FFA0H SIO1A0 0 CSIIF10 5 ADTP0 _1 ...

Page 248: ... P24 SO10 P25 SI10 are set to the port mode During restart of transmission reception the remaining data can be transferred by setting CSIE10 to 1 and writing any data to serial I O shift register 1A0 SIO1A0 Cautions 1 If the HALT instruction is executed during automatic transmission reception transfer is suspended and the HALT mode is set even if 8 bit data is being transferred 2 When suspending a...

Page 249: ...endent on ADTI0 is selected by setting bit 7 ADTI07 of ADTI0 If ADTI07 is reset to 0 the interval time is 2 fSCK If ADTI07 is set to 1 whichever is greater of the interval time determined by the set contents of ADTI0 or the interval time 2 fSCK determined by the CPU processing is selected Figure 12 17 shows the interval time of automatic transmission reception Remark fSCK Serial clock frequency Fi...

Page 250: ...ximum number of displayable pixels is shown in Table 13 1 below Table 13 1 Maximum Number of Display Pixels Bias Method Time Division Common Signals Used Maximum Number of Segments Maximum Number of Display Pixels 3 COM0 to COM2 84 28 segments 3 commons Note 1 1 3 4 COM0 to COM3 28 112 28 segments 4 commons Note 2 Notes 1 The LCD panel of the figure consists of 9 rows with 3 segments per row 2 The...

Page 251: ...ote FA14H 0 0 0 0 S20 Note FA13H 0 0 0 0 S19 Note FA12H 0 0 0 0 S18 Note FA11H 0 0 0 0 S17 Note FA10H 0 0 0 0 S16 Note FA0FH 0 0 0 0 S15 FA0EH 0 0 0 0 S14 FA0DH 0 0 0 0 S13 FA0CH 0 0 0 0 S12 FA0BH 0 0 0 0 S11 FA0AH 0 0 0 0 S10 FA09H 0 0 0 0 S9 FA08H 0 0 0 0 S8 FA07H 0 0 0 0 S7 FA06H 0 0 0 0 S6 FA05H 0 0 0 0 S5 FA04H 0 0 0 0 S4 FA03H 0 0 0 0 S3 FA02H 0 0 0 0 S2 FA01H 0 0 0 0 S1 FA00H 0 0 0 0 S0 Com...

Page 252: ...N0 3 2 1 0 3 2 1 0 6 5 7 4 FA10H LCDON0 S16 LCDM00 LCD clock control register 0 LCDC0 LCD display mode register 0 LCDM0 LCD clock selector Clock generator for boosting Selector Prescaler Booster circuit Segment voltage controller Common voltage controller Common driver Segment driver Segment driver Segment driver Segment driver Selector Selector Selector Selector Selected by mask option or port fu...

Page 253: ...5331EJ4V1UD 253 13 3 Registers Controlling LCD Controller Driver The LCD controller driver is controlled by the following three registers LCD display mode register 0 LCDM0 LCD clock control register 0 LCDC0 LCD voltage boost control register 0 LCDVA0 ...

Page 254: ...ground level to segment common pin Output select level to segment pin and LCD waveform to common pin Number of time slices Bias mode 1 3 1 3 Note When the LCD display panel is not used set VAON0 and LIPS0 to 0 to reduce power consumption Cautions 1 Bits 1 to 3 and 5 must be set to 0 2 When operating VAON0 follow the procedure described below A To stop voltage boosting after switching display statu...

Page 255: ... 28 fLCD 29 fXT 32 768 kHz fX 25 156 3 kHz fX 26 78 1 kHz fX 27 39 1 kHz Note Specify an LCD source clock fLCD frequency of at least 32 kHz Cautions 1 Bits 4 to 7 must be set to 0 2 Before changing the LCDC0 setting be sure to stop voltage boosting VAON0 0 3 Set the frame frequency to 128 Hz or lower Remarks 1 fX Main system clock oscillation frequency 2 fXT Subsystem clock oscillation frequency 3...

Page 256: ...Voltage Boost Control Register 0 0 GAIN LCDVA0 Symbol Address After reset R W FFB3H 00H R W 7 6 5 4 3 2 1 0 GAIN 0 1 1 5 V specification of the LCD panel used is 4 5 V 1 0 V specification of the LCD panel used is 3 V 0 0 0 0 0 0 Reference voltage VLC2 level selectionNote Note Select the settings according to the specifications of the LCD panel that is used Caution Before changing the LCDVA0 settin...

Page 257: ... the deselect potential 7 Start output corresponding to each data memory by setting LCDON0 bit 7 of LCDM0 LCDON0 1 13 5 LCD Display Data Memory The LCD display data memory is mapped at addresses FA00H to FA1BH Data in the LCD display data memory can be displayed on the LCD panel using the LCD controller driver Figure 13 6 shows the relationship between the contents of the LCD display data memory a...

Page 258: ... Bits 0 1 2 and 3 of each byte are read in synchronization with COM0 COM1 COM2 and COM3 respectively If the contents of each bit are 1 that bit is converted to the select voltage and if 0 it is converted to the deselect voltage The conversion results are output to the segment pins Check with the information given above what combination of the front surface electrodes corresponding to the segment s...

Page 259: ...ice mode TF 3 T VLC0 VSS VLCD VLC1 VLC2 TF 4 T COMn Four time slice mode VLC0 VLCD VLC1 VLC2 VSS T One LCD clock period TF Frame frequency Figure 13 8 Voltages and Phases of Common and Segment Signals Select Deselect Common signal Segment signal VLC0 VSS VLCD VLC0 VSS VLCD T T VLC2 VLC2 VLC1 VLC1 T One LCD clock period ...

Page 260: ...ct voltage to the S9 to S11 pins according to Table 13 5 at the timing of the common signals COM0 to COM2 see Figure 13 9 for the relationship between the segment signals and LCD segments Table 13 5 Select and Deselect Voltages COM0 to COM2 Segment S9 S10 S11 Common COM0 Deselect Select Select COM1 Select Select Select COM2 Select Select According to Table 13 5 it is determined that the display da...

Page 261: ...t 3 Bit 2 Bit 1 Bit 0 Timing strobe Data memory address LCD panel FA00H 1 2 3 4 5 6 7 8 9 A B C D E F FA10H 1 2 3 4 5 6 7 8 9 A S 0 S 1 S 2 S 3 S 4 S 5 S 6 S 7 S 8 S 9 S 10 S 11 S 12 S 13 S 14 S 15 S 16 S 17 S 18 S 19 S 20 S 21 S 22 S 23 S 24 S 25 S 26 COM 3 COM 2 COM 1 COM 0 Open 0 1 0 0 0 1 0 1 0 x Can be used to store any data because there is no corresponding segment in the LCD panel Can alway...

Page 262: ... 13 11 Three Time Slice LCD Drive Waveform Examples 1 3 Bias Method VLC0 VLC2 COM0 VLCD 0 COM0 S9 VLCD VLC1 1 3VLCD 1 3VLCD VSS VLC0 VLC2 COM1 VLC1 VSS VLC0 VLC2 COM2 VLC1 VSS VLC0 VLC2 S9 VLC1 VSS VLCD 0 COM1 S9 VLCD 1 3VLCD 1 3VLCD VLCD 0 COM2 S9 VLCD 1 3VLCD 1 3VLCD TF ...

Page 263: ...ge to the S16 and S17 pins according to Table 13 6 at the timing of the common signals COM0 to COM3 see Figure 13 12 for the relationship between the segment signals and LCD segments Table 13 6 Select and Deselect Voltages COM0 to COM3 Segment S16 S17 Common COM0 Select Select COM1 Deselect Select COM2 Select Select COM3 Select Select According to Table 13 7 it is determined that the display data ...

Page 264: ... 1 1 0 1 1 0 0 1 0 1 0 1 1 1 1 1 1 1 1 0 1 0 0 1 1 1 1 1 0 1 0 1 1 1 1 1 1 1 0 0 0 1 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 0 1 1 0 Bit 3 Bit 2 Bit 1 Bit 0 Timing strobe Data memory address LCD panel FA00H 1 2 3 4 5 6 7 8 9 A B C D E F FA10H 1 2 3 4 5 6 7 8 9 A B S 0 S 1 S 2 S 3 S 4 S 5 S 6 S 7 S 8 S 9 S 10 S 11 S 12 S 13 S 14 S 15 S 16 S 17 S 18 S 19 S 20 S 21 S 22 S 23 S 24 S 25 S 26 S 27 COM 3...

Page 265: ...CD Drive Waveform Examples 1 3 Bias Method TF VLC0 VLC2 COM0 VLCD 0 COM0 S16 VLCD VLC1 1 3VLCD 1 3VLCD VSS VLC0 VLC2 COM1 VLC1 VSS VLC0 VLC2 COM2 VLC1 VSS VLC0 VLC2 COM3 VLC1 VSS VLCD 0 COM1 S16 VLCD 1 3VLCD 1 3VLCD VLC0 VLC2 S16 VLC1 VSS Remark The waveforms of COM2 S16 and COM3 S16 are omitted ...

Page 266: ...apacitor recommended value 0 47 µF because it employs a capacitance division method to generate a supply voltage to drive the LCD Table 13 7 Output Voltages of VLC0 to VLC2 Pins LCDVA0 GAIN 0 GAIN 1 LCD drive power supply pin VLC0 4 5 V 3 0 V VLC1 3 0 V 2 0 V VLC2 LCD reference voltage 1 5 V 1 0 V Cautions 1 When using the LCD function do not leave the VLC0 VLC1 and VLC2 pins open Refer to Figure ...

Page 267: ...SET input makes this register undefined Caution Although this register is manipulated with a 16 bit memory manipulation instruction it can also be manipulated with an 8 bit memory manipulation instruction When using an 8 bit memory manipulation instruction however access the register by means of direct addressing 2 Multiplication data registers A and B MRA0 and MRB0 These are 8 bit multiplication ...

Page 268: ...er value 3 CPU clock Start Clear Counter output 16 bit adder 16 bit multiplication result storage register 0 Master MUL0 16 bit multiplication result storage register 0 Slave Multiplication data register A MRA0 Multiplication data register B MRB0 Internal bus 3 bit counter MULST0 Reset Multiplier control register 0 MULC0 ...

Page 269: ... as controls the multiplier MULC0 is set with a 1 bit or 8 bit memory manipulation instruction RESET input clears this register to 00H Figure 14 2 Format of Multiplier Control Register 0 MULST0 0 1 Multiplier operation start control bit 0 0 0 0 0 0 0 MULST0 MULC0 Symbol Address After reset R W FFD2H 00H R W 7 6 5 4 3 2 1 0 Stop operation after resetting counter to 0 Enable operation Operation stop...

Page 270: ...dded to the data of MUL0 at each CPU clock and the counter value is incremented by one 3 If MULST0 is cleared when the counter value is 111B the operation is stopped At this time MUL0 holds the data 4 While MULST0 is low the counter and slave are cleared Figure 14 3 Multiplier Operation Timing Example of AAH D3H AA D3 000B 00AA 0000 001B 010B 011B 100B 101B 110B 111B 000B 0154 0000 0000 0AA0 0000 ...

Page 271: ...ft register RMSR Remote controller receive data register RMDR Remote controller shift register receive counter register RMSCR Remote controller receive GPHS compare register RMGPHS Remote controller receive GPHL compare register RMGPHL Remote controller receive DLS compare register RMDLS Remote controller receive DLL compare register RMDLL Remote controller receive DH0S compare register RMDH0S Rem...

Page 272: ... INTGP INTRIN RMIN RMEN NCW End width select register RMER 1 Remote controller receive shift register RMSR This is an 8 bit register for reception of remote controller data Data is stored in bit 7 first Each time new data is stored the stored data is shifted to the lower bits Therefore the latest data is stored in bit 7 and the first data is stored in bit 0 RMSR is read with an 8 bit memory manipu...

Page 273: ...REND is generated Reading the values of this register allows confirmation of the number of bits even if the received data is in a format other than an integral multiple of 8 bits RMSCR is read with an 8 bit memory manipulation instruction RESET input sets RMSCR to 00H It is cleared to 00H under any of the following conditions Remote controller stops operation RMEN 0 Error is detected INTRERR is ge...

Page 274: ...egister is used to detect the low level of a remote controller data short side RMDLS is set with an 8 bit memory manipulation instruction RESET input sets RMDLS to 00H 7 Remote controller receive DLL compare register RMDLL This register is used to detect the low level of a remote controller data long side RMDLL is set with an 8 bit memory manipulation instruction RESET input sets RMDLL to 00H RIN ...

Page 275: ...high level of remote controller data 1 short side RMDH1S is set with an 8 bit memory manipulation instruction RESET input sets RMDH1S to 00H 11 Remote controller receive DH1L compare register RMDH1L This register is used to detect the high level of remote controller data 1 long side RMDH1L is set with an 8 bit memory manipulation instruction RESET input sets RMDH1L to 00H RIN Allowable range Count...

Page 276: ...TREND signal is output RMER is set with an 8 bit memory manipulation instruction RESET input sets RMER to 00H RIN Counter value RMER Data RMDLL INTREND Counter Caution For RMER and all the remote controller receive compare registers RMGPHS RMGPHL RMDLS RMDLL RMDH0S RMDH0L RMDH1S and RMDH1L disable remote controller reception bit 7 RMEN of the remote controller receive control register RMCN 0 first...

Page 277: ... 6 5 4 3 2 1 0 Address After reset R W RMCN RMEN NCW PRSEN RMIN 0 0 RMCK1 RMCK0 FF60H 00H R W RMEN Control of remote controller receive operation 0 Disable remote controller reception 1 Enable remote controller reception NCW Noise elimination width control signal 0 Eliminate noise less than 1 fPRS 1 Eliminate noise less than 2 fPRS PRSEN Internal clock division control signal 0 Clock not divided i...

Page 278: ... RMCK0 Selection of source clock fREM of remote controller counter 0 0 fX 2 6 625 kHz 0 1 fX 2 7 313 kHz 1 0 fX 2 8 156 kHz 1 1 fXT 32 768 kHz Cautions 1 Always set bits 2 and 3 to 0 2 To change the values of NCW PRSEN RMIN RMCK1 and RMCK0 disable remote controller reception RMEN 0 first Remarks 1 fX Oscillation frequency of main system clock 2 fXT Oscillation frequency of subsystem clock 3 The pa...

Page 279: ...a 0 Data 0 Data 0 15 4 2 Operation flow of type A reception mode Figure 15 5 shows the operation flow Cautions 1 When INTRERR is generated RMSR and RMSCR are automatically cleared immediately 2 When data has been set to all the bits of RMSR the following processing is automatically performed The value of RMSR is transferred to RMDR INTDFULL is generated RMSR is cleared RMDR must then be read befor...

Page 280: ...e high level width OK Data low level width OK Generate INTREND Read RMSCR Process received data Receive operation completed Yes Data high level width OK Set data to RMSR END No No Yes Yes Yes Generate INTRERR No Yes Clear RMSR and RMSCR Clear RMSR RMSCR and RMDR RMSR RMDR Generate INTDFULL Clear RMSR Read RMSR Clear RMSR and RMSCR Software processing User executes via program Hardware processing M...

Page 281: ...Within the range INTGP is generated Data measurement is started PMGPHL counter 3 Long Measuring guide pulse high level width is started from the next rising edge 2 Data low level width determination Relationship Between RMDLS RMDLL Counter Position of Waveform Corresponding Operation Counter RMDLS 1 Short Error interrupt INTRERR is generated Measuring guide pulse high level width is started RMDLS ...

Page 282: ...DH0L 2 Within the range Data 0 is received Measuring data low level width is started RMDH0L counter RMDH1S 3 Outside of the range Error interrupt INTRERR is generated Measuring the guide pulse high level width is started at the next rising edge RMDH1S counter RMDH1L 4 Within the range Data 1 is received Measuring the data low level width is started RMDH1L counter 5 Long Error interrupt INTRERR is ...

Page 283: ...r RMGPHL Remote controller receive DLS compare register RMDLS Remote controller receive DLL compare register RMDLL Remote controller receive DH0S compare register RMDH0S Remote controller receive DH0L compare register RMDH0L Remote controller receive DH1S compare register RMDH1S Remote controller receive DH1L compare register RMDH1L Remote controller receive end width select register RMER Use form...

Page 284: ...ation clock cycle after division control by PRSEN a Tolerance INT Round down the fractional portion of the value produced by the formula in the brackets n1 n2 Variables of waveform change caused by noiseNote1 TWE End width of RIN input Note2 Notes 1 Set the values of n1 and n2 as required to meet the user s system specification 2 This end width is counted after RMDLL The low level width actually r...

Page 285: ...e of RIN RMDLL counter and counter after RMDLL RMER at the rising edge of RIN Counter RMDH0S at the falling edge of RIN RMDH0L counter RMDH1S at the falling edge of RIN Register changes so that RMDH1L counter while RIN is at high level The INTRERR signal is not generated until the guide pulse is detected Once the INTRERR signal has been generated it will not be generated again until the next guide...

Page 286: ...TRERR is not generated Basic waveform Example 2 RMGPHL counter INTRERR is not generated Example 3 Counter RMDLS INTRERR is generated Example 4 RMDLL counter and counter RMER INTRERR is generated Example 5 RMDLL counter and RMER counter INTRERR is not generated INTREND is generated Example 6 Counter RMDH0S INTRERR is generated Example 7 RMDH0L counter RMDH1S INTRERR is generated Example 8 RMDH1L co...

Page 287: ...ed with the clock If NCW 0 the signal after sampling is performed twice is processed as a RIN input in the circuit If NCW 1 the signal after sampling is performed three times is processed as a RIN input in the circuit The following shows the flow of a noise elimination operation 1 Select whether or not the internal operation clock is divided by PRSEN PRSEN 0 Not divided fPRS fREM PRSEN 1 Divided f...

Page 288: ...k Internal RIN is a signal after synchronization and sampling are performed three times and is therefore later than the actual signal input from the outside to the RIN pin by 3 to 4 clocks Clock Clock RIN ideal RIN Synchronization samp2 samp3 Internal RIN Noise Delayed by 3 to 4 clocks samp1 H H L H L L L Since synchronized signal samp1 H samp1 is latched from this point and later Since synchroniz...

Page 289: ... Internal RIN is a signal after synchronization and sampling are performed three times and is therefore later than the actual signal input from the outside to the RIN pin by 6 to 8 clocks Clock divider RIN ideal RIN Synchronization samp2 samp3 Internal RIN Noise Delayed by 6 to 8 clocks samp1 Clock H H L H L L Since synchronized signal samp2 H is not satisfied samp2 is not latched Since synchroniz...

Page 290: ...nterrupt undergoes mask control If two or more interrupts with the same priority are simultaneously generated each interrupt has a predetermined priority as shown in Tables 16 1 and 16 2 A standby release signal is generated For the µPD789488 and 78F9488 5 external and 11 internal interrupt sources are incorporated as maskable interrupts For the µPD789489 and 78F9489 6 external and 16 internal int...

Page 291: ...of UART transmission for serial interface 20 0014H 8 INTWTI Reference time interval signal of watch timer WT 0016H 9 INTTM20 Match between TM20 and CR20 0018H 10 INTTM50 Match between TM50 and CR50 001AH 11 INTTM60 Match between TM60 and CR60 in 8 bit counter mode and between TM50 TM60 and CR50 CR60 in 16 bit timer mode 001CH 12 INTTM61 Match between TM61 and CR61 001EH 13 INTAD0 End of A D conver...

Page 292: ...l signal of watch timer WT 0016H 10 INTTM20 Match between TM20 and CR20 0018H 11 INTTM50 Match between TM50 and CR50 001AH 12 INTTM60 Match between TM60 and CR60 in 8 bit counter mode and between TM50 TM60 and CR50 CR60 in 16 bit timer mode 001CH 13 INTTM61 Match between TM61 and CR61 001EH 14 INTAD0 End of A D conversion 0020H 15 INTWT Watch timer WT overflow Internal 0022H B 16 INTKR00 Key retur...

Page 293: ...IE Internal bus Interrupt request Vector table address generator Standby release signal C External maskable interrupt MK IF IE Internal bus INTM0 INTM1 KRM00 KRM01 Interrupt request Edge detector Vector table address generator Standby release signal INTM0 External interrupt mode register 0 INTM1 External interrupt mode register 1 KRM00 Key return mode register 00 KRM01 Key return mode register 01 ...

Page 294: ...able 16 3 Flags Corresponding to Interrupt Request Signal Names Interrupt Request Signal Name Interrupt Request Flag Interrupt Mask Flag INTWDT INTP0 INTP1 INTP2 INTP3 INTRIN Note INTSR20 INTCSI20 INTCSI10 INTST20 INTWTI INTTM20 INTTM50 INTTM60 INTTM61 INTAD0 INTWT INTKR00 INTRERR Note INTGP Note INTREND Note INTDFULL Note INTKR01 Note WDTIF PIF0 PIF1 PIF2 PIF3 RINIF Note SRIF20 CSIIF10 STIF20 WTI...

Page 295: ...eset R W IF1 WTIF ADIF0 TMIF61 TMIF60 TMIF50 TMIF20 WTIIF STIF20 FFE1H 00H R W Symbol 7 6 5 4 3 2 1 0 Address After reset R W IF2 0 0 KRIF01 Not e DFULLIFNot e RENDIFNote GPIF Note RERRIFNote KRIF00 FFE2H 00H R W IF Interrupt request flag 0 No interrupt request signal generated 1 An interrupt request signal is generated and an interrupt request made Note µPD789489 and 78F9489 only Cautions 1 The W...

Page 296: ...50 TMMK20 WTIMK STMK20 FFE5H FFH R W Symbol 7 6 5 4 3 2 1 0 Address After reset R W MK2 1 1 KRMK01Note DFULLMKNot e RENDMKNot e GPMK Note RERRMKNot e KRMK00 FFE6H FFH R W MK Interrupt servicing control 0 Interrupt servicing enabled 1 Interrupt servicing disabled Note µPD789489 and 78F9489 only Cautions 1 When the watchdog timer is being used in watchdog timer mode 1 or 2 any attempt to read the WD...

Page 297: ...set R W INTM0 ES21 ES20 ES11 ES10 ES01 ES00 0 0 FFECH 00H R W Symbol 7 6 5 4 3 2 1 0 Address After reset R W INTM1 0 0 0 0 0 0 ES31 ES30 FFEDH 00H R W ESn1 ESn0 INTPn valid edge selection 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both rising and falling edges Remark n 0 1 2 and 3 Cautions 1 Always set bits 0 and 1 of INTM0 and 2 to 7 of INTM1 to 0 2 Before setting INTM0 and INTM1...

Page 298: ...can be read and written in 8 bit units and can be manipulated by using bit manipulation instructions and dedicated instructions EI and DI When a vectored interrupt is acknowledged the PSW is automatically saved to the stack and the IE flag is reset 0 RESET input sets the PSW to 02H Figure 16 5 Program Status Word Configuration IE Z 0 AC 0 0 1 CY PSW Symbol After reset 02H 7 6 5 4 3 2 1 0 Used in t...

Page 299: ...4 to 7 Cautions 1 Always set bits 1 to 3 to 0 2 Before setting KRM00 set 1 bit 0 KRMK00 of MK2 to disable interrupts To enable interrupts clear 0 KRMK00 after clearing 0 bit 0 KRIF00 of IF2 3 On chip pull up resistors are not automatically connected in input mode even when key return signal detection is specified Therefore when detecting the key return signal connect the pull up resistor of the co...

Page 300: ...not detected 1 Key return signal detected P6n falling edge detection Remark n 4 to 7 Cautions 1 Always set bits 1 to 3 to 0 2 Before setting KRM01 set bit 5 of MK2 KRMK01 1 to disable interrupts To enable interrupts clear KRMK01 after clearing bit 5 of IF2 KRIF01 0 3 If any of the pins specified for key return signal detection is low level the key return signal cannot be detected even if a falling...

Page 301: ...he stack in that order the IE flag is reset to 0 the contents of the vector table are loaded to the PC and then program execution branches Figure 16 10 shows the flow from non maskable interrupt request generation to acknowledgment Figure 16 11 shows the timing of non maskable interrupt acknowledgment and Figure 16 12 shows the acknowledgment operation when a number of non maskable interrupts are ...

Page 302: ...enerated Interrupt servicing starts WDTM3 0 non maskable interrupt is selected WDTM Watchdog timer mode register WDT Watchdog timer Figure 16 11 Timing of Non Maskable Interrupt Request Acknowledgment Instruction Instruction Saving PSW and PC and jump to interrupt servicing Interrupt servicing program CPU processing WDTIF Figure 16 12 Non Maskable Interrupt Request Acknowledgment Second interrupt ...

Page 303: ... 1 clock fCPU CPU clock When two or more maskable interrupt requests are generated at the same time they are acknowledged starting from the one assigned the highest priority by the priority specification flag A pending interrupt is acknowledged when the status in which it can be acknowledged is set Figure 16 13 shows the algorithm of interrupt request acknowledgment When a maskable interrupt reque...

Page 304: ...in Final Clock Under Execution Clock CPU NOP MOV A r Saving PSW and PC and jump to interrupt servicing Interrupt servicing program Interrupt 8 clocks If the interrupt request flag xxIFx is generated in the final clock of the instruction interrupt request acknowledgment processing will begin after execution of the next instruction is complete Figure 16 15 shows an example whereby an interrupt reque...

Page 305: ...st is acknowledged the EI instruction is issued and the interrupt request is enabled Example 2 Multiple interrupt servicing is not performed because interrupts are disabled INTyy EI Main servicing RETI INTyy servicing INTxx servicing IE 0 INTxx RETI INTyy is held pending IE 0 Because interrupt requests are disabled the EI instruction has not been issued in the INTxx interrupt servicing the interru...

Page 306: ... interrupt is generated when a certain type of instruction is being executed the interrupt request will not be acknowledged until the instruction is completed Such instructions interrupt request pending instructions are as follows Instructions that manipulate interrupt request flag registers IF0 to IF2 Instructions that manipulate interrupt mask flag registers MK0 to MK2 ...

Page 307: ...tops the entire system The power consumption of the CPU can be substantially reduced in this mode The data memory can be retained at a low voltage VDD 1 8 V Therefore this mode is useful for retaining the contents of the data memory at an extremely low current The STOP mode can be released by an interrupt request so that this mode can be used for intermittent operation However some time is require...

Page 308: ...ion Stabilization Time Selection Register OSTS2 0 0 1 0 0 0 0 0 OSTS2 OSTS1 OSTS0 OSTS R W FFFAH 04H R W 7 6 5 4 3 2 1 0 OSTS1 0 1 0 212 fX 215 fX 217 fX 819 s 6 55 ms 26 2 ms OSTS0 0 0 0 Setting prohibited Symbol Address After reset Oscillation stabilization time selection Other than above µ Caution The wait time after the STOP mode is released does not include the time from STOP mode release to ...

Page 309: ... timer Operable Operable Note 4 Operable Operable Note 5 Watchdog timer Operable Operation stopped Key return circuit Operable Serial interface 20 Operable Operable Note 6 Serial interface 1A0 Operable Operable Note 6 LCD controller driver Operable Note 7 Operable Notes 4 7 Operable Note 7 Operable Notes 5 7 A D converter Operation stopped Multiplier Operation stopped Remote controller receiver No...

Page 310: ...xecuted Figure 17 2 Releasing HALT Mode by Interrupt HALT instruction Standby release signal Wait Wait HALT mode Operation mode Operation mode Clock Oscillation Remarks 1 The broken lines indicate the case where the interrupt request that released the standby mode is acknowledged 2 The wait time is as follows When vectored interrupt servicing is performed 9 to 10 clocks When vectored interrupt ser...

Page 311: ...atus Clock Operation mode Oscillation stops Oscillation Oscillation Remark fX Main system clock oscillation frequency Table 17 2 Operation After Releasing HALT Mode Releasing Source MKxx IE Operation 0 0 Executes next address instruction 0 1 Executes interrupt servicing Maskable interrupt request 1 x Retains HALT mode Non maskable interrupt request x Executes interrupt servicing RESET input Reset ...

Page 312: ...d Ports output latches Status before STOP mode setting retained 16 bit timer 20 Operation stopped 8 bit timer 50 Operable Note 1 Operable Note 2 8 bit timer 60 Operable Note 3 8 bit timer 61 Operable Note 3 Watch timer Operable Note 4 Operation stopped Watchdog timer Operation stopped Key return circuit Operable Serial interface 20 Operable Note 5 Serial interface 1A0 Operable Note 5 LCD controlle...

Page 313: ... interrupt servicing is performed after the oscillation stabilization time has elapsed If interrupts are disabled the instruction at the next address is executed Figure 17 4 Releasing STOP Mode by Interrupt STOP instruction Standby release signal Wait set time by OSTS STOP mode Operation mode Oscillation stabilization wait status Clock Operation mode Oscillation stops Oscillation Oscillation Remar...

Page 314: ...nstruction RESET signal Wait 215 fX 6 55 ms STOP mode Operation mode Oscillation stabilization wait status Clock Operation mode Oscillation stops Oscillation Oscillation Reset period Remark fX Main system clock oscillation frequency Table 17 4 Operation After Releasing STOP Mode Releasing Source MKxx IE Operation 0 0 Executes next address instruction 0 1 Executes interrupt servicing Maskable inter...

Page 315: ...oscillation stabilization time just after reset release When a high level is input to the RESET pin the reset is released and program execution is started after the oscillation stabilization time 215 fX has elapsed The reset applied by the watchdog timer overflow is automatically released after reset and program execution is started after the oscillation stabilization time 215 fX has elapsed see F...

Page 316: ...erflow in Watchdog Timer X1 Overflow in watchdog timer Internal reset signal Port pin Hi Z During normal operation Reset period oscillation continues Normal operation reset processing Oscillation stabilization time wait Figure 18 4 Reset Timing by RESET Input in STOP Mode X1 RESET Internal reset signal Port pin Delay Delay Hi Z STOP instruction execution During normal operation Reset period oscill...

Page 317: ...1 00H Compare registers CR50 CR60 CRH60 CR61 CRH61 Undefined Mode control registers TMC50 TMC60 TMC61 00H 8 bit timer 50 60 61 Carrier generator output control register TCA60 00H Mode control register WTM 00H Watch timer Interrupt time selection register WTIM 00H Clock selection register WDCS 00H Watchdog timer Mode register WDTM 00H Serial operation mode register CSIM20 00H Asynchronous serial in...

Page 318: ... result register ADCRL0 0000H Display mode register LCDM0 00H Clock control register LCDC0 00H LCD controller driver Voltage boost control register LCDVA0 00H 16 bit result storage register MUL0 Undefined Data register MRA0 MRB0 Undefined Multiplier Control register MULC0 00H Control register RMCN 00H Data register RMDR 00H Shift register reception counter register RMSCR 00H Shift register RMSR 00...

Page 319: ... multiply subsystem clock by 4 Use enabled disabled by subclock select register SSCK Use enabled disabled by a mask option Pull up resistor of port 5 None Selectable by a mask option in 1 bit units Remote controller receiver Not provided Provided Not provided Provided Key return signal detection pins P00 KR0 to P07 KR7 P00 KR00 to P07 KR07 P60 ANI0 KR10 to P67 ANI7 KR17 P00 KR0 to P07 KR7 P00 KR00...

Page 320: ...controller is solder mounted on the target system Distinguishing software facilities low quantity varied model production Easy data adjustment when starting mass production 19 1 1 Programming environment The following shows the environment required for µPD78F9488 and 78F9489 flash memory programming When Flashpro III part no FL PR3 PG FP3 or Flashpro IV part no FL PR4 PG FP4 is used as a dedicated...

Page 321: ...S 3 UART UART ch 0 Async 4 800 to 76 800 bps Notes 2 4 5 MHz Note 5 4 91 or 5 MHz Note 2 1 0 RxD20 SI20 P22 TxD20 SO20 P21 8 Notes 1 Selection items for TYPE settings on the dedicated flash programmer Flashpro III part no FL PR3 PG FP3 Flashpro IV part no FL PR4 PG FP4 2 The possible setting range differs depending on the voltage For details refer to CHAPTER 22 ELECTRICAL SPECIFICATIONS µPD789488 ...

Page 322: ... SI CLKNotes 1 2 GND VPP VDD RESET RXD20 TXD20 X1 VSS Dedicated flash programmer PD78F9488 PD78F9489 µ µ Notes 1 When the system clock is supplied from the dedicated flash programmer connect the CLK pin with X1 pin and disconnect the on board resonator When using the clock of the on board resonator do not connect the CLK pin 2 When using UART with Flashpro III the clock of the resonator connected ...

Page 323: ... Serial I O with Handshake UART VPP1 Output Write voltage VPP VPP2 VDD I O VDD voltage generation voltage monitoring VDD Note Note Note GND Ground VSS CLK Output Clock output X1 RESET Output Reset signal RESET SI Input Receive signal SO20 TxD20 SO Output Transmit signal SI20 RxD20 SCK Output Transfer clock SCK20 HS Input Handshake signal P11 HS Note VDD voltage must be supplied before programming ...

Page 324: ...n resistor RVPP 10 kΩ to the VPP pin 2 Use the jumper on the board to switch the VPP pin input to either the programmer or directly to GND A VPP pin connection example is shown below Figure 19 4 VPP Pin Connection Example PD78F9488 PD78F9489 VPP Connection pin of dedicated flash programmer Pull down resistor RVPP µ µ Serial interface pin The following shows the pins used by the serial interface Se...

Page 325: ...peration of other device If the dedicated flash programmer output or input is connected to a serial interface pin input or output that is connected to another device input a signal is output to the device and this may cause an abnormal operation To prevent this abnormal operation isolate the connection with the other device or set so that the input signals to the other device are ignored Figure 19...

Page 326: ... other than those that communicate with flash programmer are in the same status as immediately after reset If the external device does not recognize initial statuses such as the output high impedance status therefore connect the external device to VDD or VSS via a resistor Resonator When using the on board clock connect X1 X2 XT1 and XT2 as required in the normal operation mode When using the cloc...

Page 327: ...gure 19 8 Wiring Example for Flash Writing Adapter with 3 Wire Serial I O GND VDD SI SO SCK CLKOUT RESET VPP RESERVE HS WRITER INTERFACE VDD 2 7 to 5 5 V GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 PD78F9488 P...

Page 328: ...shake PD78F9488 PD78F9489 GND VDD VDD2 LVDD SI SO SCK CLKOUT RESET VPP RESERVE HS WRITER INTERFACE VDD 2 7 5 5 V GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 µ µ ...

Page 329: ...I SO SCK CLKOUT RESET VPP RESERVE HS WRITER INTERFACE VDD 2 7 to 5 5 V GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 VDD2 LVDD PD78F9488 PD78F9489 µ µ ...

Page 330: ...the HALT mode with the subclock multiplied by 4 as the CPU clock Be sure to insert the following number of NOP instructions immediately after the HALT instruction Operating Temperature Number of NOP Instructions TA 40 to 45 C 2 TA 40 to 80 C 3 TA 40 to 85 C 4 Save the value of the A register to the internal high speed RAM area before the HALT instruction is executed because the value of the A regi...

Page 331: ... bit units 1 S 20 m 2 P8m m 0 to 7 Subsystem clock 4 multiplication circuit The use of a circuit to multiply the subsystem clock 32 768 kHz by 4 131 kHz is selected 1 4 multiplication circuit is used 2 4 multiplication circuit is not used Pull up resistor The connection of on chip pull up resistors for port 5 I O port can be switched in 1 bit units 1 Pull up resistor is connected 2 Pull up resisto...

Page 332: ...direct address specification In the case of immediate data describe an appropriate numeric value or a label When using a label be sure to describe the and symbols For operand register identifiers r and rp either functional names X A C etc or absolute names names in parenthesis in the table below R0 R1 R2 etc can be used for description Table 21 1 Operand Identifiers and Description Methods Identif...

Page 333: ... PSW Program status word CY Carry flag AC Auxiliary carry flag Z Zero flag IE Interrupt request enable flag Memory contents indicated by address or register contents in parenthesis XH XL Higher 8 bits and lower 8 bits of 16 bit register Logical product AND Logical sum OR V Exclusive logical sum exclusive OR Inverted data addr16 16 bit immediate data or label jdisp8 Signed 8 bit data displacement v...

Page 334: ...r A 2 4 sfr A A addr16 3 8 A addr16 addr16 A 3 8 addr16 A PSW byte 3 6 PSW byte x x x A PSW 2 4 A PSW PSW A 2 4 PSW A x x x A DE 1 6 A DE DE A 1 6 DE A A HL 1 6 A HL HL A 1 6 HL A A HL byte 2 6 A HL byte HL byte A 2 6 HL byte A XCH A X 1 4 A X A r Note 2 2 6 A r A saddr 2 6 A saddr A sfr 2 6 A sfr A DE 1 8 A DE A HL 1 8 A HL A HL byte 2 8 A HL byte Notes 1 Except r A 2 Except r A X Remark One inst...

Page 335: ... HL byte 2 6 A CY A HL byte x x x ADDC A byte 2 4 A CY A byte CY x x x saddr byte 3 6 saddr CY saddr byte CY x x x A r 2 4 A CY A r CY x x x A saddr 2 4 A CY A saddr CY x x x A addr16 3 8 A CY A addr16 CY x x x A HL 1 6 A CY A HL CY x x x A HL byte 2 6 A CY A HL byte CY x x x SUB A byte 2 4 A CY A byte x x x saddr byte 3 6 saddr CY saddr byte x x x A r 2 4 A CY A r x x x A saddr 2 4 A CY A saddr x...

Page 336: ...ddr saddr byte x A r 2 4 A A r x A saddr 2 4 A A saddr x A addr16 3 8 A A addr16 x A HL 1 6 A A HL x A HL byte 2 6 A A HL byte x OR A byte 2 4 A A byte x saddr byte 3 6 saddr saddr byte x A r 2 4 A A r x A saddr 2 4 A A saddr x A addr16 3 8 A A addr16 x A HL 1 6 A A HL x A HL byte 2 6 A A HL byte x XOR A byte 2 4 A A V byte x saddr byte 3 6 saddr saddr V byte x A r 2 4 A A V r x A saddr 2 4 A A V ...

Page 337: ...x x DEC r 2 4 r r 1 x x saddr 2 4 saddr saddr 1 x x INCW rp 1 4 rp rp 1 DECW rp 1 4 rp rp 1 ROR A 1 1 2 CY A7 A0 Am 1 Am 1 x ROL A 1 1 2 CY A0 A7 Am 1 Am 1 x RORC A 1 1 2 CY A0 A7 CY Am 1 Am 1 x ROLC A 1 1 2 CY A7 A0 CY Am 1 Am 1 x SET1 saddr bit 3 6 saddr bit 1 sfr bit 3 6 sfr bit 1 A bit 2 4 A bit 1 PSW bit 3 6 PSW bit 1 x x x HL bit 2 10 HL bit 1 CLR1 saddr bit 3 6 saddr bit 0 sfr bit 3 6 sfr b...

Page 338: ...dr16 2 6 PC PC 2 jdisp8 if Z 1 BNZ saddr16 2 6 PC PC 2 jdisp8 if Z 0 BT saddr bit addr16 4 10 PC PC 4 jdisp8 if saddr bit 1 sfr bit addr16 4 10 PC PC 4 jdisp8 if sfr bit 1 A bit addr16 3 8 PC PC 3 jdisp8 if A bit 1 PSW bit addr16 4 10 PC PC 4 jdisp8 if PSW bit 1 BF saddr bit addr16 4 10 PC PC 4 jdisp8 if saddr bit 0 sfr bit addr16 4 10 PC PC 4 jdisp8 if sfr bit 0 A bit addr16 3 8 PC PC 3 jdisp8 if...

Page 339: ...te addr1 6 1 None A ADD ADDC SUB SUBC AND OR XOR CMP MOVNote XCHNote ADD ADDC SUB SUBC AND OR XOR CMP MOV XCH MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV ADD ADDC SUB SUBC AND OR XOR CMP MOV MOV XCH MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP ROR ROL RORC ROLC r MOV MOV INC DEC B C DBNZ sfr MOV MOV saddr MOV ADD ADDC SUB SUBC AND OR XOR CMP MOV DBNZ INC DEC a...

Page 340: ...ote saddrp SP None AX ADDW SUBW CMPW MOVW XCHW MOVW MOVW rp MOVW MOVW Note INCW DECW PUSH POP saddrp MOVW sp MOVW Note Only when rp BC DE or HL 3 Bit manipulation instructions SET1 CLR1 NOT1 BT BF 2nd Operand 1st Operand addr16 None A bit BT BF SET1 CLR1 sfr bit BT BF SET1 CLR1 saddr bit BT BF SET1 CLR1 PSW bit BT BF SET1 CLR1 HL bit SET1 CLR1 CY SET1 CLR1 NOT1 ...

Page 341: ...D 341 4 Call instructions branch instructions CALL CALLT BR BC BNC BZ BNZ DBNZ 2nd Operand 1st Operand AX addr16 addr5 addr16 Basic Instructions BR CALL BR CALLT BR BC BNC BZ BNZ Compound Instructions DBNZ 5 Other instructions RET RETI NOP EI DI HALT STOP ...

Page 342: ...er pin 10 mA Output current high IOH Total for all pins 30 mA Per pin 30 mA Output current low IOL Total for all pins 160 mA Operating ambient temperature TA Normal operation 40 to 85 C Flash memory programming 10 to 40 C Storage temperature Tstg µPD789488 789489 65 to 150 C µPD78F9488 78F9489 40 to 125 C Notes 1 Make sure that the following conditions of the VPP voltage application timing are sat...

Page 343: ... momentarily for any parameter That is the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded Remark Unless otherwise specified the characteristics of alternate function pins are the same as those of port pins ...

Page 344: ...cteristics for instruction execution time 2 Time required to stabilize oscillation after reset or STOP mode release Cautions 1 When using the main system clock oscillator wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance Keep the wiring length as short as possible Do not cross the wiring with the other signal lines Do n...

Page 345: ... wire as follows in the area enclosed by the broken lines in the above figure to avoid an adverse effect from wiring capacitance Keep the wiring length as short as possible Do not cross the wiring with the other signal lines Do not route the wiring near a signal line through which a high fluctuating current flows Always make the ground point of the oscillator capacitor the same potential as VSS Do...

Page 346: ...ut voltage high VIH4 X1 X2 XT1 XT2 VDD 1 8 to 5 5 V VDD 0 1 VDD V VDD 2 7 to 5 5 V 0 0 3VDD V VIL1 P10 P11 P60 to P67 VDD 1 8 to 5 5 V 0 0 1VDD V VDD 2 7 to 5 5 V 0 0 3VDD V VIL2 P50 to P53 VDD 1 8 to 5 5 V 0 0 1VDD V VDD 2 7 to 5 5 V 0 0 2VDD V VIL3 RESET P00 to P07 P20 to P25 P30 to P34 P70 to P73 Note P80 to P87 Note VDD 1 8 to 5 5 V 0 0 1VDD V VDD 4 5 to 5 5 V 0 0 4 V Input voltage low VIL4 X1...

Page 347: ...pen drain 3 Note 2 µA Output leakage current high ILOH VO VDD 3 µA Output leakage current low ILOL VO 0 V 3 µA Software pull up resistor R1 VI 0 V P00 to P07 P10 P11 P20 to P25 P30 to P34 50 100 200 kΩ Mask option pull up resistor Note 3 R2 VI 0 V P50 to P53 10 30 60 kΩ Notes 1 Only when selected by a mask option or port function register 2 If there is no on chip pull up resistor for P50 to P53 sp...

Page 348: ...D operating Note 7 VDD 2 0 V 10 7 20 µA VDD 5 0 V 10 25 60 µA LCD not operating Note 4 VDD 3 0 V 10 8 28 µA VDD 5 0 V 10 28 69 µA IDD4 32 768 kHz crystal oscillation 4 multiplication HALT mode Note 5 C3 C4 22 pF R1 220kΩ LCD operating Note 7 VDD 3 0 V 10 10 36 µA VDD 5 0 V 10 0 1 10 µA VDD 3 0 V 10 0 05 5 µA IDD5 STOP mode Note 6 VDD 2 0 V 10 0 05 3 µA VDD 5 0 V 10 Note 2 3 5 2 mA VDD 3 0 V 10 Not...

Page 349: ...CD operating Note 7 VDD 2 0 V 10 7 25 µA VDD 5 0 V 10 25 65 µA LCD not operating Note 4 VDD 3 0 V 10 8 29 µA VDD 5 0 V 10 28 70 µA IDD4 32 768 kHz crystal oscillation 4 multiplication HALT mode Note 5 C3 C4 22 pF R1 220kΩ LCD operating Note 7 VDD 3 0 V 10 10 34 µA VDD 5 0 V 10 0 1 10 µA VDD 3 0 V 10 0 05 5 µA IDD5 STOP mode Note 6 VDD 2 0 V 10 0 05 3 µA VDD 5 0 V 10 Note 2 6 5 10 2 mA VDD 3 0 V 10...

Page 350: ...operating Note 7 VDD 2 0 V 10 7 27 µA VDD 5 0 V 10 25 70 µA LCD not operating Note 4 VDD 3 0 V 10 8 32 µA VDD 5 0 V 10 28 79 µA IDD4 32 768 kHz crystal oscillation 4 multiplication HALT mode Note 5 C3 C4 22 pF R1 220kΩ LCD operating Note 7 VDD 3 0 V 10 10 40 µA VDD 5 0 V 10 0 1 10 µA VDD 3 0 V 10 0 05 5 µA IDD5 STOP mode Note 6 VDD 2 0 V 10 0 05 3 µA VDD 5 0 V 10 Note 2 5 0 6 7 mA VDD 3 0 V 10 Not...

Page 351: ...D operating Note 7 VDD 2 0 V 10 7 27 µA VDD 5 0 V 10 25 70 µA LCD not operating Note 4 VDD 3 0 V 10 8 32 µA VDD 5 0 V 10 28 79 µA IDD4 32 768 kHz crystal oscillation 4 multiplication HALT mode Note 5 C3 C4 22 pF R1 220kΩ LCD operating Note 7 VDD 3 0 V 10 10 40 µA VDD 5 0 V 10 0 1 10 µA VDD 3 0 V 10 0 05 5 µA IDD5 STOP mode Note 6 VDD 2 0 V 10 0 05 3 µA VDD 5 0 V 10 Note 2 7 0 14 0 mA VDD 3 0 V 10 ...

Page 352: ...plication operation VDD 2 7 to 5 5 V 14 3 15 3 15 6 µs Capture input high low level width tCPTH tCPTL CPT20 10 µs VDD 2 7 to 5 5 V 0 4 MHz TMI60 TMI61 input frequency fTI VDD 1 8 to 5 5 V 0 275 kHz VDD 2 7 to 5 5 V 0 125 µs TMI60 TMI61 input high low level width tTIH tTIL VDD 1 8 to 5 5 V 1 8 µs Interrupt input high low level width tINTH tINTL INTP0 to INTP3 10 µs KR0 to KR7 µPD789488 78F9488 10 µ...

Page 353: ...DD 1 8 to 5 5 V 0 1000 ns Note R and C are the load resistance and load capacitance of the SO20 output line b 3 wire serial I O mode external clock input Parameter Symbol Conditions MIN TYP MAX Unit VDD 2 7 to 5 5 V 800 ns SCK20 cycle time tKCY2 VDD 1 8 to 5 5 V 3200 ns VDD 2 7 to 5 5 V 400 ns SCK20 high low level width tKH2 tKL2 VDD 1 8 to 5 5 V 1600 ns VDD 2 7 to 5 5 V 100 ns SI20 setup time to ...

Page 354: ...nal clock input Parameter Symbol Conditions MIN TYP MAX Unit VDD 2 7 to 5 5 V 800 ns ASCK20 cycle time tKCY3 VDD 1 8 to 5 5 V 3200 ns VDD 2 7 to 5 5 V 400 ns ASCK20 high low level width tKH3 tKL3 VDD 1 8 to 5 5 V 1600 ns VDD 2 7 to 5 5 V 39063 bps Transfer rate VDD 1 8 to 5 5 V 9766 bps ASCK20 rise fall time tR tF 1 µs ...

Page 355: ...o 5 5 V 0 250 ns Delay time from SCK10 to SO10 output tKSO4 R 1 kΩ C 100 pF Note VDD 1 8 to 5 5 V 0 1000 ns Note R and C are the load resistance and load capacitance of the SO10 output line b 3 wire serial I O mode 3 wire serial I O mode with automatic transmit receive function external clock input Parameter Symbol Conditions MIN TYP MAX Unit VDD 2 7 to 5 5 V 800 ns SCK10 cycle time tKCY5 VDD 1 8 ...

Page 356: ...surement Points Excluding X1 and XT1 Inputs 0 8VDD 0 2VDD Point of measurement 0 8VDD 0 2VDD Clock Timing 1 fX tXL tXH X1 input VIH4 MIN VIL4 MAX 1 fXT tXTL tXTH XT1 input VIH4 MIN VIL4 MAX Capture Input Timing CPT20 tCPTL tCPTH TMI Timing 1 fTI tTIL tTIH TMI60 TMI61 Interrupt Input Timing INTP0 to INTP3 tINTL tINTH ...

Page 357: ...ng tKRL KR0 to KR7 PD789488 78F9488 KR00 to KR07 KR10 to KR17 PD789489 78F9489 µ µ RESET Input Timing RESET tRSL Serial Transfer Timing 3 wire serial I O mode Remark m 1 2 4 5 UART mode external clock input tKCY3 tKL3 tKH3 ASCK20 tR tF tKCYm tKLm tKHm SCK10 SCK20 tSIKm tKSIm tKSOm Input data Output data SI10 SI20 SO10 SO20 ...

Page 358: ...V AVDD 4 5 V 14 100 µs Conversion time tCONV 1 8 V AVDD 2 7 V 28 100 µs 4 5 V AVDD 5 5 V 0 4 FSR 2 7 V AVDD 4 5 V 0 6 FSR Zero scale error Note AINL 1 8 V AVDD 2 7 V 1 2 FSR 4 5 V AVDD 5 5 V 0 4 FSR 2 7 V AVDD 4 5 V 0 6 FSR Full scale error Note AINL 1 8 V AVDD 2 7 V 1 2 FSR 4 5 V AVDD 5 5 V 2 5 LSB 2 7 V AVDD 4 5 V 4 5 LSB Non integral linearity Note INL 1 8 V AVDD 2 7 V 8 5 LSB 4 5 V AVDD 5 5 V ...

Page 359: ...ote 3 common VODC IO 5 µA 0 0 2 V LCD output voltage differential Note 3 segment VODS IO 1 µA 0 0 2 V Notes 1 This is a capacitor that is connected between voltage pins used to drive the LCD C1 A capacitor connected between CAPH and CAPL C2 A capacitor connected between VLC0 and VSS C3 A capacitor connected between VLC1 and VSS C4 A capacitor connected between VLC2 and VSS 2 This is the wait time ...

Page 360: ...ode Operation mode tSREL tWAIT STOP instruction execution VDDDR Standby release signal interrupt request Oscillation Stabilization Wait Time TA 40 to 85 C VDD 1 8 to 5 5 V Parameter Symbol Conditions MIN TYP MAX Unit Release by RESET 2 15 fX s Oscillation stabilization wait time Note 1 tWAIT Release by interrupt Note 2 s Notes 1 Use a resonator whose oscillation stabilizes within the oscillation s...

Page 361: ... VPP supply voltage VPP1 at 5 0 MHz operation 7 mA Write current VPP pin Note IPPW When VPP supply voltage VPP1 13 mA Erase current VDD pin Note IDDE When VPP supply voltage VPP1 at 5 0 MHz operation 7 mA Erase current VPP pin Note IPPE When VPP supply voltage VPP1 100 mA Unit erase time ter 0 5 1 1 s Total erase time tera 20 s Number of overwrites Erase and write is considered as 1 cycle 20 Times...

Page 362: ...hows the characteristics curves of the time from the start of voltage boosting VAON0 1 and the changes in the LCD output voltage when GAIN is set as 1 using the 3 V display panel 5 5 5 4 5 4 3 5 3 2 5 2 1 5 1 0 5 0 LCD output voltage V VDD 4 5 V VDD 5 V VDD 5 5 V 0 500 1000 1500 2000 2500 3000 3500 4000 Voltage boosting time ms VLCD0 VLCD1 VLCD2 LCD output voltage Voltage boosting time ...

Page 363: ...ollowing shows the temperature characteristics curves of LCD output voltage LCD output voltage V VLCD2 VLCD1 VLCD0 VLCD2 VLCD1 VLCD0 40 30 20 10 0 10 20 30 40 50 60 70 80 40 30 20 10 0 10 20 30 40 50 60 70 80 Temperature C LCD output voltage Temperature When GAIN 1 5 4 3 2 1 0 5 4 3 2 1 0 LCD output voltage V Temperature C LCD output voltage Temperature When GAIN 0 ...

Page 364: ...e position T P at maximum material condition ITEM MILLIMETERS A B D G 17 20 0 20 14 00 0 20 0 13 0 825 I 17 20 0 20 J C 14 00 0 20 H 0 32 0 06 0 65 T P K 1 60 0 20 P 1 40 0 10 Q 0 125 0 075 L 0 80 0 20 F 0 825 N 0 10 M 0 17 0 03 0 07 P80GC 65 8BT 1 S 1 70 MAX R 3 7 3 41 60 40 61 21 80 20 1 S S N J detail of lead end C D A B R K M L P I S Q G F M H ...

Page 365: ... 0 0 2 D F 1 25 14 0 0 2 B 12 0 0 2 M N 0 08 0 145 0 05 P Q 0 1 0 05 1 0 J 0 5 T P K L 0 5 1 0 0 2 I 0 08 S 1 1 0 1 R 3 4 3 R H K L J F Q G I T U S P detail of lead end NOTE Each lead centerline is located within 0 08 mm of its true position T P at maximum material condition 60 41 40 21 61 80 1 20 M S S C D A B N M P80GK 50 9EU 1 T 0 25 U 0 6 0 15 ...

Page 366: ...erature 260 C max Time 10 seconds max Count Once Preheating temperature 120 C max package surface temperature WS60 00 1 Partial heating Pin temperature 350 C max Time 3 seconds max per pin row Caution Do not use different soldering methods together except for partial heating 2 µ PD789488GK 9EU 80 pin plastic TQFP fine pitch 12x12 µ PD78F9488GK 9EU 80 pin plastic TQFP fine pitch 12x12 µ PD789489GK ...

Page 367: ...ature 350 C max Time 3 seconds max per pin row Note After opening the dry peak store it at 25 C or less and 65 RH or less for the allowable storage period Caution Do not use different soldering methods together except for partial heating 4 µ PD78F9489GK 9EU 80 pin plastic TQFP fine pitch 12x12 Soldering Method Soldering Conditions Recommended Condition Symbol Interface reflow Package peak temperat...

Page 368: ...flow Package peak temperature 260 C Time 60 seconds max at 220 C or higher Count Three times or less Exposure limit 7 days Note after that prebake at 125 C for 20 to 72 hours IR60 207 3 Wave soldering When the pin pitch of the package is 0 65 mm or more wave soldering can also be performed For details contact an NEC Electronics sales representative Partial heating Pin temperature 350 C max Time 3 ...

Page 369: ...pment tools Support for PC98 NX Series Unless specified otherwise the products supported by IBM PC AT compatibles can be used in the PC98 NX Series When using the PC98 NX Series refer to the explanation of IBM PC AT compatibles Windows Unless specified otherwise Windows indicates the following operating systems Windows 3 1 Windows 95 Windows 98 Windows 2000 Windows NT Ver 4 0 Windows XP ...

Page 370: ... circuit emulator Emulation board Emulation probe Conversion socket or conversion adapter Target system Flash programmer Flash memory writing adapter Flash memory Power supply unit Software package Control software Project manager Windows version only Note 2 Software package Flash memory writing environment Notes 1 C library source file is not included in the software package 2 The project manager...

Page 371: ...ackage Part number µS RA78K0S Program that converts program written in C language into object codes that can be executed by a microcontroller Used in combination with an assembler package RA78K0S and device file DF789488 both sold separately Caution when used in PC environment The C compiler package is a DOS based application but may be used in the Windows environment by using the project manager ...

Page 372: ...1 4 inch CGMT A 3 Control Software PM plus Project manager Control software created for efficient development of the user program in the Windows environment User program development operations such as editor startup build and debugger startup can be performed from the PM plus Caution The PM plus is included in the assembler package RA78K0S The PM plus is used only in the Windows environment A 4 Fl...

Page 373: ...t machine IE 789488 NS EM1 Emulation board Board for emulating the peripheral hardware inherent to the device Used in combination with an in circuit emulator NP 80GC Emulation probe Cable to connect the in circuit emulator and target system Used in combination with the EV 9200GC 80 EV 9200GC 80 Conversion socket Conversion socket to connect the NP 80GC and a target system board on which an 80 pin ...

Page 374: ...le simulating the operation of the target system on the host machine Using SM78K0S the logic and performance of the application can be verified independently of hardware development Therefore the development efficiency can be enhanced and the software quality can be improved Used in combination with a device file DF789488 sold separately SM78K0S System simulator Part number µS SM78K0S File contain...

Page 375: ... 080SBP and TGK 080SDP are products of TOKYO ELETECH CORPORATION Table B 1 Distance Between IE System and Conversion Adapter Emulation Probe Conversion Adapter Distance Between IE System and Conversion Adapter NP 80GC TQ 170 mm NP H80GC TQ TGC 080SBP 370 mm NP 80GK 170 mm NP H80GK TQ TGK 080SDP 370 mm 1 NP 80GC NP 80GC TQ NP H80GC TQ Figure B 1 Distance Between In Circuit Emulator and Conversion S...

Page 376: ...P 80GC TQ Emulation board IE 789488 NS EM1 24 8 mm 25 mm 40 mm 34 mm Target system 21 mm Pin 1 11 mm 21 mm Conversion adapter TGC 080SBP Figure B 3 Connection Conditions of Target System When NP H80GC TQ Is Used Emulation probe NP H80GC TQ Emulation board IE 789488 NS EM1 25 3 mm 25 mm 42 mm 45 mm Target system 21 mm Pin 1 11 mm Conversion adapter TGC 080SBP 21 mm ...

Page 377: ...etween In Circuit Emulator and Conversion Adapter 80GK 170 mm Note In circuit emulator IE 78K0S NS or IE 78K0S NS A Emulation board IE 789488 NS EM1 Conversion adapter TGK 080SDP Target system TGCN1 Emulation probe NP 80GK NP H80GK TQ Note Distance when NP 80GK is used When NP H80GK TQ is used the distance is 370 mm ...

Page 378: ... NP 80GK Emulation board IE 789488 NS EM1 23 mm 40 mm 34 mm Target system 16 mm Pin 1 11 mm 25 mm 16 mm Conversion adapter TGK 080SDP Figure B 6 Connection Conditions of Target System When NP H80GK TQ Is Used Emulation probe NP H80GK TQ Emulation board IE 789488 NS EM1 42 mm 45 mm 16 mm Target system 16 mm Pin 1 23 mm 10 mm Conversion adapter TGK 080SDP 11 mm ...

Page 379: ...ster 60 TCA60 131 E 8 bit compare register 50 CR50 126 8 bit compare register 60 CR60 126 8 bit compare register 61 CR61 126 8 bit H width compare register 60 CRH60 127 8 bit H width compare register 61 CRH61 127 8 bit timer counter 50 TM50 127 8 bit timer counter 60 TM60 127 8 bit timer counter 61 TM61 127 8 bit timer mode control register 50 TMC50 128 8 bit timer mode control register 60 TMC60 1...

Page 380: ...rt mode register 5 PM5 91 Port mode register 8 PM8 91 Processor clock control register PCC 98 Pull up resistor option register B0 PUB0 93 Pull up resistor option register B1 PUB1 93 Pull up resistor option register B2 PUB2 93 Pull up resistor option register B3 PUB3 93 R Receive buffer register 20 RXB20 189 Remote controller DH0L compare register RMDH0L 275 Remote controller DH1L compare register ...

Page 381: ...tion result storage register L MUL0L 267 16 bit timer counter 20 TM20 109 16 bit timer mode control register 20 TMC20 109 Serial I O shift register 1A0 SIO1A0 218 Serial operation mode register 1A0 CSIM1A0 219 Serial operation mode register 20 CSIM20 190 Subclock control register CSS 99 Subclock oscillation mode register SCKM 99 Subclock selection register SSCK 100 T Transmit shift register 20 TXS...

Page 382: ... bit compare register 60 126 CR61 8 bit compare register 61 126 CRH60 8 bit H width compare register 60 127 CRH61 8 bit H width compare register 61 127 CSIM1A0 Serial operation mode register 1A0 219 CSIM20 Serial operation mode register 20 190 CSS Subclock control register 99 I IF0 Interrupt request flag register 0 295 IF1 Interrupt request flag register 1 295 IF2 Interrupt request flag register 2...

Page 383: ...option register B1 93 PUB2 Pull up resistor option register B2 93 PUB3 Pull up resistor option register B3 93 R RMCN Remote controller receive control register 277 RMDH0L Remote controller DH0L compare register 275 RMDH0S Remote controller receive DH0S compare register 275 RMDH1L Remote controller DH1L compare register 275 RMDH1S Remote controller receive DH1S compare register 275 RMDLL Remote con...

Page 384: ...unter 50 127 TM60 8 bit timer counter 60 127 TM61 8 bit timer counter 61 127 TMC20 16 bit timer mode control register 20 110 TMC50 8 bit timer mode control register 50 128 TMC60 8 bit timer mode control register 60 129 TMC61 8 bit timer mode control register 61 132 TXS20 Transmit shift register 20 189 W WDCS Watchdog timer clock selection register 169 WDTM Watchdog timer mode register 170 WTIM Wat...

Page 385: ...on PE20 flag in Figure 11 5 Format of Asynchronous Serial Interface Status Register 20 Addition of description on UART receive data read CHAPTER 11 SERIAL INTERFACE 20 Change of Figure 13 2 LCD Controller Driver Block Diagram Addition of 13 8 Supplying LCD Drive Voltages VLC0 VLC1 and VLC2 CHAPTER 13 LCD CONTROLLER DRIVER Modification of description on serial interface 20 in Table 17 1 Status of H...

Page 386: ...e Wave Output Range of Timer 61 CHAPTER 7 8 BIT TIMERS 50 60 61 Modification of Caution in Figure 8 4 Watch Timer Interval Timer Operation Timing CHAPTER 8 WATCH TIMER Addition of descriptions in 2 A D conversion result register 0 ADCRL0 in 10 2 10 Bit A D Converter Configuration Addition of 8 Input impedance of ANI0 to ANI7 pins in 10 5 Cautions Related to 10 Bit A D Converter CHAPTER 10 10 BIT A...

Page 387: ...4 3 Operation as carrier generator Modification of Figure 7 22 Timing of Carrier Generator Operation When CR60 N CRH60 M M N Modification of Figure 7 23 Timing of Carrier Generator Operation When CR60 N CRH60 M M N Modification of Figure 7 24 Timing of Carrier Generator Operation When CR60 CRH60 N Modification of the mode name in 7 4 4 PWM output mode operation timer 50 Modification of the mode na...

Page 388: ...9489 and 78F9489 to µPD789489 78F9489 CHAPTER 22 ELECTRICAL SPECIFICATIONS µPD789488 78F9488 789489 78F9489 4th Addition of recommended conditions for µPD789489 and 78F9489 CHAPTER 25 RECOMMENDED SOLDERING CONDITIONS Addition of the lead free products Throughout Modification of descriptions of the voltage boost wait time CHAPTER 13 LCD CONTROLLER DRIVER 4th Modified version Modification of Figure ...

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