CHAPTER 5 CLOCK GENERATOR
96
User’s Manual U15331EJ4V1UD
Figure 5-1. Clock Generator Block Diagram (
µ
PD789488, 789489)
f
XT
8f
XT
f
XTT
X1
X2
XT1
XT2
f
X
f
X
2
2
f
XTT
2
1/2
Prescaler
Standby
controller
Wait
controller
Mask
option
STOP
MCC PCC1
CLS
Internal bus
CSS0
FRC SCC
Internal bus
Timer 50
Watch timer
LCD controller/driver
Clock to peripheral
hardware
CPU clock
(f
CPU
)
Subclock control
register (CSS)
Processor clock control
register (PCC)
Subclock oscillation
mode register
(SCKM)
Subsystem
clock
oscillator
Subsystem
clock
oscillator
×
4
multiplication
circuit
×
2
multiplication
circuit
Selector
Remark
f
XTT
: f
XT
or 8f
XT