CHAPTER 3 CPU ARCHITECTURE
50
User’s Manual U15331EJ4V1UD
Figure 3-3. Memory Map (
µ
PD789489)
B F F F H
0 0 0 0 H
0 0 8 0 H
0 0 7 F H
0 0 4 0 H
0 0 3 F H
0 0 3 0 H
0 0 2 F H
Program area
Program area
CALLT table area
Vector table area
Special function registers
256
×
8 bits
Internal high-speed RAM
1024
×
8 bits
Internal low-speed
512
×
8 bits
LCD display RAM
28
×
4 bits
Internal ROM
49152
×
8 bits
Reserved
Reserved
Reserved
Program memory
space
Data memory
space
F 7 0 0 H
F 6 F F H
F 5 0 0 H
F 4 F F H
C 0 0 0 H
B F F F H
F F F F H
F F 0 0 H
F E F F H
F B 0 0 H
F A F F H
0 0 0 0 H
F A 1 C H
F A 1 B H
F A 0 0 H
F 9 F F H