CHAPTER 3 CPU ARCHITECTURE
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User’s Manual U15331EJ4V1UD
3.3.3 Table indirect addressing
[Function]
Table contents (branch destination address) of the particular location to be addressed by the lower 5-bit
immediate data of an instruction code from bit 1 to bit 5 are transferred to the program counter (PC) and
branched.
This function is carried out when the CALLT [addr5] instruction is executed. The instruction enables a branch
to any location in the memory space by referring to the addresses stored in the memory table at 40H to 7FH.
[Illustration]
15
1
15
0
PC
7
0
Low Addr.
High Addr.
Memory (Table)
Effective a 1
Effective address
0
1
0
0
0
0
0
0
0
0
8
7
8
7
6
5
0
0
0
0
1
7
6
5
1
0
ta
4–0
Instruction code
3.3.4 Register addressing
[Function]
The register pair (AX) contents to be specified with an instruction word are transferred to the program counter
(PC) and branched.
This function is carried out when the BR AX instruction is executed.
[Illustration]
7
0
rp
0
7
A
X
15
0
PC
8
7
