CHAPTER 11 SERIAL INTERFACE 20
User’s Manual U15331EJ4V1UD
195
The baud rate transmit/receive clock to be generated is either a divided system clock signal, or a signal
obtained by dividing the clock input to the ASCK20 pin.
(a) Generation of UART baud rate transmit/receive clock form system clock
The transmit/receive clock is generated by dividing the system clock. The baud rate of a clock generated
from the system clock is estimated by using the following expression.
[Baud rate] = [bps]
f
X
: Main system clock oscillation frequency
n: Values in Figure 11-6, determined by the values of TPS200 to TPS203 (2
≤
n
≤
8)
Table 11-3. Example of Relationship Between System Clock and Baud Rate
Error (%)
Baud Rate (bps)
n
BRGC20 Set Value
f
X
= 5.0 MHz
f
X
= 4.9152 MHz
1,200 8 70H
2,400 7 60H
4,800 6 50H
9,600 5 40H
19,200 4 30H
38,400 3 20H
76,800 2 10H
1.73 0
Caution Do not select n = 1 during operation at f
X
> 2.5 MHz because the resulting baud rate exceeds the
rated range.
f
X
2
n + 1
×
8
