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CHAPTER 14 SERIAL INTERFACE (SIO1)
Preliminary User’s Manual U13420EJ2V0UM00
In 6-byte transmission/reception (bit 6 (ARLD0) and bit 7 (RE0) of the automatic data transmit/receive
control register (ADTC0) = 0, and 1, respectively) in basic transmit/receive mode, buffer RAM operates
as follows.
(i)
Before transmission/reception (refer to Figure 14-9 (a))
After any data has been written to SIO1 (start trigger: this data is not transferred), transmit data 1
(T1) is transferred from the buffer RAM to SIO1. When transmission of the first byte is completed,
the receive data 1 (R1) is transferred from SIO1 to the buffer RAM, and automatic data transmit/
receive address pointer (ADTP0) is decremented. Then transmit data 2 (T2) is transferred from the
buffer RAM to SIO1.
(ii) 4th byte transmit/receive point (refer to Figure 14-9 (b))
Transmission/reception of the third byte is completed, and transmit data 4 (T4) is transferred from
the buffer RAM to SIO1. When transmission of the fourth byte is completed, the receive data 4 (R4)
is transferred from SIO1 to the buffer RAM, and ADTP0 is decremented.
(iii) Completion of transmission/reception (refer to Figure 14-9 (c))
When transmission of the sixth byte is completed, receive data 6 (R6) is transferred from SIO1 to
the buffer RAM, and the interrupt request flag (CSIIF1) is set (INTCSI1 generation).
Figure 14-9. Buffer RAM Operation in 6-Byte Transmission/Reception
(in Basic Transmit/Receive Mode) (1/2)
(a) Before transmission/reception
Transmit data 1 (T1)
Transmit data 2 (T2)
Transmit data 3 (T3)
Transmit data 4 (T4)
Transmit data 5 (T5)
Transmit data 6 (T6)
FADFH
FAC5H
FAC0H
Receive data 1 (R1)
SIO1
0
CSIIF1
5
ADTP0
_1
Summary of Contents for mPD780065 Series
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