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NEC mPD780065 Series, Preliminary User'S Manual

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CHAPTER 14   SERIAL INTERFACE (SIO1)

Preliminary User’s Manual  U13420EJ2V0UM00

(5) Timing of interrupt request signal generation

The interrupt request signal is generated in synchronization with the timing shown in Table 14-2.

Table 14-2.  Timing of Interrupt Request Signal Generation

Operating Mode

Timing of Interrupt Request Signal

Single mode

Master mode

10th serial clock at end of transfer

Slave mode

8th serial clock at end of transfer

Repetitive transmit mode

Not generated

If bit shift occurs during transmission/reception

8th serial clock

(6) Interval time of automatic transmission/reception

Because read/write to/from the buffer RAM using the automatic transmit/receive function is performed

asynchronously with CPU processing, the interval time is dependent on the CPU processing of the timing of

the eighth rising of the serial clock and the set value of the automatic data transmit/receive interval specification

register (ADTI0).  Whether the interval time is dependent on ADTI0 is selected by setting of the bit 7 (ADTI07)

of ADTI0.  If ADTI07 is reset to 0, the interval time is 2/f

SCK

.  If ADTI07 is set to 1, the interval time determined

by the set contents of ADTI0 or interval time (2/f

SCK

) according to CPU processing is selected, whichever is

is greater.

Figure 14-23 shows the interval time of automatic transmission/reception

Remark

f

SCK

:  Serial clock frequency

Figure 14-23.  Interval Time of Automatic Transmission/Reception

The following expression must be satisfied to access the buffer RAM.

1 transfer cycle + interval time 

≥

 Read Write CPU buffer RAM access (time)

In the case of a “high-speed CPU & low-speed SCK

Note

”, the interval time is not necessary.  In the case of

a “low-speed CPU & high-speed SCK

Note

”, the interval time is necessary.

In this case, make sure that a sufficient interval time elapses by using the automatic data transmit/receive

interval specification register (ADTI0), so that the above expression is satisfied.

Note The speeds of the CPU clock and SCK differ depending on the type of CPU core.

Interval

SCK1

D7

SO1

SI1

CSIIF1

D6 D5 D4 D3 D2 D1 D0

D7 D6 D5 D4 D3 D2 D1 D0

D7 D6 D5 D4 D3 D2 D1 D0

D7 D6 D5 D4 D3 D2 D1 D0

Summary of Contents for mPD780065 Series

Page 1: ...1998 1999 µPD780065 Subseries 8 Bit Single Chip Microcontrollers µPD780065 µPD78F0066 Document No U13420EJ2V0UM00 2nd edition Date Published May 1999 N CP K Preliminary User s Manual Printed in Japan ...

Page 2: ...Preliminary User s Manual U13420EJ2V0UM00 2 MEMO ...

Page 3: ...ielding bag or conductive material All test and measurement tools including work bench and floor should be grounded The operator should be grounded using wrist strap Semiconductor devices must not be touched with bare hands Similar precautions need to be taken for PW boards with semiconductor devices on it 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note No connection for CMOS device inputs can be ca...

Page 4: ...y to persons or property arising from a defect in an NEC semiconductor device customers must incorporate sufficient safety measures in its design such as redundancy fire containment and anti failure features NEC devices are classified into the following three quality grades Standard Special and Specific The Specific quality grade applies only to devices developed based on a customer designated qua...

Page 5: ...C Electronics Germany GmbH Benelux Office Eindhoven The Netherlands Tel 040 2445845 Fax 040 2444580 NEC Electronics France S A Velizy Villacoublay France Tel 01 30 67 58 00 Fax 01 30 67 58 99 NEC Electronics France S A Spain Office Madrid Spain Tel 91 504 2787 Fax 91 504 2860 NEC Electronics Germany GmbH Scandinavia Office Taeby Sweden Tel 08 63 80 820 Fax 08 63 80 388 Regional Information Some in...

Page 6: ...circuit in Figure 6 8 Interval Timer Configuration Diagram p 133 Addition of cautions on sampling clock in 6 6 12 Edge detection p 187 Modification of the input buffer to the schmitt triggered input in Figure 13 1 Serial Interface UART0 Block Diagram pp 209 to Modification of following register symbols and bit names in CHAPTER 14 SERIAL INTERFACE 250 SIO1 Automatic Data Transmit Receive Address Po...

Page 7: ...nation of each instruction Other on chip peripheral functions How To Read This Manual Before reading this manual you should have general knowledge of electric and logic circuits and microcontrollers To gain a general understanding of functions Read this manual in the order of the contents How to interpret the register format For the bit number enclosed in square the bit name is defined as a reserv...

Page 8: ...ed Assembly Language U11789E U11789J RA78K Series Structured Assembler Preprocessor EEU 1402 U12323J CC78K0 C Compiler Operation U11517E U11517J Language U11518E U11518J CC78K 0 C Compiler Application Note Programming Know how U13034E U13034J IE 78K0 NS To be prepared To be prepared IE 78001 R A To be prepared To be prepared IE 78K0 R EX1 To be prepared To be prepared IE 780066 NS EM4 To be prepar...

Page 9: ...ELECTION GUIDE Products Packages CD ROM X13769X Semiconductor Device Mounting Technology Manual C10535E C10535J Quality Grades on NEC Semiconductor Devices C11531E C11531J NEC Semiconductor Device Reliability Quality Control System C10983E C10983J Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge ESD C11892E C11892J Guide to Microcomputer Related Products by Third Party ...

Page 10: ...10 Preliminary User s Manual U13420EJ2V0UM00 MEMO ...

Page 11: ...57 Port 5 37 2 2 6 P64 to P67 Port 6 37 2 2 7 P70 to P77 Port 7 38 2 2 8 P80 to P84 Port 8 39 2 2 9 P90 to P92 Port 9 39 2 2 10 ANI0 to ANI7 39 2 2 11 AVREF 40 2 2 12 AVSS 40 2 2 13 RESET 40 2 2 14 X1 and X2 40 2 2 15 XT1 and XT2 40 2 2 16 VDD0 and VDD1 40 2 2 17 VSS0 and VSS1 40 2 2 18 VPP flash memory version only 40 2 2 19 IC mask ROM version only 40 2 3 Pin I O Circuits and Recommended Connect...

Page 12: ...essing 69 3 4 8 Based indexed addressing 70 3 4 9 Stack addressing 70 CHAPTER 4 PORT FUNCTIONS 71 4 1 Port Functions 71 4 2 Port Configuration 73 4 2 1 Port 0 73 4 2 2 Port 2 75 4 2 3 Port 3 76 4 2 4 Port 4 77 4 2 5 Port 5 78 4 2 6 Port 6 79 4 2 7 Port 7 80 4 2 8 Port 8 82 4 2 9 Port 9 83 4 3 Port Function Control Registers 84 4 4 Port Function Operations 88 4 4 1 Writing to input output port 88 4...

Page 13: ...r operation 124 6 5 5 Square wave output operation 125 6 5 6 One shot pulse output operation 127 6 6 16 Bit Timer Event Counter Operating Precautions 130 CHAPTER 7 8 BIT TIMER EVENT COUNTER 135 7 1 8 Bit Timer Event Counter Functions 135 7 2 8 Bit Timer Event Counter Configurations 137 7 3 Registers to Control 8 Bit Timer Event Counter 138 7 4 8 Bit Timer Event Counter Operations 142 7 4 1 8 bit i...

Page 14: ...ter 178 11 4 2 Input voltage and conversion results 180 11 4 3 A D converter operation mode 181 11 5 A D Converter Cautions 182 CHAPTER 12 SERIAL INTERFACE OUTLINE 185 CHAPTER 13 SERIAL INTERFACE UART0 187 13 1 Serial Interface UART0 Functions 187 13 2 Serial Interface UART0 Configuration 188 13 3 Registers to Control Serial Interface UART0 189 13 4 Serial Interface UART0 Operations 193 13 4 1 Ope...

Page 15: ...tion Types 263 17 2 Interrupt Sources and Configuration 263 17 3 Interrupt Function Control Registers 267 17 4 Interrupt Servicing Operations 273 17 4 1 Non maskable interrupt request acknowledge operation 273 17 4 2 Maskable interrupt acknowledge operation 276 17 4 3 Software interrupt request acknowledge operation 278 17 4 4 Multiple interrupt servicing 279 17 4 5 Interrupt request hold 282 CHAP...

Page 16: ...s and description methods 312 22 1 2 Description of operation column 313 22 1 3 Description of flag operation column 313 22 2 Operation List 314 22 3 Instructions Listed by Addressing Type 322 APPENDIX A DEVELOPMENT TOOLS 327 A 1 Language Processing Software 330 A 2 Flash Memory Writing Tools 331 A 3 Debugging Tools 332 A 3 1 Hardware 332 A 3 2 Software 334 A 4 System Upgrade from Former In circui...

Page 17: ...iagram of P80 to P84 82 4 11 Block Diagram of P90 to P92 83 4 12 Format of Port Mode Registers PM0 PM2 to PM9 85 4 13 Format of Pull Up Resistor Option Registers PU0 PU2 to PU9 87 5 1 Clock Generator Block Diagram 90 5 2 Subsystem Clock Feedback Resistor 91 5 3 Format of Processor Clock Control Register PCC 92 5 4 External Circuit of Main System Clock Oscillator 93 5 5 External Circuit of Subsyste...

Page 18: ...ntrol Register Settings in External Event Counter Mode 124 6 22 External Event Counter Configuration Diagram 125 6 23 External Event Counter Operation Timings with Rising Edge Specified 125 6 24 Control Register Settings in Square Wave Output Mode 126 6 25 Square Wave Output Operation Timing 127 6 26 Control Register Settings for One Shot Pulse Output Operation Using Software Trigger 128 6 27 Timi...

Page 19: ...nversion End Interrupt Request Generation Timing 184 13 1 Serial Interface UART0 Block Diagram 187 13 2 Format of Asynchronous Serial Interface Mode Register ASIM0 190 13 3 Format of Asynchronous Serial Interface Status Register ASIS0 191 13 4 Format of Baud Rate Generator Control Register BRGC0 192 13 5 Error Tolerance when k 0 Including Sampling Errors 200 13 6 Format of Transmit Receive Data in...

Page 20: ...of 2 Wire Serial I O Mode 256 16 1 Serial Interface SIO31 Block Diagram 257 16 2 Format of Serial Operation Mode Register 31 CSIM31 259 16 3 Timing of 3 Wire Serial I O Mode 262 17 1 Basic Configuration of Interrupt Function 265 17 2 Format of Interrupt Request Flag Registers IF0L IF0H IF1L 268 17 3 Format of Interrupt Mask Flag Registers MK0L MK0H MK1L 269 17 4 Format of Priority Specify Flag Reg...

Page 21: ...elease by RESET Input 300 20 1 Reset Function Block Diagram 301 20 2 Timing of Reset by RESET Input 302 20 3 Timing of Reset due to Watchdog Timer Overflow 302 20 4 Timing of Reset in STOP Mode by RESET Input 302 21 1 Format of Memory Size Switching Register IMS 306 21 2 Format of Internal Expansion RAM Size Switching Register IXS 307 21 3 Format of Transmission Method Selection 308 21 4 Connectio...

Page 22: ...22 Preliminary User s Manual U13420EJ2V0UM00 MEMO ...

Page 23: ...8 Bit Timer Event Counter Configurations 137 8 1 Interval Timer Interval Time 156 8 2 Watch Timer Configuration 156 8 3 Interval Timer Interval Time 158 9 1 Watchdog Timer Runaway Detection Times 162 9 2 Interval Times 162 9 3 Watchdog Timer Configuration 163 9 4 Watchdog Timer Runaway Detection Time 167 9 5 Interval Timer Interval Time 168 10 1 Configuration of Clock Output Control Circuits 170 1...

Page 24: ... 18 1 Pin Functions in External Memory Expansion Mode 283 18 2 State of Port 4 to 6 Pins in External Memory Expansion Mode 283 19 1 HALT Mode Operating Statuses 295 19 2 Operation after HALT Mode Release 297 19 3 STOP Mode Operating Status 298 19 4 Operation after STOP Mode Release 300 20 1 Hardware Statuses after Reset 303 21 1 Differences between µPD78F0066 and Mask ROM Version 305 21 2 Transmis...

Page 25: ...lock to ultra low speed 122 µs 32 768 kHz operation with subsystem clock Instruction set suited to system control Bit manipulation possible in all address spaces Multiply and divide instructions Sixty I O ports 8 bit resolution A D converter 8 channels Serial interface 4 channels 3 wire serial I O mode provided with automatic transmission reception function 1 channel 3 wire serial I O mode 1 chann...

Page 26: ...V0UM00 1 2 Applications Car audio supporting CD text etc 1 3 Ordering Information Part Number Package Internal ROM µPD780065GC 8BT 80 pin plastic QFP 14 14 mm Mask ROM µPD78F0066GC 8BT 80 pin plastic QFP 14 14 mm Flash memory Remark indicates ROM code suffix ...

Page 27: ...ded for the µPD78F0066 1 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 ANI7 2 ANI6 3 ANI5 4 ANI4 5 ANI3 6 ANI2 7 ANI1 8 ANI0 9 AVREF 10 RESET 11 XT1 12 XT2 13 IC VPP 14 X1 15 X2 16 VDD1 17 VSS1 18 P90 SCK31 19 P91 SO31 20 P92 SI31 60 P42 AD2 59 P43 AD3 58 P44 AD4 57 P45 AD5 56 P46 AD6 55 P47 AD7 54 P50 A8 53 P51 A9 52 P52 A10 51 P53 A11 50 P54 A12 49 P55 A13 48 P56 A14 47 P57 A15 46 ...

Page 28: ...Output AVSS Analog Ground SI1 SI31 Serial Input BUSY Busy SO1 SO31 Serial Output IC Internally Connected STB Strobe INTP0 to INTP3 Interrupt from Peripherals TI00 TI01 TI50 TI51 Timer Input P00 to P07 Port0 TO0 TO50 TO51 Timer Output P20 to P27 Port2 TxD0 Transmit Data P30 to P37 Port3 VDD0 VDD1 Power Supply P40 to P47 Port4 VPP Programming Power Supply P50 to P57 Port5 VSS0 VSS1 Ground P64 to P67...

Page 29: ...I O and FIP C D Display output total 53 PD78064F with enhanced I O and FIP C D Display output total 48 PD78044F with N ch open drain I O Display output total 34 PD780988 64 pin Inverter control On chip inverter controller and UART reduced EMI noise PD78064 with enhanced SIO and expanded ROM and RAM PD78064 with reduced EMI noise Basic subseries for LCD drive On chip UART On chip DCAN controller PD...

Page 30: ...18F 8 K to 60 K µPD78083 8 K to 16 K 1 ch UART 1 ch 33 Inverter µPD780988 16 K to 60 K 3 ch Note 1 ch 8 ch 3 ch UART 2 ch 47 4 0 V control FIP µPD780208 32 K to 60 K 2 ch 1 ch 1 ch 1 ch 8 ch 2 ch 74 2 7 V drive µPD780228 48 K to 60 K 3 ch 1 ch 72 4 5 V µPD780232 16 K to 24 K 4 ch 2 ch 40 µPD78044H 32 K to 48 K 2 ch 1 ch 1 ch 8 ch 1 ch 68 2 7 V µPD78044F 16 K to 40 K 2 ch LCD µPD780308 48 K to 60 K...

Page 31: ... TI00 TO0 P20 TI01 P21 TI50 TO50 P22 TI51 TO51 P23 SDIO30 P75 SCK30 P74 SI31 P92 SO31 P91 SCK31 P90 RxD0 P73 TxD0 P72 ASCK0 P71 AVSS AVREF PCL P70 SERIAL INTERFACE 30 SERIAL INTERFACE 1 SI1 P84 SO1 P83 SCK1 P82 BUSY P81 STB P80 ANI0 to ANI7 INTP0 P00 to INTP3 P03 VDD0 VDD1 VSS0 VSS1 IC VPP 78K 0 CPU CORE ROM RAM PORT 0 P00 to P07 PORT 9 P90 to P92 PORT 8 P80 to P84 PORT 2 P20 to P27 PORT 3 P30 to ...

Page 32: ... O port CMOS I O 60 A D converter 8 bit resolution 8 channels Low voltage operation AVDD 2 7 to 5 5 V Serial interface 3 wire serial I O mode 1 channel 3 wire serial I O mode provided with automatic transmit receive function 1 channel 2 wire serial I O mode 1 channel UART mode 1 channel Timer 16 bit timer event counter 1 channel 8 bit timer event counter 2 channels Watch timer 1 channel Watchdog t...

Page 33: ...1 bit units An on chip pull up resistor can be specified by means of software P64 Input Output Input RD P65 WR P66 WAIT P67 ASTB CHAPTER 2 PIN FUNCTION 2 1 Pin Functions 1 Port Pins 1 2 Port 0 8 bit input output port Input output mode can be specified in 1 bit units An on chip pull up resistor can be specified by means of software Port 2 8 bit input output port Input output mode can be specified i...

Page 34: ...s An on chip pull up resistor can be specified by means of software Pin Name Input Output Function After Reset Alternate Function INTP0 to Input External interrupt request input with specifiable valid edges Input P00 to P03 INTP3 rising edge falling edge both rising and falling edges SI1 Input Serial interface serial data input Input P84 SI31 P92 SO1 Output Serial interface serial data output Inpu...

Page 35: ...o A15 Output High order address bus when expanding external memory Input P50 to P57 RD Output Strobe signal output for read operation from external memory Input P64 WR Strobe signal output for write operation from external memory P65 WAIT Input Wait insertion when accessing external memory Input P66 ASTB Output Strobe output externally latching address information Input P67 output to ports 4 5 to ...

Page 36: ...an be specified 2 2 2 P20 to P27 Port 2 This is an 8 bit input output port Besides serving as an input output port these pins function as timer input outputs The following operating modes can be specified in 1 bit units 1 Port mode These pins function as an 8 bit input output port They can be specified in 1 bit units as input or output ports with port mode register 2 PM2 On chip pull up resistors ...

Page 37: ... output ports these pins function as an address bus The following operating modes can be specified in 1 bit units 1 Port mode These pins function as an 8 bit input output port They can be specified in 1 bit units as input output ports with port mode register 5 PM5 On chip pull up resistors can be specified by defining pull up resistor option register 5 PU5 2 Control mode These pins function as hig...

Page 38: ...port They can be specified in 1 bit units as input or output ports with port mode register 7 PM7 On chip pull up resistors can be specified by defining pull up resistor option register 7 PU7 2 Control mode These pins function as serial data input output serial clock input output and clock output of the serial interface a SDIO30 The serial interface serial data input output pin b SCK30 The serial i...

Page 39: ...erial data input output pins b SCK1 The serial interface serial clock input output pin c BUSY The serial interface automatic transmission reception busy input pin d STB The serial interface automatic transmission reception strobe output pin 2 2 9 P90 to P92 Port 9 This is a 3 bit input output port Besides serving as serial interface input output ports these pins function as the data input output a...

Page 40: ... XT2 2 2 16 VDD0 and VDD1 VDD0 is a positive power supply port pin VDD1 is a positive power supply pin other than port pin 2 2 17 VSS0 and VSS1 VSS0 is a ground potential port pin VSS1 is a ground potential pin other than port pin 2 2 18 VPP flash memory version only High voltage apply pin for flash memory programming mode setting and program write verify Connect directly to VSS0 or VSS1 in the no...

Page 41: ...P04 to P07 P20 T100 TO0 Independently connect to VDD0 or VSS0 via a resistor P21 T101 P22 TI50 TO50 P23 TI51 TO51 P24 to P27 P30 to P37 P40 AD0 to P47 AD7 5 H Independently connect to VDD0 via a resistor P50 A8 to P57 A15 Independently connect to VDD0 or VSS0 via a resistor P64 RD P65 WR P66 WAIT P67 ASTB P70 PCL P71 ASCK0 8 C P72 TxD0 5 H P73 RxD0 8 C P74 SCK30 P75 SDIO30 5 H P76 P77 8 C P80 STB ...

Page 42: ...triggered input with hysteresis characteristics IN Type 8 C data output disable P ch IN OUT VDD0 N ch P ch VDD0 pullup enable Type 5 H data output disable P ch IN OUT VDD0 N ch input enable P ch VDD0 pullup enable Type 16 Type 7 B VSS0 VSS0 P ch feedback cut off XT1 XT2 IN Comparator P ch N ch AVSS VREF Threshold voltage ...

Page 43: ...ching Register IXS µPD780065 CAH 04H µPD78F0066 CCH or the value corresponding to mask ROM version Figure 3 1 Memory Map µPD780065 Reserved Internal buffer RAM 32 8 bits Reserved Internal expansion RAM 4096 8 bits 0000H Data memory space Internal ROM 40960 8 bits 9FFFH 1000H 0FFFH 0800H 07FFH 0080H 007FH 0040H 003FH 0000H CALLF entry area CALLT table area Vector table area Program area Program are...

Page 44: ...h memory 49152 8 bits BFFFH 1000H 0FFFH 0800H 07FFH 0080H 007FH 0040H 003FH 0000H CALLF entry area CALLT table area Vector table area Program area Program area External memory 10240 8 bits Program memory space C000H BFFFH E800H E7FFH FEE0H FEDFH FAE0H FADFH FAC0H FABFH F800H F7FFH FF00H FEFFH FFFFH Internal high speed RAM 1024 8 bits Special function registers SFRs 256 8 bits FB00H FAFFH General r...

Page 45: ...ly it is addressed with the program counter PC The µPD780065 Subseries products incorporate an internal ROM or flash memory as listed below Table 3 1 Internal ROM Capacity Part Number Internal ROM Type Capacity µPD780065 Mask ROM 40960 8 bits 0000H to 9FFFH µPD78F0066 Flash Memory 49152 8 bits 0000H to BFFFH The internal program memory space is divided into the following three areas ...

Page 46: ...ddresses Table 3 2 Vector Table Vector Table Address Interrupt Source 0000H RESET input 0004H INTWDT 0006H INTP0 0008H INTP1 000AH INTP2 000CH INTP3 000EH INTSER0 0010H INTSR0 0012H INTST0 0014H INTCSI30 0016H INTCSI31 0018H INTCSI1 001AH INTTM00 001CH INTTM01 001EH INTTM50 0020H INTTM51 0022H INTWTI 0024H INTWT 0026H INTAD0 003EH BRK 2 CALLT instruction table area The 64 byte area 0040H to 007FH ...

Page 47: ...oring transmitted received data to from the serial interface SIO1 a 3 wire serial I O mode with automatic transmission reception function When the internal buffer RAM is not used in the 3 wire serial I O mode with automatic transmission reception function it is used as a conventional RAM 3 1 3 Special Function Register SFR area An on chip peripheral hardware special function register SFR is alloca...

Page 48: ...ar special addressing methods designed for the functions of special function registers SFR and general purpose registers are available for use Data memory addressing is illustrated in Figures 3 3 and 3 4 For the details of each addressing mode see 3 4 Operand Address Addressing Figure 3 3 Data Memory Addressing µPD780065 0000H General registers 32 8 bits Internal ROM 40960 8 bits External memory 1...

Page 49: ...FFH FEE0H FEDFH FF00H FEFFH FFFFH Internal high speed RAM 1024 8 bits FB00H FF20H FF1FH FE20H FE1FH Special function registers SFRs 256 8 bits SFR addressing Register addressing Short direct addressing Direct addressing Register indirect addressing Based addressing Based indexed addressing Reserved Internal buffer RAM 32 8 bits Reserved Internal expansion RAM 4096 8 bits E800H FAE0H FADFH FAC0H FA...

Page 50: ...er of bytes of the instruction to be fetched When a branch instruction is executed immediate data and register contents are set RESET input sets the reset vector table values at addresses 0000H and 0001H to the program counter Figure 3 5 Program Counter Format 15 0 PC PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 2 Program status word PSW The program status word is an 8 bit...

Page 51: ...lt has a carry from bit 3 or a borrow at bit 3 this flag is set 1 It is reset 0 in all other cases e In service priority flag ISP This flag manages the priority of acknowledgeable maskable vectored interrupts When this flag is 0 low level vectored interrupts request specified with a priority specify flag register PR0L PR0H PR1L refer to 17 3 3 Priority Specify Flag Register PR0L PR0H PR1L are disa...

Page 52: ...emory Interrupt and BRK Instructions PSW PC15 to PC8 PC15 to PC8 PC7 to PC0 Register pair lower SP SP _ 2 SP _ 2 Register pair upper CALL CALLF and CALLT Instructions PUSH rp Instruction SP _ 1 SP SP SP _ 2 SP _ 2 SP _ 1 SP PC7 to PC0 SP _ 3 SP _ 2 SP _ 1 SP SP SP _ 3 RETI and RETB Instructions PSW PC15 to PC8 PC15 to PC8 PC7 to PC0 Register pair lower SP SP 2 SP Register pair upper RET Instructio...

Page 53: ...C DE and HL and absolute names R0 to R7 and RP0 to RP3 Register banks to be used for instruction execution are set with the CPU control instruction SEL RBn Because of the 4 register bank configuration an efficient program can be created by switching between a register for normal processing and a register for interrupts for each bank Figure 3 10 General Register Configuration a Absolute name b Func...

Page 54: ... manipulation instruction operand sfr This manipulation can also be specified with an address 16 bit manipulation Describe the symbol reserved with assembler for the 16 bit manipulation instruction operand sfrp When addressing an address describe an even address Table 3 3 gives a list of special function registers The meaning of items in the table is as follows Symbol Symbol indicating the address...

Page 55: ...egister 50 CR50 R W Undefined FF11H 8 bit compare register 51 CR51 FF12H 8 bit counter 50 TM5 TM50 R 00H FF13H 8 bit counter 51 TM51 FF15H A D conversion result register ADCR0 FF17H Serial I O shift register 1 SIO1 R W Undefined FF18H Serial I O shift register 30 SIO30 FF19H Serial I O shift register 31 SIO31 FF1AH Transmit shift register TXS0 W FFH Receive buffer register RXB0 R FF20H Port mode r...

Page 56: ...register EGP FF49H External interrupt falling edge enable register EGN FF60H 16 bit timer mode control register TMC0 FF61H Prescaler mode register PRM0 FF62H Capture compare control register 0 CRC0 FF63H 16 bit timer output control register 0 TOC0 FF68H Serial operation mode register 1 CSIM1 FF69H Automatic data transmission reception ADTC0 control register FF6AH Automatic data transmission recept...

Page 57: ...pecification flag register 0L PR0 PR0L FFE9H Priority level specification flag register 0H PR0H FFEAH Priority level specification flag register 1L PR1L FFF0H Memory size switching register IMS CFHNote 2 FFF4H Internal expansion RAM size switching IXS 0CHNote 3 register FFF8H Memory expansion wait setting register MM 10H FFF9H Watchdog timer mode register WDTM 00H FFFAH Oscillation stabilization t...

Page 58: ...tive addressing Function The value obtained by adding 8 bit immediate data displacement value jdisp8 of an instruction code to the start address of the following instruction is transferred to the program counter PC and branched The displacement value is treated as signed two s complement data 128 to 127 and bit 7 becomes a sign bit In other words relative addressing consists in relative branching ...

Page 59: ...hen the CALL addr16 or BR addr16 or CALLF addr11 instruction is executed CALL addr16 and BR addr16 instructions can be branched to the entire memory space The CALLF addr11 instruction is branched to the 0800H to 0FFFH area Illustration In the case of CALL addr16 and BR addr16 instructions In the case of CALLF addr11 instruction 15 0 PC 8 7 7 0 CALL or BR Low Addr High Addr 15 0 PC 8 7 7 0 fa10 8 1...

Page 60: ...eration code are transferred to the program counter PC and branched This function is carried out when the CALLT addr5 instruction is executed This instruction references the address stored in the memory table from 40H to 7FH and allows branching to the entire memory space Illustration 15 1 15 0 PC 7 0 Low Addr High Addr Memory Table Effective address 1 Effective address 0 1 0 0 0 0 0 0 0 0 8 7 8 7...

Page 61: ...UM00 3 3 4 Register addressing Function Register pair AX contents to be specified with an instruction word are transferred to the program counter PC and branched This function is carried out when the BR AX instruction is executed Illustration 7 0 rp 0 7 A X 15 0 PC 8 7 ...

Page 62: ... Instruction Register to be Specified by Implied Addressing MULU A register for multiplicand and AX register for product storage DIVUW AX register for dividend and quotient storage ADJBA ADJBS A register for storage of numeric values which become decimal correction targets ROR4 ROL4 A register for storage of digit data which undergoes digit rotation Operand format Because implied addressing can be...

Page 63: ...ion with the following operand format is executed When an 8 bit register is specified one of the eight registers is specified with 3 bits in the operation code Operand format Identifier Description r X A C B E D L H rp AX BC DE HL r and rp can be described with absolute names R0 to R7 and RP0 to RP3 as well as function names X A C B E D L H AX BC DE and HL Description example MOV A C when selectin...

Page 64: ...d with immediate data in an instruction word becoming an operand address Operand format Identifier Description addr16 Label or 16 bit immediate data Description example MOV A 0FE00H when setting addr16 to FE00H Operation code 1 0 0 0 1 1 1 0 OP code 0 0 0 0 0 0 0 0 00H 1 1 1 1 1 1 1 0 FEH Illustration Memory 0 7 addr16 lower addr16 upper OP code ...

Page 65: ...rea FF00H to FF1FH where short direct addressing is applied ports which are frequently accessed in a program and a compare register of the timer event counter and a capture register of the timer event counter are mapped and these SFRs can be manipulated with a small number of bytes and clocks When 8 bit immediate data is at 20H to FFH bit 8 of an effective address is set to 0 When it is at 00H to ...

Page 66: ...o FE30H and immediate data to 50H Operation code 0 0 0 1 0 0 0 1 OP code 0 0 1 1 0 0 0 0 30H saddr offset 0 1 0 1 0 0 0 0 50H immediate data Illustration When 8 bit immediate data is 20H to FFH α 0 When 8 bit immediate data is 00H to 1FH α 1 15 0 Short Direct Memory Effective Address 1 1 1 1 1 1 1 8 7 0 7 OP code saddr offset α ...

Page 67: ...ces FF00H to FFCFH and FFE0H to FFFFH However the SFR mapped at FF00H to FF1FH can be accessed with short direct addressing Operand format Identifier Description sfr Special function register name sfrp 16 bit manipulatable special function register name even address only Description example MOV PM0 A when selecting PM0 FF20H as sfr Operation code 1 1 1 1 0 1 1 0 OP code 0 0 1 0 0 0 0 0 20H sfr off...

Page 68: ...ank select flag RBS0 and RBS1 serve as an operand address for addressing the memory to be manipulated This addressing can be carried out for all the memory spaces Operand format Identifier Description DE HL Description example MOV A DE when selecting DE as register pair Operation code 1 0 0 0 0 1 0 1 Illustration 16 0 8 D 7 E 0 7 7 0 A DE The contents of the memory addressed are transferred Memory...

Page 69: ...register bank specified with the register bank select flag RBS0 and RBS1 and the sum is used to address the memory Addition is performed by expanding the offset data as a positive number to 16 bits A carry from the 16th bit is ignored This addressing can be carried out for all the memory spaces Operand format Identifier Description HL byte Description example MOV A HL 10H when setting byte to 10H ...

Page 70: ...its A carry from the 16th bit is ignored This addressing can be carried out for all the memory spaces Operand format Identifier Description HL B HL C Description example In the case of MOV A HL B Operation code 1 0 1 0 1 0 1 1 3 4 9 Stack addressing Function The stack area is indirectly addressed with the stack pointer SP contents This addressing method is automatically employed when the PUSH POP ...

Page 71: ...the port configuration Every port is capable of 1 bit and 8 bit manipulations and can carry out considerably varied control operations Besides port functions the ports can also serve as on chip hardware input output pins Figure 4 1 Port Types Port 0 P00 Port 2 P20 P27 Port 3 P30 P37 Port 6 Port 5 P50 P57 P64 P67 Port 7 P70 P77 Port 4 P40 P47 P07 Port 8 P80 P84 Port 9 P90 P92 ...

Page 72: ...ut mode can be specified in 1 bit units An on chip pull up resistor can be specified by means of software Port 3 8 bit input output port Input output mode can be specified in 1 bit units An on chip pull up resistor can be specified by means of software Port 4 8 bit input output port Input output mode can be specified in 1 bit units An on chip pull up resistor can be specified by means of software ...

Page 73: ... output mode can be specified for pins P00 to P07 in 1 bit units with port mode register 0 PM0 For pins P00 to P07 an on chip pull up resistor can be specified in 6 bit units with pull up resistor option register 0 PU0 This port can also be used as an external interrupt request input RESET input sets port 0 to input mode Figure 4 2 shows a block diagram of port 0 Caution Because port 0 also serves...

Page 74: ...ure 4 2 Block Diagram of P00 to P07 PU Pull up resistor option register PM Port mode register RD Port 0 read signal WR Port 0 write signal RD P00 INTP0 to P03 INTP3 P04 to P07 P ch WRPU WRPORT WRPM PU00 to PU07 Output latch P00 to P07 PM00 to PM07 Selector VDD0 Internal bus ...

Page 75: ... bit units with pull up resistor option register 2 PU2 This port can also be used as the timer input output RESET input sets port 2 to input mode Figure 4 3 shows a block diagram of port 2 Figure 4 3 Block Diagram of P20 to P27 PU Pull up resistor option register PM Port mode register RD Port 2 read signal WR Port 2 write signal RD P20 TI00 TO0 P21 TI01 P22 TI50 TO50 P23 TI51 TO51 P24 to P27 P ch ...

Page 76: ...s P30 to P37 an on chip pull up resistor can be specified in 1 bit units with pull up resistor option register 3 PU3 RESET input sets port 3 to input mode Figure 4 4 shows a block diagram of port 3 Figure 4 4 Block Diagram of P30 to P37 PU Pull up resistor option register PM Port mode register RD Port 3 read signal WR Port 3 write signal RD P30 to P37 P ch WRPU WRPORT WRPM PU30 to PU37 Output latc...

Page 77: ...cified in 1 bit units with pull up resistor option register 4 PU4 This port can also be used as an address data bus in external memory expansion mode RESET input sets port 4 to input mode Figure 4 5 shows a block diagram of port 4 Figure 4 5 Block Diagram of P40 to P47 PUO Pull up resistor option register PM Port mode register RD Port 4 read signal WR Port 4 write signal RD P40 AD0 to P47 AD7 P ch...

Page 78: ...n be specified in 1 bit units with pull up resistor option register 5 PU5 This port can also be used as an address bus in external memory expansion mode RESET input sets port 5 to input mode Figure 4 6 shows a block diagram of port 5 Figure 4 6 Block Diagram of P50 to P57 PU Pull up resistor option register PM Port mode register RD Port 5 read signal WR Port 5 write signal RD P50 A8 to P57 A15 P c...

Page 79: ... PU6 This port can also be used as a control signal output in external memory expansion mode RESET input sets port 6 to input mode Figure 4 7 shows a block diagram of port 6 Caution When external wait is not used in external memory expansion mode P66 can be used as an input output port Figure 4 7 Block Diagram of P64 to P67 PU Pull up resistor option register PM Port mode register RD Port 6 read s...

Page 80: ...tor option register 7 PU7 This port can also be used as the serial interface serial data input output serial clock input output and clock output RESET input sets the input mode Figures 4 8 and 4 9 show block diagrams of port 7 Figure 4 8 Block Diagram of P70 to P75 PU Pull up resistor option register PM Port mode register RD Port 7 read signal WR Port 7 write signal RD P70 PCL P71 ASCK0 P72 TxD0 P...

Page 81: ...3420EJ2V0UM00 Figure 4 9 Block Diagram of P76 and P77 PU Pull up resistor option register PM Port mode register RD Port 7 read signal WR Port 7 write signal RD P76 P77 P ch WRPU WRPORT WRPM PU76 PU77 Output latch P76 P77 PM76 PM77 Selector VDD0 Internal bus ...

Page 82: ...gister 8 PU8 This port can also be used as the serial interface serial data input output serial clock input output automatic transmission reception busy input and strobe output RESET input sets the input mode Figure 4 10 shows a block diagram of port 8 Figure 4 10 Block Diagram of P80 to P84 PU Pull up resistor option register PM Port mode register RD Port 8 read signal WR Port 8 write signal RD P...

Page 83: ...ts with pull up resistor option register 9 PU9 This port can also be used as the serial interface serial data input output and serial clock input output RESET input sets the input mode Figure 4 11 shows a block diagram of port 9 Figure 4 11 Block Diagram of P90 to P92 PU Pull up resistor option register PM Port mode register RD Port 9 read signal WR Port 9 write signal RD P90 SCK31 P91 SO31 P92 SI...

Page 84: ...PM9 These registers are used to set port input output in 1 bit units PM0 and PM2 to PM9 are independently set with a 1 bit or 8 bit memory manipulation instruction RESET input sets registers to FFH Caution As port 0 has an alternate function as an external interrupt input when the port function output mode is specified and the output level is changed the interrupt request flag is set When the outp...

Page 85: ... R W Symbol 7 6 5 4 3 2 1 0 PM4 PM47 PM46 PM45 PM44 PM43 PM42 PM41 PM40 Address FF25H After Reset FFH R W Symbol 7 6 5 4 3 2 1 0 PM5 PM57 PM56 PM55 PM54 PM53 PM52 PM51 PM50 Address FF26H After Reset FFH R W Symbol 7 6 5 4 3 2 1 0 PM6 PM67 PM66 PM65 PM64 1 1 1 1 Address FF27H After Reset FFH R W Symbol 7 6 5 4 3 2 1 0 PM7 PM77 PM76 PM75 PM74 PM73 PM72 PM71 PM70 Address FF28H After Reset FFH R W Sym...

Page 86: ...t An on chip pull up resistor for each port pin can be specified by setting PU0 and PU2 to PU9 PU0 and PU2 to PU9 are set with a 1 bit or 8 bit memory manipulation instruction RESET input sets this register to 00H Caution When an on chip pull up resistor is used even if output mode is set the pull up resistor will not be cut off To use in output mode set the corresponding pull up resistor option r...

Page 87: ... R W Symbol 7 6 5 4 3 2 1 0 PU4 PU47 PU46 PU45 PU44 PU43 PU42 PU41 PU40 Address FF35H After Reset 00H R W Symbol 7 6 5 4 3 2 1 0 PU5 PU57 PU56 PU55 PU54 PU53 PU52 PU51 PU50 Address FF36H After Reset 00H R W Symbol 7 6 5 4 3 2 1 0 PU6 PU67 PU66 PU65 PU64 0 0 0 0 Address FF37H After Reset 00H R W Symbol 7 6 5 4 3 2 1 0 PU7 PU77 PU76 PU75 PU74 PU73 PU72 PU71 PU70 Address FF38H After Reset 00H R W Sym...

Page 88: ...tput pins the output latch contents for pins specified as input are undefined except for the manipulated bit 4 4 2 Reading from input output port 1 Output mode The output latch contents are read by a transfer instruction The output latch contents do not change 2 Input mode The pin status is read by a transfer instruction The output latch contents do not change 4 4 3 Operations on input output port...

Page 89: ...he processor clock control register PCC 2 Subsystem clock oscillator The circuit oscillates at a frequency of 32 768 kHz Oscillation cannot be stopped If the subsystem clock oscillator is not used the internal feedback resistor can be disabled by the processor clock control register PCC This enables to reduce the power dissipation in the STOP mode 5 2 Clock Generator Configuration The clock genera...

Page 90: ...XT X1 X2 Main system clock oscillator fX Prescaler fX 2 fX 22 fX 23 fX 24 fXT 2 1 2 Prescaler Watch timer clock output function Clock to peripheral hardware CPU clock fCPU Standby control circuit Wait control circuit To INTP0 sampling clock 3 STOP MCC FRC CLS CSS PCC2 PCC1 PCC0 Processor clock control register PCC Internal bus Selector XT1 XT2 ...

Page 91: ...trol register PCC The PCC sets whether to use CPU clock selection the ratio of division main system clock oscillator operation stop and subsystem clock oscillator internal feedback resistor The PCC is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets the PCC to 04H Figure 5 2 Subsystem Clock Feedback Resistor FRC P ch Feedback resistor XT1 XT2 ...

Page 92: ... status 0 Main system clock 1 Subsystem clock CSS PCC2 PCC1 PCC0 CPU clock fCPU select 0 0 0 0 fX 0 0 1 fX 2 0 1 0 fX 22 0 1 1 fX 23 1 0 0 fX 24 1 0 0 0 fXT 2 0 0 1 0 1 0 0 1 1 1 0 0 Other than above Setting prohibited Notes 1 Bit 5 is Read Only 2 When the CPU is operating on the subsystem clock MCC should be used to stop the main system clock oscillation A STOP instruction should not be used Caut...

Page 93: ...llator oscillates with a crystal resonator or a ceramic resonator standard 8 38 MHz connected to the X1 and X2 pins External clocks can be input to the main system clock oscillator In this case input a clock signal to the X1 pin and an inverted phase clock signal to the X2 pin Figure 5 4 shows an external circuit of the main system clock oscillator Figure 5 4 External Circuit of Main System Clock ...

Page 94: ...ternal clocks can be input to the main system clock oscillator In this case input a clock signal to the XT1 pin and an inverted phase clock signal to the XT2 pin Figure 5 5 shows an external circuit of the subsystem clock oscillator Figure 5 5 External Circuit of Subsystem Clock Oscillator a Crystal oscillation b External clock Cautions are listed on the next page XT2 XT1 32 768 kHz XT1 XT2 PD74HC...

Page 95: ...apacitor of the oscillation circuit at the same potential as VSS1 Do not ground a capacitor to a ground pattern where high current flows Do not fetch signals from the oscillator Take special note of the fact that the subsystem clock oscillator is a circuit with low level amplification so that current consumption is maintained at low levels Figure 5 6 shows examples of incorrect oscillator connecti...

Page 96: ...0 High current High current VSS1 VSS1 IC X1 X2 VSS1 e Signals are fetched Remark When using a subsystem clock replace X1 and X2 with XT1 and XT2 respectively Also insert resistors in series on the XT2 side Cautions 2 When X2 and XT1 are wired in parallel the cross talk noise of X2 may increase with XT1 resulting in malfunctioning To prevent that from occurring it is recommended to wire X2 and XT1 ...

Page 97: ... power consumption operations and clock operations connect the XT1 and XT2 pins as follows XT1 Connect to VDD0 XT2 Open In this state however some current may leak via the internal feedback resistor of the subsystem clock oscillator when the main system clock stops To minimize leakage current the above internal feedback resistor can be removed with bit 6 FRC of the processor clock control register...

Page 98: ... With the main system clock selected two standby modes the STOP and HALT modes are available To reduce current consumption in the STOP mode the subsystem clock feedback resistor can be disconnected to stop the subsystem clock d The PCC can be used to select the subsystem clock and to operate the system with low current consumption 122 µs 32 768 kHz operation e With the subsystem clock selected mai...

Page 99: ...t 7 MCC of the PCC is set to 1 when operated with the main system clock the main system clock oscillation does not stop When bit 4 CSS of the PCC is set to 1 and the operation is switched to subsystem clock operation CLS 1 after that the main system clock oscillation stops see Figure 5 7 Figure 5 7 Main System Clock Stop Function 1 2 a Operation when MCC is set after setting CSS with main system c...

Page 100: ...Caution Do not execute the STOP instruction while the subsystem clock is in operation 5 6 Changing System Clock and CPU Clock Settings 5 6 1 Time required for switchover between system clock and CPU clock The system clock and CPU clock can be switched over by means of bits 0 to 2 PCC0 to PCC2 and bit 4 CSS of the processor clock control register PCC The actual switchover operation is not performed...

Page 101: ...ction 20 instructions 0 1 1 2 instructions 2 instructions 2 instructions 2 instructions fX 16fXT instruction 10 instructions 1 0 0 1 instruction 1 instruction 1 instruction 1 instruction fX 32fXT instruction 5 instructions 1 1 instruction 1 instruction 1 instruction 1 instruction 1 instruction Remarks 1 One instruction is the minimum instruction execution time with the pre switchover CPU clock 2 F...

Page 102: ...eds the PCC is rewritten and maximum speed operation is carried out 3 Upon detection of a decrease of the VDD voltage due to an interrupt request signal the main system clock is switched to the subsystem clock which must be in an oscillation stable state 4 Upon detection of VDD voltage reset due to an interrupt 0 is set to the MCC and oscillation of the main system clock is started After the lapse...

Page 103: ...timer an external event counter to output square wave output with any selected frequency and PWM output Two 8 bit timer event counters can be used as one 16 bit timer event counter See CHAPTER 7 8 BIT TIMER EVENT COUNTER 3 Watch timer WT This timer can set a flag every 0 5 sec or 0 25 sec and simultaneously generate an interrupt request at the preset time intervals See CHAPTER 8 WATCH TIMER 4 Watc...

Page 104: ... output Pulse width measurement Square wave output One shot pulse output Interrupt request Notes 1 The watch timer can perform both watch timer and interval timer functions at the same time 2 WDTM can perform either the watchdog timer function or the interval timer function 6 2 16 Bit Timer Event Counter Functions The 16 bit timer event counter has the following functions Interval timer PPG output...

Page 105: ...ed frequency 6 One shot pulse output TM0 is able to output one shot pulse which can set any width of output pulse Internal bus Capture compare control register 0 CRC0 TI01 P21 fX fX 22 fX 26 fX 23 TI00 TO0 P20 Prescaler mode register 0 PRM0 2 PRM01PRM00 CRC02 16 bit timer capture compare register 01 CR01 Coincidence Coincidence 16 bit timer counter 0 TM0 Clear Noise elimi nation circuit CRC02 CRC0...

Page 106: ...M0 Port mode register 2 PM2 Note Note See Block Diagram of Figure 4 3 P20 to P27 1 16 bit timer counter 0 TM0 TM0 is a 16 bit read only register that counts count pulses The counter is incremented in synchronization with the rising edge of an input clock If the count value is read during operation input of the count clock is temporarily stopped and the count value at that point is read The count v...

Page 107: ...re trigger is specified to be the valid edge of the TI01 P21 pin the situation is as shown in Table 6 4 Table 6 3 TI00 TO0 P20 Pin Valid Edge and Capture Compare Register Capture Trigger ES01 ES00 TI00 TO0 P20 Pin Valid Edge CR00 Capture Trigger CR01 Capture Trigger 0 0 Falling edge Rising edge Rising edge 0 1 Rising edge Falling edge Falling edge 1 0 Setting prohibited Setting prohibited Setting ...

Page 108: ...et other than 0000H to CR01 This means 1 pulse count operation cannot be performed when CR01 is used as the event counter However in the free running mode and in the clear mode using the valid edge of TI00 if 0000H is set to CR01 an interrupt request INTTM01 is generated following overflow FFFFH 6 4 Registers to Control 16 Bit Timer Event Counter The following five types of registers are used to c...

Page 109: ...01 1 1 1 Match between TM0 and CR00 match between TM0 and CR01 or TI00 valid edge OVF0 TM0 overflow detection 0 Overflow not detected 1 Overflow detected Cautions 1 Timer operation must be stopped before writing to bits other than the OVF0 flag 2 Set the valid edge of the TI00 TO0 P20 pin with prescaler mode register 0 PRM0 3 If clear start mode on match between TM0 and CR00 is selected when the s...

Page 110: ...CRC02 CR01 operating mode selection 0 Operates as compare register 1 Operates as capture register CRC01 CR00 capture trigger selection 0 Captures on valid edge of TI01 1 Captures on valid edge of TI00 by reverse phase CRC00 CR00n operating mode selection 0 Operates as compare register 1 Operates as capture register Cautions 1 Timer operation must be stopped before setting CRC0 2 When clear start m...

Page 111: ... by software 0 One shot pulse trigger not used 1 One shot pulse trigger used OSPE One shot pulse output control 0 Continuous pulse output 1 One shot pulse outputNote TOC04 Timer output F F control by match of CR01 and TM0 0 Inversion operation disabled 1 Inversion operation enabled LVS0 LVR0 16 bit timer event counter timer output F F status setting 0 0 No change 0 1 Timer output F F reset 0 1 0 T...

Page 112: ...M00 Count clock selection 0 0 fX 8 38 MHz 0 1 fX 22 2 09 MHz 1 0 fX 26 131 kHz 1 1 TI00 valid edgeNote Note The external clock needs a pulse more than twice the length of the internal clock fX 23 Cautions 1 If the valid edge of TI00 is to be set to the count clock do not set the clear start mode and the capture trigger at the valid edge of TI00 Moreover do not use the P20 TI00 TO0 pins as timer ou...

Page 113: ... output set PM20 and the output latch of P20 to 0 PM2 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets PM7 value to FFH Figure 6 6 Format of Port Mode Register 2 PM2 7 PM27 6 PM26 5 PM25 4 PM24 3 PM23 2 PM22 1 PM21 0 PM20 Symbol PM2 Address FF22H After reset FFH R W PM2n 0 1 P2n pin input output mode selection n 0 to 7 Output mode output buffer ON Input mode output buf...

Page 114: ...interrupt request signal INTTM00 is generated Count clock of the 16 bit timer event counter can be selected with bits 0 to 1 PRM00 PRM01 of prescaler mode register 0 PRM0 See 6 6 16 Bit Timer Event Counter Operating Precautions 2 16 bit Compare Register Setting about the operation when the compare register value is changed during timer count operation Figure 6 7 Control Register Settings for Inter...

Page 115: ...N 00H to FFH 16 bit timer capture compare register 00 CR00 16 bit timer counter 0 TM0 OVF0 Clear circuit Noise elimination circuit INTTM00 fX fX 22 fX 26 fX 23 TI00 TO0 P20 Selector Count clock t TM0 count value CR00 INTTM00 TO0 0000H 0001H N 0000H 0001H N 0000H 0001H N N N N N Count start Clear Clear Interrupt request acknowledged Interrupt request acknowledged Interval time Interval time Interva...

Page 116: ...peration a 16 bit timer mode control register 0 TMC0 b Capture compare control register 0 CRC0 c 16 bit timer output control register 0 TOC0 Cautions 1 Values in the following range should be set in CR00 and CR01 0000H CR01 CR00 FFFFH 2 The cycle of the pulse generated through PPG output CR00 setting value 1 has a duty of CR01 setting value 1 CR00 setting value 1 Remark don t care 0 0 0 0 TMC03 1 ...

Page 117: ... TM0 is taken into 16 bit timer capture compare register 01 CR01 and an external interrupt request signal INTTM01 is set Any of three edges can be selected rising falling or both edges specified by means of bits 6 and 7 ES10 and ES11 of PRM0 For valid edge detection sampling is performed at the count clock selected by PRM0 and a capture operation is only performed when a valid level is detected tw...

Page 118: ...th Measurement Operation by Free Running Counter and One Capture Register with Both Edges Specified fX fX 22 fX 26 TI00 TO0 P20 16 bit timer counter 0 TM0 OVF0 16 bit timer capture compare register 01 CR01 Internal bus INTTM01 Selector t 0000H 0000H FFFFH 0001H D0 D0 Count clock TM0 count value TI00 pin input CR01 capture value INTTM01 OVF0 D1 D0 t D3 D2 t 10000H D1 D2 t D1 D2 D3 D2 D3 D0 1 D1 D1 ...

Page 119: ...ny of three edges can be selected rising falling or both edges as the valid edges for the TI00 TO0 P20 pin and the TI01 P21 pin specified by means of bits 4 and 5 ES00 and ES01 and bits 6 and 7 ES10 and ES11 of INTM0 respectively For TI00 TO0 P20 pin valid edges detection sampling is performed at the interval selected by means of the prescaler mode register 0 PRM0 and a capture operation is only p...

Page 120: ...ecified Figure 6 16 Timing of Pulse Width Measurement Operation with Free Running Counter with Both Edges Specified Count clock TM0 TI00 Rising edge detection CR01 INTTM01 n 3 n 2 n 1 n n 1 n t 0000H 0000H FFFFH 0001H D0 D0 TI01 pin input CR00 capture value INTTM01 INTTM00 OVF0 D1 D0 t D3 D2 t 10000H D1 D2 t 10000H D1 D2 1 t D1 D2 1 D1 D2 D2 D3 D0 1 D1 D1 1 D2 1 D2 2 Count clock TM0 count value TI...

Page 121: ... bits 4 and 5 ES00 and ES01 of prescaler mode register 0 PRM0 For TI00 TO0 P20 pin valid edge detection sampling is performed at the interval selected by means of the prescaler mode register PRM0 and a capture operation is only performed when a valid level is detected twice thus eliminating noise with a short pulse width Caution If the valid edge of TI00 TO0 P20 is specified to be both rising and ...

Page 122: ...ettings in Figure 6 19 The edge specification can be selected from two types rising and falling edges by bits 4 and 5 ES00 and ES01 of the prescaler mode resister 0 PRM0 In a valid edge detection the sampling is performed by a cycle selected by the prescaler mode resistor 0 PRM0 and a capture operation is only performed when a valid level is detected twice thus eliminating noise with a short pulse...

Page 123: ...th measurement See Figures 6 2 and 6 3 Figure 6 20 Timing of Pulse Width Measurement Operation by Means of Restart with Rising Edge Specified 0 0 0 0 TMC03 1 TMC02 0 TMC01 0 1 OVF0 0 TMC0 Clears and starts at valid edge of TI00 TO0 P20 pin 0 0 0 0 0 CRC02 1 CRC01 1 CRC00 1 CRC0 CR00 as capture register Captures to CR00 at edge reverse to valid edge of TI00 TO0 P20 CR01 as capture register t 0000H ...

Page 124: ... the falling edge or both edges can be selected with bits 4 and 5 ES00 and ES01 of prescaler mode register 0 PRM0 Because operation is carried out only after the valid edge is detected twice by sampling at internal clock fX 23 noise with short pulse widths can be removed Caution When used as an external event counter the P20 TI00 TO0 pin cannot be used as timer output TO0 Figure 6 21 Control Regis...

Page 125: ...peration A square wave with any selected frequency to be output at intervals of the count value preset to 16 bit timer capture compare register 00 CR00 operates The TO0 pin output status is reversed at intervals of the count value preset to CR00 by setting bit 0 TOE0 and bit 1 TOC01 of the 16 bit timer output control register 0 TOC0 to 1 This enables a square wave with any selected frequency to be...

Page 126: ... function to be used simultaneously with square wave output See Figures 6 2 6 3 and 6 4 0 0 0 0 TMC03 1 TMC02 1 TMC01 0 1 OVF0 0 TMC0 Clears and starts on coincidence between TM0 and CR00 0 0 0 0 0 CRC02 0 1 CRC01 0 1 CRC00 0 CRC0 CR00 as compare register 0 OSPT 0 OSPE 0 TOC04 0 LVS0 0 1 LVR0 0 1 TOC01 1 TOE0 1 TOC0 Enables TO0 output Reverses output on coincidence between TM0 and CR00 Specifies i...

Page 127: ...0 TI00 P20 pin By setting 1 in OSPT 16 bit timer counter 0 TM0 is cleared and started and output is activated by the count value set beforehand in 16 bit timer capture compare register 01 CR01 Thereafter output is inactivated by the count value set beforehand in 16 bit timer capture compare register 00 CR00 TM0 continues to operate after one shot pulse is output To stop TM0 00H must be set to TMC0...

Page 128: ...00H CR01 CR00 FFFFH Remark 0 1 Setting 0 or 1 allows another function to be used simultaneously with one shot pulse output See Figures 6 2 6 3 and 6 4 0 0 0 0 TMC03 0 TMC02 1 TMC01 0 1 OVF0 0 TMC0 Free running mode 0 0 0 0 0 CRC02 0 CRC01 0 1 CRC00 0 CRC0 CR00 as compare register CR01 as compare register 0 OSPT 0 OSPE 1 TOC04 1 LVS0 0 1 LVR0 0 1 TOC01 1 TOE0 1 TOC0 Enables TO0 output Reverses outp...

Page 129: ...re Trigger Caution The 16 bit timer counter 0 TM0 starts operation at the moment a value other than 0 0 operation stop mode is set to TMC02 and TMC03 respectively Sets 0CH to TMC0 TM0 count starts Count clock TM0 count value CR01 set value CR00 set value OSPT INTTM01 INTTM00 TO0 pin output 0000H 0001H N N 1 0000H N 1 N M 1 M M 1 M 2 N M N M N M N M ...

Page 130: ... CR00 CR01 This means 1 pulse count operation cannot be performed when it is used as the event counter 3 Operation after compare register change during timer count operation If the value after 16 bit timer capture compare register 00 CR00 is changed is smaller than that of 16 bit timer counter 0 TM0 TM0 continues counting overflows and then restarts counting from 0 Thus if the value M after CR00 c...

Page 131: ...alid edge setting Set the valid edge of the TI00 TO0 P20 pin after setting bits 2 and 3 TMC02 and TMC03 of 16 bit timer mode control register 0 TMC0 to 0 0 respectively and then stopping timer operation Valid edge is set with bits 4 and 5 ES00 and ES01 of the prescaler mode register 0 PRM0 6 Re trigger of one shot pulse When outputting one shot pulse do not set 1 in OSPT When outputting one shot p...

Page 132: ...ger input is prior to the other The data read from CR00 CR01 is not defined 2 The coincidence timing of contending operation between the write period of 16 bit timer capture compare register CR00 CR01 and 16 bit timer counter 0 TM0 CR00 CR01 used as a compare register The coincidence discriminant is not performed normally Do not write any data to CR00 CR01 near the coincidence timing 9 Timer opera...

Page 133: ...et in compare mode even if a capture trigger has been input 12 Edge detection 1 To secure capture of the capture trigger a pulse more than twice the length of the count clock to be selected is required When TI00 is high level just after system reset the falling edge is detected just after the TM0 operation is permitted Be aware of this if using pull up resistors 2 The sampling clock for noise elim...

Page 134: ...134 Preliminary User s Manual U13420EJ2V0UM00 MEMO ...

Page 135: ...bit timer event counters alone individual mode The timer operates as an 8 bit timer event counter It has the following functions Interval timer External event counter Square wave output PWM output 2 Mode using the cascade connection 16 bit resolution cascade connection mode The timer operates as a 16 bit timer event counter by connecting in cascade It has the following functions Interval timer wit...

Page 136: ...0 Internal bus TCE50 TMC506 TMC504 LVS50 LVR50 TMC501 TOE50 Invert level Timer mode control register 50 TMC50 S R S Q R INV Selector INTTM50 TO50 TI50 P22 Selector 8 bit counter 50 TM50 Selector Internal bus TI51 TO51 P23 fX 23 fX 25 fX 27 fX 29 fX 2 Coincidence Mask circuit OVF Clear 3 TCL512 TCL511 TCL510 Timer clock selection register 51 TCL51 Internal bus TCE51 TMC516 TMC514 LVS51 LVR51 TMC511...

Page 137: ...hem in two times reading When count value is read during operation count clock input is temporary stopped and then the count value is read In the following situations count value is set to 00H 1 RESET input 2 When TCE5n is cleared 3 When TM5n and CR5n match in clear start mode if this mode was entered upon match of TM5n and CR5n values Caution In cascade connection mode the count value is reset to...

Page 138: ...struction RESET input sets to 00H Figure 7 3 Format of Timer Clock Select Register 50 TCL50 Address FF71H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 TCL50 0 0 0 0 0 TCL502 TCL501 TCL500 TCL502 TCL501 TCL500 Count clock selection 0 0 0 TI50 Falling edge 0 0 1 TI50 Rising edge 0 1 0 fX 8 38 MHz 0 1 1 fX 22 2 09 MHz 1 0 0 fX 24 523 kHz 1 0 1 fX 26 131 kHz 1 1 0 fX 28 32 7 kHz 1 1 1 fX 210 8 18 kHz Ca...

Page 139: ...1 When cascade connection is used the settings of TCL5n0 to TCL5n2 n 0 1 are valid only for the lowermost timer 2 fX Main system clock oscillation frequency 3 Figures in parentheses are for operation with fX 8 38 MHz 2 8 bit Timer Mode Control Register 5n TMC5n n 0 1 TMC5n is a register which sets up the following six types 1 8 bit counter 5n TM5n count operation control 2 8 bit counter 5n TM5n op...

Page 140: ...d CR5n 1 PWM Free running mode TMC5n4 Single mode cascade connection mode selection 0 Single mode use the lowest timer 1 Cascade connection mode connect to lower timer LVS5n LVR5n Timer output F F status setting 0 0 No change 0 1 Timer output F F reset 0 1 0 Timer output F F set 1 1 1 Setting prohibited TMC5n1 In other modes TMC5n6 0 In PWM mode TMC5n6 1 Timer F F control Active level selection 0 ...

Page 141: ...r timer output set PM22 PM23 and output latches of P22 and P23 to 0 PM2 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets PM2 to FFH Figure 7 6 Format of Port Mode Register 2 PM2 Address FF22H After reset FFH R W Symbol 7 6 5 4 3 2 1 0 PM2 PM27 PM26 PM25 PM24 PM23 PM22 PM21 PM20 PM2n P2n pin input output mode selection n 0 to 7 0 Output mode output buffer ON 1 Input mod...

Page 142: ...lock of TM5n can be selected with bits 0 to 2 TCL5n0 to TCL5n2 of timer clock select register 5n TCL5n See 7 5 8 bit Timer Event Counter Caution 2 Operation after compare register change during timer count operation about the operation when the compare register value is changed during timer count operation Setting 1 Set the registers TCL5n Select count clock CR5n Compare value TMC5n Clear and Star...

Page 143: ...er Operation Timings 1 3 a Basic operation Remarks 1 Interval time N 1 t N 00H to FFH 2 n 0 1 t Count clock TM5n count value CR5n TCE5n INTTM5n TO5n Start count Clear Clear 00H 01H N 00H 01H N 00H 01H N N N N N Interrupt request received Interrupt request received Interval time Interval time Interval time ...

Page 144: ...erval Timer Operation Timings 2 3 b When CR5n 00H c When CR5n FFH n 0 1 t Count clock TM5 CR5n TCE5n INTTM5n TO5n Interval time 00H 00H 00H 00H 00H t Count clock TM5n CR5n TCE5n INTTM5n TO5n 01H FEH FFH 00H FEH FFH 00H FFH FFH FFH Interval time Interrupt request received Interrupt request received ...

Page 145: ...Timer Operation Timings 3 3 d Operated by CR5n transition M N e Operated by CR5n transition M N n 0 1 Count clock TM5 CR5n TCE5n INTTM5n TO5n 00H N N M N FFH 00H M 00H M CR5n transition TM5n overflows since M N H Count clock TM5 CR5n TCE5n INTTM5n TO5n N 1 N N 00H 01H N M 1 M 00H 01H M CR5n transition H ...

Page 146: ...timer clock select register 5n TCL5n is input Either the rising or falling edge can be selected When TM5n counted values match the values of 8 bit compare register 5n CR5n TM5n is cleared to 0 and the interrupt request signal INTTM5n are generated Whenever the TM5n counted value matches the value of CR5n INTTM5n is generated Remark n 0 1 Figure 7 8 External Event Counter Operation Timings with Ris...

Page 147: ...Select count clock CR5n Compared value TMC5n Clear and Start mode by match of TM5n and CR5n LVS5n LVR5n Timer output F F status setting 1 0 High level output 0 1 Low level output Timer output F F reverse enable Timer output enable TOE5n 1 2 After TCE5n 1 is set count operation starts 3 Timer output F F is reversed by match of TM5n and CR5n After INTTM5n is generated TM5n is cleared to 00H 4 Timer ...

Page 148: ...eration Setting 1 Set port latch P72 73 and port mode register 7 PM72 PM73 to 0 2 Set active level width with 8 bit compare register CR5n 3 Select count clock with timer clock select register 5n TCL5n 4 Set active level with bit 1 of TMC5n TMC5n1 5 Count operation starts when bit 7 of TMC5n is set to 1 Set TCE5n to 0 to stop count operation PWM output operation 1 PWM output output from TO5n output...

Page 149: ...CE5n INTTM5n TO5n 00H 01H FFH 00H 01H 02H N N 1 FFH 00H 01H 02H M 00H N Active level Active level Inactive level Count clock TM5n CR5n TCE5n INTTM5n TO5n L Inactive level Inactive level 01H 00H FFH 00H 01H 02H N N 1 FFH 00H 01H 02H M 00H 00H N 2 TM5n CR5n TCE5n INTTM5n TO5n 01H 00H FFH 00H 01H 02H N N 1 FFH 00H 01H 02H M 00H FFH N 2 Inactive level Active level Inactive level Active level Inactive ...

Page 150: ...n value transits from N to M between two clocks 00H and 01H after overflow of TM5n n 0 1 Count clock TM5n CR5n TCE5n INTTM5n TO5n CR5n transition N M N N 1 N 2 FFH 00H 01H M M 1 M 2 FFH 00H 01H 02H M M 1 M 2 N 02H M H Count clock TM5n CR5n TCE5n INTTM5n TO5n N N 1 N 2 FFH 00H 01H N N 1 N 2 FFH 00H 01H 02H N 02H N H 03H M M M 1 M 2 CR5n transition N M Count clock TM5n CR5n TCE5n INTTM5n TO5n N N 1 ...

Page 151: ...ear start mode by match of TM50 and CR50 TM51 and CR51 TM50 TMC50 0000 0B don t care TM51 TMC51 0001 0B don t care 2 When TMC51 is set to TCE51 1 and then TCE50 is set to TCE50 1 count operation starts 3 When the values of TM50 and CR50 of cascade connected timer match INTTM50 of TM50 is generated TM50 and TM51 are cleared to 00H 4 INTTM50 generates repeatedly at the same interval Cautions 1 Stop ...

Page 152: ...signal to be generated after timer start This is because 8 bit counter 5n TM5n is started asynchronously with the count pulse Figure 7 13 8 Bit Counter Start Timing n 0 1 Count clock TM50 TM51 CR50 CR51 TCE50 TCE51 INTTM50 TO50 Operation permit Count start Interval time 00H 01H N N 1 FFH 00H FFH 00H FFH 00H 01H N 00H 01H A 00H 00H 01H 02H M 1 M 00H B 00H N M Interrupt request generation Level reve...

Page 153: ...to restart the timer after transiting CR5n Figure 7 14 Timing after Compare Register Transition during Timer Count Operation Caution Except when the TI5n input is selected always set TCE5n 0 before setting the stop state Remarks 1 N X M 2 n 0 1 3 TM5n n 0 1 reading during timer operation When reading TM5n during operation select count clock having high low level wave form longer than two cycles of...

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Page 155: ... timer The watch timer and the interval timer can be used simultaneously Figure 8 1 shows the watch timer block diagram Figure 8 1 Watch Timer Block Diagram fX 27 fXT fW fW 24 fW 25 fW 26 fW 27 fW 28 fW 29 Clear 9 bit prescaler Clear 5 bit counter INTWT INTWTI WTM7 WTM6 WTM5 WTM4 WTM1 WTM0 Watch timer mode control register WTM Internal bus Selector Selector ...

Page 156: ... fX 8 38 MHz fX 4 19 MHz fXT 32 768 kHz 211 1 fX 24 1 fXT 244 µs 489 µs 488 µs 212 1 fX 25 1 fXT 489 µs 978 µs 977 µs 213 1 fX 26 1 fXT 978 µs 1 96 ms 1 95 ms 214 1 fX 27 1 fXT 1 96 ms 3 91 ms 3 91 ms 215 1 fX 28 1 fXT 3 91 ms 7 82 ms 7 81 ms 216 1 fX 29 1 fXT 7 82 ms 15 6 ms 15 6 ms Remark fX Main system clock oscillation frequency fXT Subsystem clock oscillation frequency 8 2 Watch Timer Configu...

Page 157: ...1H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 WTM WTM7 WTM6 WTM5 WTM4 0 0 WTM1 WTM0 WTM7 Watch timer count clock selection 0 fX 27 65 4 kHz 1 fXT 32 768 kHz WTM6 WTM5 WTM4 Prescaler interval time selection 0 0 0 24 fW 0 0 1 25 fW 0 1 0 26 fW 0 1 1 27 fW 1 0 0 28 fW 1 0 1 29 fW Other than above Setting prohibited WTM1 5 bit counter operation control 0 Clear after operation stop 1 Start WTM0 Watch t...

Page 158: ...9 1 fW at maximum may occur in the first overflow INTWT after the zero second start of watch timer 8 4 2 Interval timer operation The watch timer operates as interval timer which generates interrupt requests INTWTI repeatedly at an interval of the preset count value The interval time can be selected with bits 4 to 6 WTM4 to WTM6 of the watch timer mode control register WTM Table 8 3 Interval Timer...

Page 159: ...er clock frequency n The number of times of interval timer operations Figures in parentheses are for operation with fW 32 768 kHz 0H Start Overflow Overflow 5 bit counter Count clock fW 29 Watch timer interrupt INTWT Interval timer interrupt INTWTI Interrupt time of watch timer 0 5 s Interval time T T Interrupt time of watch timer 0 5 s n T n T ...

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Page 161: ... The watchdog timer and the interval timer cannot be used simultaneously Figure 9 1 shows a block diagram of the watchdog timer Figure 9 1 Watchdog Timer Block Diagram fX 28 RUN Clock input circuit control INTWDT RESET WDT mode signal 3 OSTS2 OSTS1 OSTS0 WDCS2 WDCS1 WDCS0 RUN WDTM4 Internal bus Division circuit Divided clock selection circuit Output controller Devision mode selection circuit WDTM3...

Page 162: ...6 1 fX 7 82 ms 217 1 fX 15 6 ms 218 1 fX 31 3 ms 220 1 fX 125 ms Remarks 1 fX Main system clock oscillation frequency 2 Figures in parentheses are for operation with fX 8 38 MHz 2 Interval timer mode Interrupt requests are generated at the preset time intervals Table 9 2 Interval Times Interval Time 212 1 fX 489 µs 213 1 fX 978 µs 214 1 fX 1 96 ms 215 1 fX 3 91 ms 216 1 fX 7 82 ms 217 1 fX 15 6 ms...

Page 163: ...nfiguration Control register Watchdog timer clock select register WDCS Watchdog timer mode register WDTM Oscillation stabilization time select register OSTS 9 3 Registers to Control the Watchdog Timer The following three types of registers are used to control the watchdog timer Watchdog timer clock select register WDCS Watchdog timer mode register WDTM Oscillation stabilization time select registe...

Page 164: ... 2 Format of Watchdog Timer Clock Select Register WDCS Address FF42H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 WDCS 0 0 0 0 0 WDCS2 WDCS1 WDCS0 WDCS2 WDCS1 WDCS0 Overflow time of watchdog timer interval timer 0 0 0 212 fX 489 µs 0 0 1 213 fX 978 µs 0 1 0 214 fX 1 96 ms 0 1 1 215 fX 3 91 ms 1 0 0 216 fX 7 82 ms 1 0 1 217 fX 15 6 ms 1 1 0 218 fX 31 3 ms 1 1 1 220 fX 125 ms Remarks 1 fX Main system ...

Page 165: ...on mode selectionNote 2 0 Interval timer modeNote 3 Maskable interrupt request occurs upon generation of an overflow 1 0 Watchdog timer mode 1 Non maskable interrupt request occurs upon generation of an overflow 1 1 Watchdog timer mode 2 Reset operation is activated upon generation of an overflow Notes 1 Once set to 1 RUN cannot be cleared to 0 by software Thus once counting starts it can only be ...

Page 166: ...when releasing the STOP mode by RESET input the time required to release is 217 fx Figure 9 4 Format of Oscillation Stabilization Time Select Register OSTS Address FFFAH After reset 04H R W Symbol 7 6 5 4 3 2 1 0 OSTS 0 0 0 0 0 OSTS2 OSTS1 OSTS0 OSTS2 OSTS1 OSTS0 Selection of oscillation stabilization time 0 0 0 212 fX 488 µs 0 0 1 214 fX 1 95 ms 0 1 0 215 fX 3 91 ms 0 1 1 216 fX 7 81 ms 1 0 0 217...

Page 167: ...runaway detection time is exceeded system reset or a non maskable interrupt request is generated according to WDTM bit 3 WDTM3 value The watchdog timer continues operating in the HALT mode but it stops in the STOP mode Thus set RUN to 1 before the STOP mode is set clear the watchdog timer and then execute the STOP instruction Cautions 1 The actual runaway detection time may be shorter than the set...

Page 168: ...NTWDT can be generated Among maskable interrupts INTWDT has the highest priority at default The interval timer continues operating in the HALT mode but it stops in STOP mode Thus set RUN to 1 before the STOP mode is set clear the interval timer and then execute the STOP instruction Cautions 1 Once bit 4 WDTM4 of WDTM is set to 1 this selects the watchdog timer mode the interval timer mode is not s...

Page 169: ...trolled transmission and clock output for supply to peripheral LSIs The clock selected with the clock output selection register CKS is output Figure 10 1 shows the block diagram of clock output control circuits Figure 10 1 Clock Output Control Circuit Block Diagram 8 Clock control circuit CLOE PCL P70 Internal bus Selector CLOE CCS3 CCS2 CCS1 CCS0 Clock output selection register CKS Prescaler fX t...

Page 170: ...lect register CKS Port mode register PM7 Note Note See Block Diagram of Figure 4 8 P70 to P73 P75 10 3 Register to Control Clock Output Control Circuit The following two types of registers are used to control the clock output control circuits Clock output select register CKS Port mode register PM7 1 Clock output select register CKS This register sets output enable disable for clock output PCL and ...

Page 171: ...fX 26 131 kHz 0 1 1 1 fX 27 65 5 kHz 1 0 0 0 fXT 32 768 kHz Other than above Setting prohibited Remarks 1 fX main system clock oscillation frequency 2 fXT Subsystem clock oscillation frequency 3 Figures in parentheses are for operation with fX 8 38 MHz or fXT 32 768 kHz 2 Port mode register PM7 This register sets port 7 input output in 1 bit units When using the P70 PCL pin for clock output set PM...

Page 172: ...ter CKS clock pulse output in disabled status 2 Set bit 4 CLOE of CKS to 1 and enable clock output Remark The clock output control circuit is designed not to output pulses with a small width during output enable disable switching of the clock output As shown in Figure 10 4 be sure to start output from the low period of the clock marked with in the figure When stopping output do so after securing h...

Page 173: ...I7 to perform A D conversion A D conversion operation is repeated Each time an A D conversion operation ends an interrupt request INTAD0 is generated Figure 11 1 A D Converter Block Diagram ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 Sample hold circuit Voltage comparator Successive approximation register SAR Control circuit 3 A D conversion result register ADCR0 AVREF Also used as analog power supply...

Page 174: ...r that stores the A D conversion result Each time A D conversion ends the conversion result is loaded from the successive approximation register ADCR0 is read by an 8 bit memory manipulation instruction RESET input sets ADCR0 to 00H Caution When writing is performed to the A D converter mode register ADM0 and analog input channel specification register ADS0 the contents of ADCR0 may become undefin...

Page 175: ...A D conversion A D conversion values may not be obtained as expected due to coupling noise Thus do not apply any pulse to a pin adjacent to the pin in the process of A D conversion 7 AVREF pin This pin inputs the A D converter reference voltage It can also be used as analog power supply It converts signals input to ANI0 to ANI7 into digital signals according to the voltage applied between AVREF an...

Page 176: ...ol 7 6 5 4 3 2 1 0 ADM0 ADCS0 0 FR02 FR01 FR00 0 0 0 ADCS0 A D conversion operation control 0 Stop conversion operation 1 Enable conversion operation FR02 FR01 FR00 Conversion time selectionNote 1 0 0 0 144 fX 17 1 µs 0 0 1 120 fX 14 3 µs 0 1 0 96 fX Setting prohibitedNote 2 1 0 0 72 fX Setting prohibitedNote 2 1 0 1 60 fX Setting prohibitedNote 2 1 1 0 48 fX Setting prohibitedNote 2 Other than ab...

Page 177: ...conversion ADS0 is set by an 8 bit memory manipulation RESET input sets ADS0 to 00H Figure 11 3 Format of Analog Input Channel Specification Register ADS0 Address FF81H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 ADS0 0 0 0 0 0 ADS02 ADS01 ADS00 ADS02 ADS01 ADS00 Analog input channel specification 0 0 0 ANI0 0 0 1 ANI1 0 1 0 ANI2 0 1 1 ANI3 1 0 0 ANI4 1 0 1 ANI5 1 1 0 ANI6 1 1 1 ANI7 ...

Page 178: ... analog input is greater than 1 2 AVREF the MSB of SAR remains set If the analog input is smaller than 1 2 AVREF the MSB is reset 6 Next bit 6 of SAR is automatically set and the operation proceeds to the next comparison The series resistor string voltage tap is selected according to the preset value of bit 7 as described below Bit 7 1 3 4 AVREF Bit 7 0 1 4 AFREF The voltage tap and analog input v...

Page 179: ...e operation is performed to the ADM0 or the analog input channel specification register ADS0 during an A D conversion operation the conversion operation is initialized and if the ADCS0 bit is set 1 conversion starts again from the beginning RESET input sets the A D conversion result register ADCR0 to 00H Conversion time Sampling time Sampling A D conversion Undefined 80H C0H or 40H Conversion resu...

Page 180: ... 5 AVREF or ADCR0 0 5 AVREF VIN ADCR0 0 5 AVREF 256 256 where INT Function which returns integer part of value in parentheses VIN Analog input voltage AVREF AVREF pin voltage ADCR0 A D conversion result register ADCR0 value Figure 11 5 shows the relationship between the analog input voltage and the A D conversion result Figure 11 5 Relationship between Analog Input Voltage and A D Conversion Resul...

Page 181: ...register ADCR0 and the interrupt request signal INTAD0 is generated After one A D conversion operation is started and ended the next conversion operation is immediately started A D conversion operations are repeated until new data is written to ADS0 If ADS0 is rewritten during A D conversion the converter suspends A D conversion and A D conversion of the newly selected analog input channel is star...

Page 182: ... In particular if a voltage higher than AVREF or lower than AVSS is input even if within the absolute maximum rating range the conversion value of that channel will be undefined and the conversion values of other channels may also be affected 3 Contending operations 1 Contention between A D conversion result register ADCR0 write and ADCR0 read by instruction upon the end of conversion ADCR0 read i...

Page 183: ...rsion the expected A D conversion value may not be obtainable due to coupling noise Therefore avoid applying pulses to pins adjacent to the pin undergoing A D conversion 6 AVREF pin input impedance A series resistor string of approx 10 kΩ is connected between the AVREF pin and the AVSS pin Therefore when the output impedance of the reference voltage is too high it seems as if the AVREF pin and the...

Page 184: ...Figure 11 9 A D Conversion End Interrupt Request Generation Timing Remarks 1 n 0 1 7 2 m 0 1 7 8 Conversion results just after A D conversion start The first A D conversion value just after A D conversion operations start may not fall within the rating Polling A D conversion end interrupt request INTAD0 and take measures such as removing the first conversion results 9 A D conversion result registe...

Page 185: ...erfaces are listed in Table 12 1 For details refer to the respective chapter Table 12 1 Outline of On Chip Serial Interface of the µPD780065 Subseries Channel Serial Transfer Mode UART0 UART Asynchronous serial interface SIO1 3 wire serial I O Automatic transmission reception function MSB LSB first switchable SIO30 2 wire serial I O Fixed to MSB first SIO31 3 wire serial I O Fixed to MSB first ...

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Page 187: ...an also be defined by dividing clocks input to the ASCK0 pin The UART baud rate generator can also be used to generate a MIDI standard baud rate 31 25 kbps For details see 13 4 2 Asynchronous serial interface UART mode 3 Infrared data transfer mode For details see 13 4 3 Infrared data transfer mode Figure 13 1 shows a block diagram of the serial interface UART0 macro Figure 13 1 Serial Interface U...

Page 188: ...XS0 and the receive buffer register RXB0 A read operation reads values from RXB0 2 Receive shift register RX0 This register converts serial data input via the RxD0 pin to parallel data When one byte of data is received at this register the receive data is transferred to the receive buffer register RXB0 RX0 cannot be manipulated directly by a program 3 Receive buffer register RXB0 This register is ...

Page 189: ...of registers for control functions Asynchronous serial interface mode register ASIM0 Asynchronous serial interface status register ASIS0 Baud rate generator control register BRGC0 1 Asynchronous serial interface mode register ASIM0 This is an 8 bit register that controls serial interface UART0 s serial transfer operations ASIM0 can be set by a 1 bit or 8 bit memory manipulation instruction RESET i...

Page 190: ...etection during reception parity errors do not occur 1 0 Odd parity 1 1 Even parity CL0 Character length specification 0 7 bits 1 8 bits SL0 Stop bit length specification for transmit data 0 1 bit 1 2 bits ISRM0 Receive completion interrupt control when error occurs 0 Receive completion interrupt request is issued when an error occurs 1 Receive completion interrupt request is not issued when an er...

Page 191: ... 1 Stop bit not detected OVE0 Overrun error flag 0 No overrun error 1 Overrun errorNote 2 Next receive operation was completed before data was read from receive buffer register Notes 1 Even if a stop bit length is set to two bits by setting bit 2 SL0 in the asynchronous serial interface mode register ASIM0 stop bit detection during a receive operation only applies to a stop bit length of 1 bit 2 B...

Page 192: ... 0 0 0 0 fSCK 16 0 0 0 0 1 fSCK 17 1 0 0 1 0 fSCK 18 2 0 0 1 1 fSCK 19 3 0 1 0 0 fSCK 20 4 0 1 0 1 fSCK 21 5 0 1 1 0 fSCK 22 6 0 1 1 1 fSCK 23 7 1 0 0 0 fSCK 24 8 1 0 0 1 fSCK 25 9 1 0 1 0 fSCK 26 10 1 0 1 1 fSCK 27 11 1 1 0 0 fSCK 28 12 1 1 0 1 fSCK 29 13 1 1 1 0 fSCK 30 14 1 1 1 1 Setting prohibit Cautions 1 Writing to BRGC0 during a communication operation may cause abnormal output from the bau...

Page 193: ...interface mode register ASIM0 ASIM0 can be set by a 1 bit or 8 bit memory manipulation instruction RESET input sets ASIM0 to 00H Address FFA0H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 ASIM0 TXE0 RXE0 PS01 PS00 CL0 SL0 ISRM0 IRDAM0 TXE0 RXE0 Operation mode RxD0 P73 pin function TxD0 P72 pin function 0 0 Operation stop Port function P73 Port function P72 0 1 UART mode Serial function RxD0 receive ...

Page 194: ... 1 Register settings UART mode is set by the asynchronous serial interface mode register ASIM0 asynchronous serial interface status register ASIS0 and the baud rate generator control register BRGC0 a Asynchronous serial interface mode register ASIM0 ASIM0 can be set by a 1 bit or 8 bit memory manipulation instruction RESET input sets ASIM0 to 00H Caution In UART mode set the port mode register PMX...

Page 195: ...ors do not occur 1 0 Odd parity 1 1 Even parity CL0 Character length specification 0 7 bits 0 8 bits SL0 Stop bit length specification for transmit data 0 1 bit 1 2 bits ISRM0 Receive completion interrupt control when error occurs 0 Receive completion interrupt request is issued when an error occurs 1 Receive completion interrupt request is not issued when an error occurs IRDAM0 Operation specifie...

Page 196: ...o framing error 1 Framing errorNote 1 Stop bit not detected OVE0 Overrun error flag 0 No overrun error 1 Overrun errorNote 2 Next receive operation was completed before data was read from receive buffer register Notes 1 Even if a stop bit length is set to two bits by setting bit 2 SL0 in the asynchronous serial interface mode register ASIM0 stop bit detection during a receive operation only applie...

Page 197: ...k selection for baud rate generator k 0 0 0 0 fSCK 16 0 0 0 0 1 fSCK 17 1 0 0 1 0 fSCK 18 2 0 0 1 1 fSCK 19 3 0 1 0 0 fSCK 20 4 0 1 0 1 fSCK 21 5 0 1 1 0 fSCK 22 6 0 1 1 1 fSCK 23 7 1 0 0 0 fSCK 24 8 1 0 0 1 fSCK 25 9 1 0 1 0 fSCK 26 10 1 0 1 1 fSCK 27 11 1 1 0 0 fSCK 28 12 1 1 0 1 fSCK 29 13 1 1 1 0 fSCK 30 14 1 1 1 1 Setting prohibit Cautions 1 Writing to BRGC0 during a communication operation m...

Page 198: ...ormula Baud rate fX Hz 2n 1 k 16 fX Main system clock oscillation frequency n Value set via TPS00 to TPS02 0 n 7 For details see Table 13 2 k Value set via MDL00 to MDL03 0 k 14 Table 13 2 shows the relationship between the 5 bit counter s source clock assigned to bits 4 to 6 TPS00 to TPS02 of BRGC0 and the n value in the above formula Table 13 2 Relationship between 5 Bit Counter s Source Clock a...

Page 199: ...0 70H 1 73 6BH 1 14 2400 6BH 1 10 6AH 0 16 68H 0 60H 1 73 5BH 1 14 4800 5BH 1 10 5AH 0 16 58H 0 50H 1 73 4BH 1 14 9600 4BH 1 10 4AH 0 16 48H 0 40H 1 73 3BH 1 14 19200 3BH 1 10 3AH 0 16 38H 0 30H 1 73 2BH 1 14 31250 31H 1 3 30H 0 2DH 1 70 24H 0 21H 1 3 38400 2BH 1 10 2AH 0 16 28H 0 20H 1 73 1BH 1 14 76800 1BH 1 10 1AH 0 16 18H 0 10H 1 73 115200 12H 1 10 11H 2 12 10H 0 Infrared 131031 bps 125000 bps...

Page 200: ...2AH 0 16 1AH 0 16 19200 1AH 0 16 312500 10H 0 Remark fX Main system clock oscillation frequency Figure 13 5 Error Tolerance when k 0 Including Sampling Errors Remark T 5 bit counter s source clock cycle Baud rate error tolerance when k 0 15 5 100 4 8438 320 Basic timing clock cycle T START D0 D7 P STOP High speed clock clock cycle T enabling normal reception START D0 D7 P STOP Low speed clock cloc...

Page 201: ... register ASIM0 is used to set the character bit length parity selection and stop bit length within each data frame When 7 bits is selected as the number of character bits only the low order 7 bits bits 0 to 6 are valid so that during a transmission the highest bit bit 7 is ignored and during reception the highest bit bit 7 must be set to 0 The ASIM0 and the baud rate generator control register BR...

Page 202: ...sfer data that include a parity bit and a parity error occurs when the counted result is an odd number ii Odd parity During transmission The number of bits in transmit data that includes a parity bit is controlled so that there is an odd number of bits whose value is 1 The value of the parity bit is as follows If the transmit data contains an odd number of bits whose value is 1 the parity bit is 0...

Page 203: ... 7 Figure 13 7 Timing of Asynchronous Serial Interface Transmit Completion Interrupt Request i Stop bit length 1 bit Caution Do not rewrite to the asynchronous serial interface mode register ASIM0 during a transmit operation Rewriting ASIM0 register during a transmit operation may disable further transmit operations in such cases enter a RESET to restore normal operation Whether or not a transmit ...

Page 204: ...rame is completed the receive data in the shift register is transferred to the receive buffer register RXB0 and a receive completion interrupt request INTSR0 occurs Even if an error has occurred the receive data in which the error occurred is still transferred to RXB0 When ASIM0 bit 1 ISRM0 is cleared 0 upon occurrence of an error INTSR0 occurs see Figure 13 9 When ISRM0 bit is set 1 INTSR0 does n...

Page 205: ...ror its error flag will be set Table 13 4 Causes of Receive Errors Receive Error Cause ASIS0 Value Parity error Parity specified during transmission does not match parity of receive data 04H Framing error Stop bit was not detected 02H Overrun error Reception of the next data was completed before data was read from the 01H receive buffer register Figure 13 9 Receive Error Timing Note If a receive e...

Page 206: ... string of the UART frame which consists of pulses a start bit eight data bits and a stop bit The length of the electrical pulses that are used to transmit and receive in an IR frame is 3 16 the length of the cycle time for one bit i e the bit time This pulse whose width is 3 16 the length of one bit time rises from the middle of the bit time see the figure below Figure 13 10 Data Format Compariso...

Page 207: ...e Pulse Width Minimum Value 3 16 Pulse Width Maximum Pulse Width Nominal Value kbits s of bit rate µs Note 2 µs µs 115 2 Note 1 0 87 1 41 1 63 2 71 Notes 1 At the operation time with fX 7 3728 MHz 2 When a digital noise elimination circuit is used in a microcontroller operating at 1 41 MHz or above Caution When using the baud rate generator control register BRGC0 in infrared data transfer mode set...

Page 208: ...iming Receive operation timing Data reception is delayed for one half of the specified baud rate UART output data UART Inverted data Infrared data transfer enable signal TxD0 pin output signal Start bit Stop bit UART transfer data RxD0 input Edge detection Sampling clock Start bit Stop bit Receive rate Conversion data Sampling timing ...

Page 209: ...ata transfer processing time Since the start bit of the 8 bit data that undergoes serial transfer is switchable between MSB and LSB connection is enabled with either start bit device The 3 wire serial I O mode is valid for connection of peripheral I O units and display controllers which incorporate a conventional synchronous serial interface 3 3 wire serial I O mode with automatic transmit receive...

Page 210: ...llowing hardware Table 14 1 Configuration of Serial Interface SIO1 Item Configuration Register Serial I O shift register 1 SIO1 Automatic data transmit receive address pointer ADTP0 Control register Serial operating mode register 1 CSIM1 Automatic data transmit receive control register ADTC0 Automatic data transmit receive interval specification register ADTI0 ...

Page 211: ...SCK10 Q R S Clear SIO1 write Serial I O shift register 1 SIO1 Buffer RAM Automatic data transmit receive address pointer ADTP0 Internal bus ADTI07 ADTI04 ADTI03 ADTI02 ADTI01 ADTI00 Match 5 Bit counter ADTI00 to ADTI04 RE0 ARLD0 ERCE0 ERR0 TRF0 STRB0 BUSY10 BUSY00 Selector TRF0 CSIE10 DIR10 ATE0 LCSK10 SCL101 SCL100 Serial operating mode register 1 CSIM1 INTCSI1 f X 2 3 to f X 2 5 Automatic data t...

Page 212: ...he serial input SI1 to SIO1 RESET input makes SIO1 undefined Caution Do not write data to SIO1 while the automatic transmit receive function is activated 2 Automatic data transmit receive address pointer ADTP0 This register stores the value of transmit data byte 1 while the automatic transmit receive function is activated As data is transferred received it is automatically decremented ADTP0 is set...

Page 213: ...serial clock operation mode operation enable stop and automatic transmit receive operation enable stop CSIM1 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets CSIM1 to 00H Caution In serial I O mode set the port mode register PMXX as follows In each case set the output latch to 0 respectively During serial clock output master transmission or master reception Set P82 SCK...

Page 214: ...f SCK1 pin 0 SCK1 is used as a port P82 when CSIE10 0 SCK1 is used for clock output when CSIE10 1 1 SCK1 is fixed to high level output when CSIE10 0 SCK1 is used for clock output when CSIE10 1 SCL101 SCL100 Selects serial clock of serial interface SIO1 0 0 External clock input to SCK1 pinNote 2 0 1 fX 23 1 05 MHz 1 0 fX 24 524 kHz 1 1 fX 25 262 kHz Notes 1 When CSIE10 0 SIO1 operation stop status ...

Page 215: ...ctive low BUSY00 0 1 STRB0 0 1 Strobe output control Strobe output disableNote 3 Strobe output enable TRF0 1 Status of automatic transmit receive functionNote 4 Detection of termination of automatic transmission reception This bit is set to 0 upon suspension of automatic transmission reception or when ARLD0 0 During automatic transmission reception This bit is set to 1 when data is written to SIO1...

Page 216: ...MOS I O is used even when bit 7 CSIE10 of CSIM1 is set to 1 4 When an interrupt is acknowledged interrupt request flag CSIIF1 is cleared Therefore use TRF0 instead of CSIIF1 to identify the completion of automatic transmission reception 5 When RE0 is reset to 0 P84 CMOS I O is used even when bit 7 CSIE10 of CSIM1 is set to 1 Caution When an external clock input is selected with bits 0 and 1 SCL101...

Page 217: ... fX 8 38 MHz fSCK 1 05 MHz Note 2 ADTI04 ADTI03 ADTI02 ADTI01 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 90 s 0 5 fSCK 2 86 s 0 5 fSCK 3 81 s 0 5 fSCK 4 76 s 0 5 fSCK 5 71 s 0 5 fSCK 6 67 s 0 5 fSCK 7 62 s 0 5 fSCK 8 57 s 0 5 fSCK 9 52 s 0 5 fSCK 10 5 s 0 5 fSCK 11 4 s 0 5 fSCK 12 4 s 0 5 fSCK 13 3 s 0 5 fSCK 14...

Page 218: ...terval time 2 0 5 fSCK fSCK 2 n 1 to 31 Interval time n 1 0 5 fSCK fSCK Cautions 1 Do not write ADTI0 during operation of automatic data transmit receive function 2 Be sure to set bits 5 and 6 to 0 3 When controlling the interval time of automatic transmit receive data transfer by using ADTI0 busy control is invalid Refer to 14 4 3 4 a Busy control option Remark fX Main system clock oscillation fr...

Page 219: ...ion frequency fSCK Serial clock frequency Figure 14 4 Format of Automatic Data Transmit Receive Interval Specification Register ADTI0 2 2 Address FF6BH After reset 00H R W Data transfer interval specification fX 8 38 MHz fSCK 1 05 MHz Note ADTI04 ADT0I3 ADTI02 ADTI01 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 16 2...

Page 220: ...SO1 P82 SCK1 P81 BUSY and P80 STB pins can be used as ordinary input output ports 1 Register setting The operation stop mode is set with the serial operating mode register 1 CSIM1 CSIM1 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets CSIM1 to 00H Address FF68H After reset 00H R W CSIE10 Enables disables operation of serial interface SIO1 Shift register operation Seria...

Page 221: ...utput mode PM82 0 During serial clock input slave transmission or slave reception Set P82 to input mode PM82 1 During transmission transmission and reception mode Set P83 SO1 to output mode PM83 0 During reception mode Set P84 SI1 to input mode PM84 1 Address FF68H After reset 00H R W CSIE10 Enables disables operation of serial interface SIO1 Shift register operation Serial counter PortNote 1 0 St...

Page 222: ... 2 STRB0 and 1 BUSY10 of the automatic data transmit receive control register ADTC0 to 0 0 Caution Be sure to set bits 2 and 3 to 0 2 Communication operation The 3 wire serial I O mode is used for data transmission reception in 8 bit units 1 bit unit data transmission reception is carried out in synchronization with the serial clock Shift operation of the serial I O shift register 1 SIO1 is carrie...

Page 223: ...der for data write to SIO1 The SIO1 shift order remains unchanged Thus MSB LSB start bit must be switched before writing data to the shift register 4 Transfer start Serial transfer is started by setting transfer data to the serial I O shift register 1 SIO1 when the following two conditions are satisfied Serial interface SIO1 operation control bit bit 7 CSIE10 of the serial operating mode register ...

Page 224: ...egister setting The 3 wire serial I O mode with automatic transmit receive function is set with the serial operation mode register 1 CSIM1 the automatic data transmit receive control register ADTC0 and the automatic data transmit receive interval specification register ADTI0 a Serial operation mode register 1 CSIM1 CSIM1 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets...

Page 225: ...SCK1 is used as port P82 when CSIE10 0 SCK1 is used for clock output when CSIE10 1 1 SCK1 is fixed to high level output when CSIE10 0 SCK1 is used for clock output when CSIE10 1 SCL101 SCL100 Selects serial clock of serial interface SIO1 0 0 External clock input to SCK1 pinNote 2 0 1 fX 23 1 05 MHz 1 0 fX 24 524 kHz 1 1 fX 25 262 kHz Notes 1 When CSIE10 0 SIO1 operation stop status P84 SI1 P83 SO1...

Page 226: ... transmit receive functionNote 4 Detection of termination of automatic transmission reception This bit is set to 0 upon suspension of automatic transmission reception or when ARLD0 0 During automatic transmission reception This bit is set to 1 when data is written to SIO1 R W R W R R ERR0 0 1 Error detection of automatic transmit receive function No error This bit is set to 0 when data is written ...

Page 227: ... 7 CSIE10 of CSIM1 is set to 1 4 When an interrupt is acknowledged interrupt request flag CSIIF1 is cleared Therefore use TRF0 instead of CSIIF1 to identify the completion of automatic transmission reception 5 When RE0 is reset to 0 P84 CMOS I O is used even when bit 7 CSIE10 of CSIM1 is set to 1 Caution When an external clock input is selected with CSIM1 bits 1 0 SCL101 SCL100 are set to 0 set AD...

Page 228: ...erval time of automatic transmit receive data transfer by using ADTI0 busy control is invalid Refer to 14 4 3 4 a Busy control option Remark fX Main system clock oscillation frequency fSCK Serial clock frequency Data transfer interval specification fX 8 38 MHz fSCK 1 05 MHz Note 2 ADTI04 ADTI03 ADTI02 ADTI01 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 ...

Page 229: ...valid Refer to 14 4 3 4 a Busy control option Remark fX Main system clock oscillation frequency fSCK Serial clock frequency Data transfer interval specification fX 8 38 MHz fSCK 1 05 MHz Note ADTI04 ADTI03 ADTI02 ADTI01 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 16 2 s 0 5 fSCK 17 1 s 0 5 fSCK 18 1 s 0 5 fSCK 19 0...

Page 230: ...nterval in the automatic data transmit receive interval specification register ADTI0 4 Write any value to the serial I O shift register 1 SIO1 transfer start trigger Caution Writing any value to SIO1 orders the start of automatic transmit receive operation and the written value has no meaning The following operations are automatically carried out when a and b are carried out After the buffer RAM d...

Page 231: ...s can be used as normal input output ports Figure 14 7 shows the basic transmit receive mode operation timings and Figure 14 8 shows the operation flowchart Figure 14 9 shows buffer RAM operation at 6 byte transmission Figure 14 7 Basic Transmit Receive Mode Operation Timings Cautions 1 Because inthebasictransmit receivemode theautomatictransmit receivefunction writes reads data to from the buffer...

Page 232: ...ransmit receive control register ADTC0 Start Write transmit data in buffer RAM Set ADTP0 to the value pointer value obtained by subtracting 1 from the number of transmit data bytes Set the transmit receive operation interval time in ADTI0 Write any data to SIO1 Start trigger Write transmit data from buffer RAM to SIO1 Transmission reception operation Write receive data from SIO1 to buffer RAM Poin...

Page 233: ...ansferred from the buffer RAM to SIO1 ii 4th byte transmit receive point refer to Figure 14 9 b Transmission reception of the third byte is completed and transmit data 4 T4 is transferred from the buffer RAM to SIO1 When transmission of the fourth byte is completed the receive data 4 R4 is transferred from SIO1 to the buffer RAM and ADTP0 is decremented iii Completion of transmission reception ref...

Page 234: ... byte transmission reception c Completion of transmission reception Receive data 1 R1 Receive data 2 R2 Receive data 3 R3 Transmit data 4 T4 Transmit data 5 T5 Transmit data 6 T6 FADFH FAC5H FAC0H Receive data 4 R4 SIO1 0 CSIIF1 2 ADTP0 _1 Receive data 1 R1 Receive data 2 R2 Receive data 3 R3 Receive data 4 R4 Receive data 5 R5 Receive data 6 R6 FADFH FAC5H FAC0H SIO1 1 CSIIF1 0 ADTP0 ...

Page 235: ...80 STB pins can be used as normal input ports Figure 14 10 shows the basic transmit mode operation timings and Figure 14 11 shows the operation flowchart Figure 14 12 shows buffer RAM operation in 6 byte repeat transmission Figure 14 10 Basic Transmit Mode Operation Timings Cautions 1 Because in the basic transmit mode the automatic transmit receive function reads data from the buffer RAM after 1 ...

Page 236: ...t 3 of automatic data transmit receive control register ADTC0 Start Write transmit data in buffer RAM Set ADTP0 to the value pointer value obtained by subtracting 1 from the number of transmit data bytes Set the transmit receive operation interval time in ADTI0 Write any data to SIO1 Start trigger Write transmit data from buffer RAM to SIO1 Transmission operation Pointer value 0 No TRF0 0 No End Y...

Page 237: ... data 2 T2 is transferred from the buffer RAM to SIO1 ii 4th byte transmission point refer to Figure 14 12 b Transmission of the third byte is completed and transmit data 4 T4 is transferred from the buffer RAM to SIO1 When transmission of the fourth byte is completed ADTP0 is decremented iii Completion of transmission reception refer to Figure 14 12 c When transmission of the sixth byte is comple...

Page 238: ...yte transmission point c Completion of transmission reception Transmit data 1 T1 Transmit data 2 T2 Transmit data 3 T3 Transmit data 4 T4 Transmit data 5 T5 Transmit data 6 T6 FADFH FAC5H FAC0H SIO1 1 CSIIF1 0 ADTP0 Transmit data 1 T1 Transmit data 2 T2 Transmit data 3 T3 Transmit data 4 T4 Transmit data 5 T5 Transmit data 6 T6 FADFH FAC5H FAC0H SIO1 0 CSIIF1 2 ADTP0 _1 ...

Page 239: ...ffer RAM contents are transmitted again When a reception operation busy control and strobe control are not performed the P84 SI1 P81 BUSY and P80 STB pins can be used as ordinary input output ports The repeat transmit mode operation timing is shown in Figure 14 13 and the operation flowchart in Figure 14 14 Figure 14 13 Repeat Transmit Mode Operation Timing Caution Since in the repeat transmit mod...

Page 240: ...egister SIO1 Serial I O shift register 1 Start Write transmit data in buffer RAM Set ADTP0 to the value pointer value obtained by subtracting 1 from the number of transmit data bytes Set the transmit receive operation interval time in ADTI0 Write any data to SIO1 Start trigger Write transmit data from buffer RAM to SIO1 Transmission operation Pointer value 0 No Yes Decrement pointer value Software...

Page 241: ...d from the buffer RAM to SIO1 ii Upon completion of transmission of 6 bytes refer to Figure 14 15 b When transmission of the sixth byte is completed the interrupt request flag CSIIF1 is not set The previous pointer value is assigned to the ADTP0 iii 7th byte transmission point refer to Figure 14 15 c Transmit data 1 T1 is transferred from the buffer RAM to SIO1 again When transmission of the first...

Page 242: ...pletion of transmission of 6 bytes c 7th byte transmission point Transmit data 1 T1 Transmit data 2 T2 Transmit data 3 T3 Transmit data 4 T4 Transmit data 5 T5 Transmit data 6 T6 FADFH FAC5H FAC0H SIO1 0 CSIIF1 0 ADTP0 Transmit data 1 T1 Transmit data 2 T2 Transmit data 3 T3 Transmit data 4 T4 Transmit data 5 T5 Transmit data 6 T6 FADFH FAC5H FAC0H SIO1 0 CSIIF1 5 ADTP0 _1 ...

Page 243: ...O1 P82 SCK1 P81 BUSY and P80 STB are set to the port mode During restart of transmission reception remaining data can be transferred by setting CSIE10 to 1 and writing any data to the serial I O shift register 1 SIO1 Cautions 1 If the HALT instruction is executed during automatic transmission reception transfer is suspended and the HALT mode is set even if 8 bit data transfer is in progress 2 When...

Page 244: ...hows the system configuration of the master device and a slave device when the busy control option is used Figure 14 17 System Configuration When Busy Control Option Is Used The master device inputs the busy signal output by the slave device to the BUSY P81 pin The master device samples the input busy signal in synchronization with the falling of the serial clock Even if the busy signal becomes ac...

Page 245: ... transmit receive control register ADTC0 When the busy signal becomes inactive waiting is released If the sampled busy signal is inactive transmission reception of the next 8 bit data is started at the falling edge of the next clock Because the busy signal is asynchronous with the serial clock it takes up to 1 clock until the busy signal is sampled even if made inactive by the slave It takes 0 5 c...

Page 246: ... control option the following conditions must be satisfied Bit 5 ATE0 of the serial operating mode register 1 CSIM1 is set to 1 Bit 2 STRB0 of the automatic data transmit receive control register ADTC0 is set to 1 A strobe signal is output from the STB P80 pin for the duration of 1 clock in synchronization with the falling of the ninth serial clock Figure 14 20 shows the operation timing when the ...

Page 247: ...used as a normal I O port pin To use the busy strobe control option the following conditions must be satisfied Bit 5 ATE0 of the serial operating mode register 1 CSIM1 is set to 1 Bit 2 STRB0 and bit 1 BUSY10 of the automatic data transmit receive control register ADTC0 are set to 1 The active level of the busy signal is set by bit 0 BUSY00 of ADTC0 BUSY00 0 Active high BUSY00 1 Active low Figure ...

Page 248: ...sed when BUSY00 0 Caution When TRF0 is cleared the SO1 pin becomes low level Remark CSIIF1 Interrupt request flag TRF0 Bit 3 of automatic data transmit receive control register ADTC0 STB SCK1 D7 SO1 SI1 CSIIF1 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 BUSY TRF0 Busy input released Busy input valid ...

Page 249: ...nal inactive within 2 clocks The master samples the busy signal in synchronization of the falling of the leading side of the serial clock If a bit shift does not occur all the eight serial clocks that have been sampled are inactive If the sampled serial clocks are active it is assumed that a bit shift has occurred and error processing is executed by setting bit 4 ERR0 of the automatic transmit rec...

Page 250: ...endent on ADTI0 is selected by setting of the bit 7 ADTI07 of ADTI0 If ADTI07 is reset to 0 the interval time is 2 fSCK If ADTI07 is set to 1 the interval time determined by the set contents of ADTI0 or interval time 2 fSCK according to CPU processing is selected whichever is is greater Figure 14 23 shows the interval time of automatic transmission reception Remark fSCK Serial clock frequency Figu...

Page 251: ...CK30 and serial data input output line SDIO30 The first bit of the serial transferred 8 bit data is fixed as the MSB 2 wire serial I O mode is useful for connection to a peripheral I O incorporating a clock synchronous serial interface or a display controller etc For details see 15 4 2 2 wire serial I O mode Figure 15 1 shows a block diagram of the serial interface SIO30 Figure 15 1 Serial Interfa...

Page 252: ...rial transmit receive shift operations synchronized with the serial clock SIO30 is set by an 8 bit memory manipulation instruction When 1 is set to bit 7 CSIE30 of the serial operation mode register 30 CSIM30 a serial operation can be started by writing data to or reading data from SIO30 When transmitting data written to SIO30 is output to the serial output SO30 When receiving data is read from th...

Page 253: ...aster reception Set P74 SCK30 to output mode PM74 0 During serial clock input slave transmission or slave reception Set P74 to input mode PM74 1 During transmit mode Set P75 SDIO30 to output mode PM75 0 During receive mode Set P75 SDIO30 to input mode PM75 1 Figure 15 2 Format of Serial Operation Mode Register 30 CSIM30 Address FFB0H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 CSIM30 CSIE30 0 0 0 0...

Page 254: ...mode power consumption can be reduced In addition pins can be used as normal I O ports 1 Register settings Operation stop mode is set by serial operation mode register 30 CSIM30 CSIM30 can be set by a 1 bit or 8 bit memory manipulation instruction RESET input sets CSIM0 to 00H Address FFB0H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 CSIM30 CSIE30 0 0 0 0 MODE0 SCL301 SCL300 CSIE30 SIO30 operation ...

Page 255: ...ode PM74 0 During serial clock input slave transmission or slave reception Set P74 to input mode PM74 1 During transmit mode Set P75 SDIO30 to output mode PM75 0 During receive mode Set P75 SDIO30 to input mode PM75 1 Address FFB0H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 CSIM30 CSIE30 0 0 0 0 MODE0 SCL301 SCL300 CSIE30 Enable disable specification for SIO30 Shift register operation Serial count...

Page 256: ... 15 3 Timing of 2 Wire Serial I O Mode 3 Transfer start Serial transfer starts when the following two conditions have been satisfied and transfer data has been set or read to serial I O shift register 30 SIO30 SIO30 operation control bit CSIE30 1 After an 8 bit serial transfer either the internal serial clock is stopped or SCK30 is set to high level Transmit mode When CSIE30 1 and MODE0 0 transfer...

Page 257: ...ansmit and receive operations are enabled in 3 wire serial I O mode the processing time for data transfers is reduced The first bit of the serial transferred 8 bit data is fixed as the MSB 3 wire serial I O mode is useful for connection to a peripheral I O incorporating a clock synchronous serial interface or a display controller etc For details see 16 4 2 3 wire serial I O mode Figure 16 1 shows ...

Page 258: ...rial transmit receive shift operations synchronized with the serial clock SIO31 is set by an 8 bit memory manipulation instruction When 1 is set to bit 7 CSIE31 of the serial operation mode register 31 CSIM31 a serial operation can be started by writing data to or reading data from SIO31 When transmitting data written to SIO31 is output to the serial output SO31 When receiving data is read from th...

Page 259: ...ing serial clock input slave transmission or slave reception Set P90 to input mode PM90 1 During transmit transmit and receive mode Set P91 SO31 to output mode PM91 0 During receive mode Set P92 SI31 to input mode PM92 1 Figure 16 2 Format of Serial Operation Mode Register 31 CSIM31 Address FFB1H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 CSIM31 CSIE31 0 0 0 0 MODE1 SCL311 SCL310 CSIE31 Enable dis...

Page 260: ...er consumption can be reduced In addition pins can be used as normal I O ports 1 Register settings Operation stop mode are set by the serial operation mode register 31 CSIM31 CSIM31 can be set by a 1 bit or 8 bit memory manipulation instruction RESET input sets CSIM0 to 00H Address FFB1H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 CSIM31 CSIE31 0 0 0 0 MODE1 SCL311 SCL310 CSIE31 SIO31 operation ena...

Page 261: ... transmission or master reception Set P90 SCK31 to output mode PM90 0 During serial clock input slave transmission or slave reception Set P90 to input mode PM90 1 During transmit transmit and receive mode Set P91 SO31 to output mode PM91 0 During receive mode Set P92 SI31 to input mode PM92 1 Address FFB1H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 CSIM31 CSIE31 0 0 0 0 MODE1 SCL311 SCL310 CSIE31 ...

Page 262: ...ith the rising edge of the serial clock is latched to SIO31 Completion of an 8 bit transfer automatically stops operation of SIO31 and sets interrupt request flag CSIIF31 Figure 16 3 Timing of 3 Wire Serial I O Mode 3 Transfer start A serial transfer starts when the following two conditions have been satisfied and transfer data has been set or read to serial I O shift register 31 SIO31 The SIO31 o...

Page 263: ...pt priority group by setting the priority specify flag registers PR0L PR0H PR1L Multiple high priority interrupts can be applied to low priority interrupts If two or more interrupts with the same priority are simultaneously generated each interrupt has a predetermined priority see Table 17 1 A standby release signal is generated Four external interrupt requests and fourteen internal interrupt requ...

Page 264: ...10 INTCSI1 End of serial interface SIO1 transfer 0018H 11 INTTM00 Match of 16 bit timer counter 0 and 001AH capture compare register 00 CR00 with CR00 specified to compare register TI00 valid edge detection with CR01 specified to capture register 12 INTTM01 Match of 16 bit timer counter 0 and 001CH capture compare register 01 CR01 with CR01 specified to compare register TI01 valid edge detection w...

Page 265: ...0 to INTP3 Internal Bus Interrupt request Priority Control Circuit Vector Table Address Generator Standby release signal Internal Bus Interrupt request IF MK IE PR ISP Priority Control Circuit Vector Table Address Generator Standby release signal Internal Bus Interrupt request IF MK IE PR ISP Priority Control Circuit Vector Table Address Generator Standby release signal External Interrupt Edge Ena...

Page 266: ...RUPT FUNCTIONS Preliminary User s Manual U13420EJ2V0UM00 Figure 17 1 Basic Configuration of Interrupt Function 2 2 D Software interrupt Internal Bus Interrupt request Priority Control Circuit Vector Table Address Generator ...

Page 267: ...pecify flags corresponding to interrupt request sources Table 17 2 Flags Corresponding to Interrupt Request Sources Interrupt Request Interrupt Request Flag Interrupt Mask Flag Priority Specify Flag Register Register Register INTWDT WDTIF IF0L WDTMK MK0L WDTPR PR0L INTP0 PIF0 PMK0 PPR0 INTP1 PIF1 PMK1 PPR1 INTP2 PIF2 PMK2 PPR2 INTP3 PIF3 PMK3 PPR3 INTSER0 SERIF0 SERMK0 SERPR0 INTSR0 SRIF0 SRMK0 SR...

Page 268: ...equest Flag Registers IF0L IF0H IF1L Address FFE0H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 IF0L STIF0 SRIF0 SERIF0 PIF3 PIF2 PIF1 PIF0 WDTIF Address FFE1H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 IF0H WTIIF TMIF51 TMIF50 TMIF01 TMIF00 CSIIF1 CSIIF31 CSIIF30 Address FFE2H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 IF1L 0 0 0 0 0 0 ADIF0 WTIF XXIFX Interrupt request flag 0 No interrupt request ...

Page 269: ... 5 4 3 2 1 0 MK0L STMK0 SRMK0 SERMK0 PMK3 PMK2 PMK1 PMK0 WDTMK Address FFE5H After reset FFH R W Symbol 7 6 5 4 3 2 1 0 MK0H WTIMK TMMK51 TMMK50 TMMK01 TMMK00 CSIMK1 CSIMK31 CSIMK30 Address FFE6H After reset FFH R W Symbol 7 6 5 4 3 2 1 0 MK1L 1 1 1 1 1 1 ADMK0 WTMK XXMKX Interrupt servicing control 0 Interrupt servicing enabled 1 Interrupt servicing disabled Cautions 1 If the watchdog timer is us...

Page 270: ...ESET input sets these registers to FFH Figure 17 4 Format of Priority Specify Flag Registers PR0L PR0H PR1L Address FFE8H After reset FFH R W Symbol 7 6 5 4 3 2 1 0 PR0L STPR0 SRPR0 SERPR0 PPR3 PPR2 PPR1 PPR0 WDTPR Address FFE9H After reset FFH R W Symbol 7 6 5 4 3 2 1 0 PR0H WTIPR TMPR51 TMPR50 TMPR01 TMPR00 CSIPR1 CSIPR31 CSIPR30 Address FFEAH After reset FFH R W Symbol 7 6 5 4 3 2 1 0 PR1L 1 1 ...

Page 271: ...ion instruction RESET input sets these registers to 00H Figure 17 5 Format of External Interrupt Rising Edge Enable Register EGP External Interrupt Falling Edge Enable Register EGN Address FF48H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 EGP 0 0 0 0 EGP3 EGP2 EGP1 EGP0 Address FF49H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 EGN 0 0 0 0 EGN3 EGN2 EGN1 EGN0 EGPn EGNn INTPn pin valid edge selection ...

Page 272: ...d into a stack and the IE flag is reset to 0 If a maskable interrupt request is acknowledged the contents of the priority specify flag of the acknowledged interrupt are transferred to the ISP flag The PSW contents are also saved into the stack with the PUSH PSW instruction They are reset from the stack with the RETI RETB and POP PSW instructions RESET input sets PSW to 02H Figure 17 6 Program Stat...

Page 273: ... non maskable interrupt request generated during execution of a non maskable interrupt servicing program is acknowledged after the current execution of the non maskable interrupt servicing program is terminated following RETI instruction execution and one main routine instruction is executed However if a new non maskable interrupt request is generated twice or more during non maskable interrupt se...

Page 274: ... processing WDTIF Interrupt request generated during this interval is acknowledged at WDTIF Watchdog timer interrupt request flag Start WDTM4 1 with watchdog timer mode selected Overflow in WDT WDT interrupt servicing Interrupt control register not accessed Interval timer No Reset processing No Interrupt request generation Start of interrupt servicing Interrupt request held pending No No No Yes Ye...

Page 275: ... interrupt servicing program execution Main routine NMI request 1 Execution of 1 instruction NMI request 2 Execution of NMI request 1 NMI request 2 held pending Servicing of NMI request 2 that was pended Main routine NMI request 1 Execution of 1 instruction Execution of NMI request 1 NMI request 2 held pending NMI request 3 held pending Servicing of NMI request 2 that was pended NMI request 3 not ...

Page 276: ...clocks 32 clocks When PR 1 8 clocks 33 clocks Note If an interrupt request is generated just before a divide instruction the wait time becomes longer Remark 1 clock 1 fCPU fCPU CPU clock If two or more interrupt requests are generated simultaneously the request with a higher priority level specified in the priority specify flag is acknowledged first If two or more interrupts requests have the same...

Page 277: ...servicing Start IF 1 MK 0 PR 0 IE 1 ISP 1 Interrupt request held pending Yes Yes No No Yes Interrupt request generation Yes No Low priority No No Yes Yes No IE 1 No Any high priority interrupt request among those simultaneously generated with PR 0 Yes High priority No Yes Yes No Vectored interrupt servicing Interrupt request held pending Interrupt request held pending Interrupt request held pendin...

Page 278: ...dged the contents are saved into the stacks in the order of the program status word PSW then program counter PC the IE flag is reset 0 and the contents of the vector table 003EH 003FH are loaded into PC and branched Return from a software interrupt is possible with the RETB instruction Caution Do not use the RETI instruction for returning from the software interrupt 8 clocks 7 clocks Instruction I...

Page 279: ...currently being serviced is generated during interrupt servicing it is not acknowledged for multiple interrupt servicing Interrupt requests that are not enabled because of the interrupt disable state or they have a lower priority are held pending When servicing of the current interrupt ends the pendent interrupt request is acknowledged following execution of one main processing instruction executi...

Page 280: ...due to priority control Interrupt request INTyy issued during servicing of interrupt INTxx is not acknowledged because its priority is lower than that of INTxx and multiple interrupt servicing does not take place The INTyy interrupt request is held pending and is acknowledged following execution of one main processing instruction PR 0 Higher priority level PR 1 Lower priority level IE 0 Interrupt ...

Page 281: ...nterrupt INTxx EI instruction is not issued therefore interrupt request INTyy is not acknowledged and multiple interrupt servicing does not take place The INTyy interrupt request is held pending and is acknowledged following execution of one main processing instruction PR 0 Higher priority level IE 0 Interrupt request acknowledge disabled Main processing INTxx servicing INTyy servicing EI 1 instru...

Page 282: ...0H PR1L EGP and EGN registers Caution The BRK instruction is not one of the above listed interrupt request hold instructions However the software interrupt activated by executing the BRK instruction causes the IE flag to be cleared Therefore even if a maskable interrupt requests is generated during execution of the BRK instruction the interrupt request is not acknowledged However a non maskable in...

Page 283: ...exed address data bus P40 to P47 A8 to A15 Address bus P50 to P57 RD Read strobe signal P64 WR Write strobe signal P65 WAIT Wait signal P66 ASTB Address strobe signal P67 Table 18 2 State of Port 4 to 6 Pins in External Memory Expansion Mode Port Port 4 Port 5 Port 6 External expansion mode 0 to 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 Single chip mode Port Port Port 256 byte expansion mode Address data ...

Page 284: ...byte expansion mode when MM2 MM0 011 Single chip mode FFFFH FF00H FEFFH FB00H FAFFH F800H F7FFH E000H DFFFH A100H A0FFH 0000H B000H AFFFH A000H 9FFFH 4 Kbyte expansion mode when MM2 MM0 100 FFFFH FF00H FEFFH FB00H FAFFH F800H F7FFH E800H E7FFH C100H C0FFH 0000H D000H CFFFH C000H BFFFH SFR Internal high speed RAM Full address mode when MM2 MM0 111 or 16 Kbyte expansion mode when MM2 MM0 101 256 byt...

Page 285: ...f Memory Expansion Mode Register MEM Address FF47H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 MEM 0 0 0 0 0 MM2 MM1 MM0 MM2 MM1 MM0 Single chip memory P40 to P47 P50 to P57 P64 to P67 pin state expansion mode selection P40 to P47 P50 to P53 P54 P55 P56 P57 P64 to P67 0 0 0 Single chip mode Port mode 0 0 1 0 1 1 Memory 256 byte AD0 to AD7 Port mode P64 RD expansion mode P65 WR 1 0 0 mode 4 Kbyte A8...

Page 286: ...ts MM is set by a 1 bit or 8 bit memory manipulation instruction RESET input sets MM to 10H Figure 18 3 Format of Memory Expansion Wait Setting Register MM Address FFF8H After reset 10H R W Symbol 7 6 5 4 3 2 1 0 MM 0 0 PW1 PW0 0 0 0 0 PW1 PW0 Wait control 0 0 No wait 0 1 Wait one wait state inserted 1 0 Setting prohibited 1 1 Wait control by external wait pin ...

Page 287: ...strobe signal is not output maintains high level 3 WAIT pin Alternate function P66 External wait signal input pin When the external wait is not used the WAIT pin can be used as an input output port During internal memory access the external wait signal is ignored 4 ASTB pin Alternate function P67 Address strobe signal output pin The address strobe signal is output regardless of data access and ins...

Page 288: ...ait PW1 PW0 0 0 setting b Wait PW1 PW0 0 1 setting c External wait PW1 PW0 1 1 setting RD ASTB AD0 to AD7 A8 to A15 Lower address Instruction code Higher address RD ASTB AD0 to AD7 A8 to A15 Internal wait signal 1 clock wait Lower address Instruction code Higher address RD ASTB AD0 to AD7 A8 to A15 WAIT Lower address Instruction code Higher address ...

Page 289: ... No wait PW1 PW0 0 0 setting b Wait PW1 PW0 0 1 setting c External wait PW1 PW0 1 1 setting RD ASTB AD0 to AD7 A8 to A15 Lower address Read data Higher address RD ASTB AD0 to AD7 A8 to A15 Internal wait signal 1 clock wait Lower address Read data Higher address RD ASTB AD0 to AD7 A8 to A15 WAIT Lower address Read data Higher address ...

Page 290: ... PW1 PW0 0 0 setting b Wait PW1 PW0 0 1 setting c External wait PW1 PW0 1 1 setting WR ASTB AD0 to AD7 A8 to A15 Lower address Write data Higher address Hi Z WR ASTB AD0 to AD7 A8 to A15 Internal wait signal 1 clock wait Lower address Write data Higher address Hi Z WR ASTB AD0 to AD7 A8 to A15 WAIT Lower address Write data Higher address Hi Z ...

Page 291: ...etting b Wait PW1 PW0 0 1 setting c External wait PW1 PW0 1 1 setting Read data Write data Higher address Hi Z Lower address RD ASTB AD0 to AD7 A8 to A15 WR RD ASTB AD0 to AD7 A8 to A15 Hi Z WR Write data Higher address Internal wait signal 1 clock wait Read data Lower address WAIT Hi Z RD ASTB AD0 to AD7 A8 to A15 WR Write data Higher address Read data Lower address ...

Page 292: ...e SRAM in Figure 18 8 In addition the external device expansion function is used in the full address mode and the addresses from 0000H to 9FFFH 40 Kbytes are allocated for internal ROM and the addresses after A000H from SRAM Figure 18 8 Connection Example of µPD780065 and Memory RD WR A8 to A14 ASTB AD0 to AD7 VDD0 PD74HC573 LE D0 to D7 OE Q0 to Q7 PD43256B CS OE WE I O1 to I O8 A0 to A14 Data bus...

Page 293: ...ra low current consumption Because this mode can be cleared upon interrupt request it enables intermittent operations to be carried out However because a wait time is required to secure an oscillation stabilization time after the STOP mode is cleared select the HALT mode if it is necessary to start processing immediately upon interrupt request In either of these two modes all the contents of regis...

Page 294: ...mbol 7 6 5 4 3 2 1 0 OSTS 0 0 0 0 0 OSTS2 OSTS1 OSTS0 OSTS2 OSTS1 OSTS0 Selection of oscillation stabilization time 0 0 0 212 fX 488 µs 0 0 1 214 fX 1 95 ms 0 1 0 215 fX 3 91 ms 0 1 1 216 fX 7 81 ms 1 0 0 217 fX 15 6 ms Other than above Setting prohibited Caution The wait time after the STOP mode is cleared does not include the time see a in the illustration below from STOP mode clear to clock osc...

Page 295: ...Clock generator Both main system clock and subsystem clock can be oscillated Clock supply to CPU stops CPU Operation stops Port Output latch Status before HALT mode setting is held 16 bit timer event Operable Operable when TI00 counter is selected 8 bit timer event Operable Operable when TI50 counter TI51 are selected as count clock Watch timer Operable when fX 27 is Operable Operable when fXT is ...

Page 296: ...ar Upon Interrupt Request Generation HALT instruction Wait Wait Operation mode HALT mode Operation mode Oscillation Clock Standby release signal Interrupt request Remarks 1 The broken line indicates the case when the interrupt request which has cleared the standby mode is acknowledged 2 Wait times are as follows When vectored interrupt service is carried out 8 or 9 clocks When vectored interrupt s...

Page 297: ...tion with fX 8 38 MHz Table 19 2 Operation after HALT Mode Release Release Source MK PR IE ISP Operation Maskable interrupt request 0 0 0 Next address instruction execution 0 0 1 Interrupt service execution 0 1 0 1 Next address instruction execution 0 1 0 0 1 1 1 Interrupt service execution 1 HALT mode hold Non maskable interrupt request Interrupt service execution RESET input Reset processing don...

Page 298: ...STS the operating mode is set The operating status in the STOP mode is described in Table 19 3 below Table 19 3 STOP Mode Operating Status STOP Mode Setting With Subsystem Clock Without Subsystem Clock Item Clock generator Only main system clock oscillation is stopped CPU Operation stops Port Output latch Status before STOP mode setting is held 16 bit timer event counter Operation stops 8 bit time...

Page 299: ...illation stabilization time vectored interrupt service is carried out If interrupt acknowledge is disabled the next address instruction is executed Figure 19 4 STOP Mode Release by Interrupt Request Generation Remark The broken line indicates the case when the interrupt request which has cleared the standby status is acknowledged STOP instruction Wait Time set by OSTS Oscillation stabilization wai...

Page 300: ...eses are for operation with fX 8 38 MHz Table 19 4 Operation after STOP Mode Release Release Source MK PR IE ISP Operation Maskable interrupt request 0 0 0 Next address instruction execution 0 0 1 Interrupt service execution 0 1 0 1 Next address instruction execution 0 1 0 0 1 1 1 Interrupt service execution 1 STOP mode hold RESET input Reset processing don t care STOP instruction Wait 217 fX 15 6...

Page 301: ...on time just after reset clear When a high level is input to the RESET pin the reset is cleared and program execution starts after the lapse of oscillation stabilization time 217 fX The reset applied by watchdog timer overflow is automatically cleared after a reset and program execution starts after the lapse of oscillation stabilization time 217 fX see Figures 20 2 to 20 4 Cautions 1 For an exter...

Page 302: ...stabilization time wait Normal operation Reset processing X1 RESET Internal reset signal Port pin Hi Z Normal operation Reset period Oscillation stop Oscillation stabilization time wait Normal operation Reset processing X1 Watchdog timer overflow Internal reset signal Port pin Delay Delay Hi Z Normal operation Oscillation stabilization time wait Normal operation Reset processing X1 RESET Internal ...

Page 303: ... selection register OSTS 04H 16 bit timer event Timer register TM0 0000H counter Capture compare register CR00 CR01 Undefined Prescaler mode register PRM0 00H Mode control register TMC0 00H Output control register TOC0 00H 8 bit timer event counter Timer counters TM50 TM51 00H Compare registers CR50 CR51 Undefined Clock selection registers TCL50 TCL51 00H Mode control register TMC50 TMC51 04H Watc...

Page 304: ...0H Transmit shift register TXS0 FFH Receive buffer register RXB0 Serial interface SIO1 Shift register SIO1 Undefined Automatic data transmission reception address pointer ADTP0 00H Operating mode register CSIM1 00H Automatic data transmission reception control register ADTC0 00H Automatic data transmission reception interval specification 00H register ADTI0 Serial interface SIO3 Shift registers SI...

Page 305: ... 21 1 Differences between µPD78F0066 and Mask ROM Version Item µPD78F0066 Mask ROM Version µPD780065 Internal ROM configuration Flash memory Mask ROM Internal ROM capacity 48 Kbytes 40 Kbytes IC pin None Available VPP pin Available None Electrical specifications Refer to data sheet of each product Caution Flash memory versions and mask ROM versions differ in their noise immunity and noise radiatio...

Page 306: ...ut sets IMS to CFH Caution The initial value of IMS is CFH setting prohibited As the initial program setting be sure to set the following values µPD780065 CAH µPD78F0066 CCH or a value supporting the Mask ROM version Figure 21 1 Format of Memory Size Switching Register IMS Address FFF0H After reset CFH R W Symbol 7 6 5 4 3 2 1 0 IMS RAM2 RAM1 RAM0 0 ROM3 ROM2 ROM1 ROM0 RAM2 RAM1 RAM0 Internal high...

Page 307: ...nipulation instruction RESET input sets IXS to 0CH Caution Set IXS to 04H as the initial value of the program The initial value of IXS is 0CH setting prohibited Figure 21 2 Format of Internal Expansion RAM Size Switching Register IXS Address FFF4H After reset 0CH R W Symbol 7 6 5 4 3 2 1 0 IXS 0 0 0 IXRAM4 IXRAM3 IXRAM2 IXRAM1 IXRAM0 IXRAM4 IXRAM3 IXRAM2 IXRAM1 IXRAM0 Internal expansion RAM capaci...

Page 308: ...ashpro III and serial communication Select the transmission method for writing from Table 21 2 For the selection of the transmission method a format like the one shown in Figure 21 3 is used The transmission methods are selected with the VPP pulse numbers shown in Table 21 2 Table 21 2 Transmission Method List Transmission Method Number of Channels Pin Used Number of VPP Pulses 3 wire serial I O 2...

Page 309: ...bytes Continuous write Performs successive write operations using the data input with high speed write operation Status Checks the current operation mode and operation end Oscillation frequency setting Inputs the resonator oscillation frequency information Delete time setting Inputs the memory delete time Baud rate setting Sets the transmission rate when the UART method is used Silicon signature r...

Page 310: ...µPD78F0066 Preliminary User s Manual U13420EJ2V0UM00 Figure 21 5 Connection of Flashpro II or Flashpro III Using UART Method VPP VDD RESET SO SI GND VPP VDD RESET RxD0 TxD0 VSS Flashpro II or Flashpro III PD78F0066 µ ...

Page 311: ...V0UM00 CHAPTER 22 INSTRUCTION SET This chapter lists each instruction set of the µPD780065 Subseries in table form For details of its operation and operation code refer to the separate document 78K 0 Series User s Manual Instructions U12326E ...

Page 312: ...d rp either function names X A C etc or absolute names names in parentheses in the table below R0 R1 R2 etc can be used for description Table 22 1 Operand Identifiers and Description Methods Identifier Description Method r X R0 A R1 C R2 B R3 E R4 D R5 L R6 H R7 rp AX RP0 BC RP1 DE RP2 HL RP3 sfr Special function register symbolNote sfrp Special function register symbol 16 bit manipulatable regist...

Page 313: ...flag AC Auxiliary carry flag Z Zero flag RBS Register bank select flag IE Interrupt request enable flag NMIS Non maskable interrupt servicing flag Memory contents indicated by address or register contents in parentheses XH XL Higher 8 bits and lower 8 bits of 16 bit register Logical product AND Logical sum OR Exclusive logical sum exclusive OR Inverted data addr16 16 bit immediate data or label jd...

Page 314: ...L C HL C A 1 6 7 m HL C A XCH A r Note 3 1 2 A r A saddr 2 4 6 A saddr A sfr 2 6 A sfr A addr16 3 8 10 n m A addr16 A DE 1 4 6 n m A DE A HL 1 4 6 n m A HL A HL byte 2 8 10 n m A HL byte A HL B 2 8 10 n m A HL B A HL C 2 8 10 n m A HL C Notes 1 When the internal high speed RAM area is accessed or instruction with no data access 2 When an area except the internal high speed RAM area is accessed 3 E...

Page 315: ...A CY A byte CY saddr byte 3 6 8 saddr CY saddr byte CY A r Note 4 2 4 A CY A r CY r A 2 4 r CY r A CY A saddr 2 4 5 A CY A saddr CY A addr16 3 8 9 n A CY A addr16 CY A HL 1 4 5 n A CY A HL CY A HL byte 2 8 9 n A CY A HL byte CY A HL B 2 8 9 n A CY A HL B CY A HL C 2 8 9 n A CY A HL C CY Notes 1 When the internal high speed RAM area is accessed or instruction with no data access 2 When an area exce...

Page 316: ...Y A HL byte CY A HL B 2 8 9 n A CY A HL B CY A HL C 2 8 9 n A CY A HL C CY AND A byte 2 4 A A byte saddr byte 3 6 8 saddr saddr byte A r Note 3 2 4 A A r r A 2 4 r r A A saddr 2 4 5 A A saddr A addr16 3 8 9 n A A addr16 A HL 1 4 5 n A A HL A HL byte 2 8 9 n A A HL byte A HL B 2 8 9 n A A HL B A HL C 2 8 9 n A A HL C Notes 1 When the internal high speed RAM area is accessed or instruction with no d...

Page 317: ...2 8 9 n A A HL B A HL C 2 8 9 n A A HL C CMP A byte 2 4 A byte saddr byte 3 6 8 saddr byte A r Note 3 2 4 A r r A 2 4 r A A saddr 2 4 5 A saddr A addr16 3 8 9 n A addr16 A HL 1 4 5 n A HL A HL byte 2 8 9 n A HL byte A HL B 2 8 9 n A HL B A HL C 2 8 9 n A HL C Notes 1 When the internal high speed RAM area is accessed or instruction with no data access 2 When an area except the internal high speed R...

Page 318: ...cumulator after Subtract MOV1 CY saddr bit 3 6 7 CY saddr bit CY sfr bit 3 7 CY sfr bit CY A bit 2 4 CY A bit CY PSW bit 3 7 CY PSW bit CY HL bit 2 6 7 n CY HL bit saddr bit CY 3 6 8 saddr bit CY sfr bit CY 3 8 sfr bit CY A bit CY 2 4 A bit CY PSW bit CY 3 8 PSW bit CY HL bit CY 2 6 8 n m HL bit CY Notes 1 When the internal high speed RAM area is accessed or instruction with no data access 2 When ...

Page 319: ... 8 sfr bit 1 A bit 2 4 A bit 1 PSW bit 2 6 PSW bit 1 HL bit 2 6 8 n m HL bit 1 CLR1 saddr bit 2 4 6 saddr bit 0 sfr bit 3 8 sfr bit 0 A bit 2 4 A bit 0 PSW bit 2 6 PSW bit 0 HL bit 2 6 8 n m HL bit 0 SET1 CY 1 2 CY 1 1 CLR1 CY 1 2 CY 0 0 NOT1 CY 1 2 CY CY Notes 1 When the internal high speed RAM area is accessed or instruction with no data access 2 When an area except the internal high speed RAM a...

Page 320: ... rp 1 4 SP 1 rpH SP 2 rpL SP SP 2 POP PSW 1 2 PSW SP SP SP 1 R R R rp 1 4 rpH SP 1 rpL SP SP SP 2 MOVW SP word 4 10 SP word SP AX 2 8 SP AX AX SP 2 8 AX SP BR addr16 3 6 PC addr16 addr16 2 6 PC PC 2 jdisp8 AX 2 8 PCH A PCL X BC addr16 2 6 PC PC 2 jdisp8 if CY 1 BNC addr16 2 6 PC PC 2 jdisp8 if CY 0 BZ addr16 2 6 PC PC 2 jdisp8 if Z 1 BNZ addr16 2 6 PC PC 2 jdisp8 if Z 0 Notes 1 When the internal h...

Page 321: ...bit addr16 4 12 PC PC 4 jdisp8 if PSW bit 1 then reset PSW bit HL bit addr16 3 10 12 n m PC PC 3 jdisp8 if HL bit 1 then reset HL bit DBNZ B addr16 2 6 B B 1 then PC PC 2 jdisp8 if B 0 C addr16 2 6 C C 1 then PC PC 2 jdisp8 if C 0 saddr addr16 3 8 10 saddr saddr 1 then PC PC 3 jdisp8 if saddr 0 SEL RBn 2 4 RBS1 0 n NOP 1 2 No Operation EI 2 6 IE 1 Enable Interrupt DI 2 6 IE 0 Disable Interrupt HAL...

Page 322: ...RUCTION SET Preliminary User s Manual U13420EJ2V0UM00 22 3 Instructions Listed by Addressing Type 1 8 bit instructions MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MULU DIVUW INC DEC ROR ROL RORC ROLC ROR4 ROL4 PUSH POP DBNZ ...

Page 323: ...XCH ROL SUB ADD ADD ADD ADD ADD RORC SUBC ADDC ADDC ADDC ADDC ADDC ROLC AND SUB SUB SUB SUB SUB OR SUBC SUBC SUBC SUBC SUBC XOR AND AND AND AND AND CMP OR OR OR OR OR XOR XOR XOR XOR XOR CMP CMP CMP CMP CMP r MOV MOV INC ADD DEC ADDC SUB SUBC AND OR XOR CMP B C DBNZ sfr MOV MOV saddr MOV MOV DBNZ INC ADD DEC ADDC SUB SUBC AND OR XOR CMP addr16 MOV PSW MOV MOV PUSH POP DE MOV HL MOV ROR4 ROL4 HL by...

Page 324: ...drp MOVW MOVW addr16 MOVW SP MOVW MOVW Note Only when rp BC DE HL 3 Bit manipulation instructions MOV1 AND1 OR1 XOR1 SET1 CLR1 NOT1 BT BF BTCLR Second Operand A bit sfr bit saddr bit PSW bit HL bit CY addr16 None First Operand A bit MOV1 BT SET1 BF CLR1 BTCLR sfr bit MOV1 BT SET1 BF CLR1 BTCLR saddr bit MOV1 BT SET1 BF CLR1 BTCLR PSW bit MOV1 BT SET1 BF CLR1 BTCLR HL bit MOV1 BT SET1 BF CLR1 BTCLR...

Page 325: ...nch instructions CALL CALLF CALLT BR BC BNC BZ BNZ BT BF BTCLR DBNZ Second Operand AX addr16 addr11 addr5 addr16 First Operand Basic instruction BR CALL CALLF CALLT BR BR BC BNC BZ BNZ Compound BT instruction BF BTCLR DBNZ 5 Other instructions ADJBA ADJBS BRK RET RETI RETB SEL NOP EI DI HALT STOP ...

Page 326: ...326 Preliminary User s Manual U13420EJ2V0UM00 MEMO ...

Page 327: ... employ the µPD780065 Subseries Support for PC98 NX series Unless otherwise specified products supported by IBM PC AT and compatibles can be used for the PC98 NX series When using the PC98 NX series refer to the explanations of IBM PC AT and compatibles Windows Unless otherwise specified Windows indicates following OSs Windows 3 1 Windows95 WindowsNT Ver 4 0 ...

Page 328: ... Integrated debugger Device file Embedded Software Real time OS OS Debugging Tool Assembler package C compiler package C library source file Device file Language Processing Software Flash memory write adapter In circuit Emulator Power supply unit Emulation probe Conversion socket or conversion adapter Target system Host Machine PC Interface adapter PC card interface etc Emulation board I O board P...

Page 329: ...egrated debugger Device file Embedded Software Real time OS OS Debugging Tool Assembler package C compiler package C library source file Device file Language Processing Software Flash memory write adapter In circuit Emulator Emulation probe Conversion socket or conversion adapter Target system Host Machine PC or EWS Interface board Interface adapter Emulation board I O board Probe board Emulation ...

Page 330: ...roject Manager included in assembler package on Windows Part Number µS RA78K0 This compiler converts programs written in C language into object codes executable with a microcontroller This compiler should be used in combination with an optical assembler package and device file Precaution when using RA78K 0 in PC environment This C compiler package is a DOS based application It can also be used in ...

Page 331: ...0 DAT DDS 3K13 SPARCstationTM SunOSTM Rel 4 1 4 3 5 inch 2HC FD 3K15 Solaris Rel 2 5 1 1 4 inch CGMT 3R13 NEWSTM RISC NEWS OSTM Rel 6 1 3 5 inch 2HC FD Note Can also be operated in DOS environment A 2 Flash Memory Writing Tools Flashpro II type FL PR2 Flash programmer dedicated to microcontrollers with on chip flash memory Flashpro III type FL PR3 PG FP3 Flash programmer FA 80GCNote Flash memory w...

Page 332: ...hine This board is used for extending the IE 78K0 NS functions and is used connected to the IE 78K0 NS With the addition of this board the addition of a coverage function enhancementoftracerandtimerfunctions andothersuchdebuggingfunctionenhancements are possible This adapter is used for supplying power from a receptacle of 100 V to 240 V AC This adapter is required when using the PC 9800 series PC...

Page 333: ...to the host machine This adapter is required when using the PC 9800 series computer except notebook type as the IE 78001 R A host machine C bus supported This adapter is required when using the IBM PC AT and compatibles as the IE 78001 R A host machine ISA bus supported This adapter is required when using the PC with an on chip PCI bus as the IE 78001 R A host machine This is adapter and cable req...

Page 334: ...sting and performance testing on an independent basis from hardware development without having to use an in circuit emulator thereby providing higher development efficiency and software quality The SM78K0 should be used in combination with the optical device file DF780066 Part Number µS SM78K0 Remark in the part number differs depending on the host machine and OS used µS SM78K0 Host Machine OS Sup...

Page 335: ...n 3P16 HP9000 series 700 HP UX Rel 10 10 DAT DDS 3K13 SPARCstation SunOS Rel 4 1 4 3 5 inch 2HC FD 3K15 Solaris Rel 2 5 1 1 4 inch CGMT 3R13 NEWSTM RISC NEWS OS Rel 6 1 3 5 inch 2HC FD This debugger is a control program to debug 78K 0 Series microcontrollers It adopts a graphical user interface which is equivalent visually and operationally to Windows or OSF Motif It also has an enhanced debugging...

Page 336: ... 78000 R A that in circuit emulator can operate as an equivalent to the IE 78001 R A by replacing its internal break board with the IE 78001 R BK Table A 1 System up Method from Former In circuit Emulator for 78K 0 Series to the IE 78001 R A In circuit Emulator Owned In circuit Emulator Cabinet System upNote Board to be Purchased IE 78000 R Required IE 78001 R BK IE 78000 R A Not required Note For...

Page 337: ... pin index E EV 9200GC 80 B C M N O L K S R Q P I H J G EV 9200GC 80 G1E ITEM MILLIMETERS INCHES A B C D E F G H I J K L M N O P Q R S 18 0 14 4 14 4 18 0 4 C 2 0 0 8 6 0 16 0 18 7 6 0 16 0 18 7 8 2 8 0 2 5 2 0 0 35 2 3 1 5 0 709 0 567 0 567 0 709 4 C 0 079 0 031 0 236 0 63 0 736 0 236 0 63 0 736 0 323 0 315 0 098 0 079 0 014 0 091 0 059 φ φ Based on EV 9200GC 80 1 Package drawing in mm φ φ ...

Page 338: ...0 03 2 3 1 57 0 03 0 776 0 591 0 591 0 776 0 236 0 236 0 014 0 093 0 091 0 062 0 65 0 02 19 12 35 0 05 0 65 0 02 19 12 35 0 05 φ φ 0 001 0 002 0 003 0 002 0 001 0 002 0 003 0 002 0 003 0 002 0 003 0 002 0 001 0 001 0 001 0 002 φ 0 001 0 002 φ φ Based on EV 9200GC 80 2 Pad drawing in mm Dimensions of mount pad for EV 9200 and that for target device QFP may be different in some parts For the recomme...

Page 339: ...339 Preliminary User s Manual U13420EJ2V0UM00 APPENDIX B EMBEDDED SOFTWARE For efficient development and maintenance of the µPD780065 Subseries the following embedded products are available ...

Page 340: ...ce and sign the user agreement Remark and in the part number differ depending on the host machine and OS used µS RX78013 Product Outline Maximum Number for Use in Mass Production 001 Evaluation object Do not use for mass produced product 100K Mass production object 0 1 million units 001M 1 million units 010M 10 million units S01 Source program Source program for mass produced object Host Machine O...

Page 341: ...er differ depending on the host machine and OS used µS MX78K0 Product Outline Maximum Number for Use in Mass Production 001 Evaluation object Use in preproduction stages Mass production object Use in mass production stages S01 Source program Only the users who purchased mass production objects are allowed to purchase this program Host Machine OS Supply Medium AA13 PC 9800 series Windows Japanese v...

Page 342: ...342 Preliminary User s Manual U13420EJ2V0UM00 MEMO ...

Page 343: ...ster CRC0 110 Clock output select register CKS 170 E 8 bit compare register 50 CR50 137 8 bit compare register 51 CR51 137 8 bit counter 50 TM50 137 8 bit counter 51 TM51 137 8 bit timer mode control register 50 TMC50 139 8 bit timer mode control register 51 TMC51 139 External interrupt falling edge enable register EGN 271 External interrupt rising edge enable register EGP 271 I Internal expansion...

Page 344: ... PCC 92 Program status word PSW 50 272 Pull up resistor option register 0 PU0 87 Pull up resistor option register 2 PU2 87 Pull up resistor option register 3 PU3 87 Pull up resistor option register 4 PU4 87 Pull up resistor option register 5 PU5 87 Pull up resistor option register 6 PU6 87 Pull up resistor option register 7 PU7 87 Pull up resistor option register 8 PU8 87 Pull up resistor option r...

Page 345: ... control register 0 TMC0 108 16 bit timer output control register 0 TOC0 111 T Timer clock select register 50 TCL50 138 Timer clock select register 51 TCL51 139 Transmit shift register TXS0 188 W Watch timer mode control register WTM 157 Watchdog timer clock select register WDCS 164 Watchdog timer mode register WDTM 165 ...

Page 346: ...er 110 CR00 16 bit capture compare register 00 107 CR01 16 bit capture compare register 01 108 CR50 8 bit compare register 50 137 CR51 8 bit compare register 51 137 CSIM1 Serial operation mode register 1 213 224 CSIM30 Serial operation mode register 30 253 254 255 CSIM31 Serial operation mode register 31 259 260 261 E EGN External interrupt falling edge enable register 271 EGP External interrupt r...

Page 347: ...gister 0H 270 PR0L Priority specify flag register 0L 270 PR1L Priority specify flag register 1L 270 PRM0 Prescaler mode register 0 112 PSW Program status word 50 272 PU0 Pull up resistor option register 0 87 PU2 Pull up resistor option register 2 87 PU3 Pull up resistor option register 3 87 PU4 Pull up resistor option register 4 87 PU5 Pull up resistor option register 5 87 PU6 Pull up resistor opt...

Page 348: ... bit counter 50 137 TM51 8 bit counter 51 137 TMC0 16 bit timer mode control register 0 108 TMC50 8 bit timer mode control register 50 139 TMC51 8 bit timer mode control register 51 139 TOC0 16 bit timer output control register 0 111 TXS0 Transmit shift register 188 W WDCS Watchdog timer clock select register 164 WDTM Watchdog timer mode register 165 WTM Watch timer mode control register 157 ...

Page 349: ...nal clock and capture trigger addition of description of sampling clock for noise elimination Modification of input buffer to schmitt triggered input in block diagram of UART CHAPTER 13 SERIAL INTERFACE UART0 Modification of register symbols and bit names CHAPTER 14 SERIAL Automatic data transmit receive address pointer ADTP0 INTERFACE SIO1 Automatic data transmit receive control register ADTC0 Au...

Page 350: ...350 Preliminary User s Manual U13420EJ2V0UM00 MEMO ...

Page 351: ... 02 2719 5951 Address North America NEC Electronics Inc Corporate Communications Dept Fax 1 800 729 9288 1 408 588 6130 Europe NEC Electronics Europe GmbH Technical Documentation Dept Fax 49 211 6503 274 South America NEC do Brasil S A Fax 55 11 6465 6829 Asian Nations except Philippines NEC Electronics Singapore Pte Ltd Fax 65 250 3583 Japan NEC Semiconductor Technical Hotline Fax 044 548 7900 I ...

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