NEC mPD780065 Series, Preliminary User'S Manual

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CHAPTER 5 CLOCK GENERATOR
Preliminary User’s Manual U13420EJ2V0UM00
5.5 Clock Generator Operations
The clock generator generates the following various types of clocks and controls the CPU operating mode including
the standby mode.
• Main system clock f
X
• Subsystem clock f
XT
• CPU clock f
CPU
• Clock to peripheral hardware
The following clock generator functions and operations are determined with the processor clock control register
(PCC).
(a) Upon generation of RESET signal, the lowest speed mode of the main system clock (3.81
µ
s @ 8.38-MHz
oscillation) is selected (PCC = 04H). Main system clock oscillation stops while low level is applied to RESET
pin.
(b) With the main system clock selected, one of the five CPU clock types (0.24
µ
s. 0.48
µ
s, 0.95
µ
s, 1.91
µ
s, 3.81
µ
s, @ 8.38-MHz operation) can be selected by setting the PCC.
(c) With the main system clock selected, two standby modes, the STOP and HALT modes, are available. To reduce
current consumption in the STOP mode, the subsystem clock feedback resistor can be disconnected to stop the
subsystem clock.
(d) The PCC can be used to select the subsystem clock and to operate the system with low-current consumption
(122
µ
s @ 32.768-kHz operation).
(e) With the subsystem clock selected, main system clock oscillation can be stopped with the PCC. The HALT mode
can be used. However, the STOP mode cannot be used. (Subsystem clock oscillation cannot be stopped.)
(f) The main system clock is divided and supplied to the peripheral hardware. The subsystem clock is supplied to
the watch timer and clock output functions only. Thus the watch function and the clock output function can also
be continued in the standby state. However, since all other peripheral hardware operate with the main system
clock, the peripheral hardware also stops if the main system clock is stopped. (Except external input clock
operation)