NEC mPD780065 Series, Preliminary User'S Manual

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168
CHAPTER 9 WATCHDOG TIMER
Preliminary User’s Manual U13420EJ2V0UM00
9.4.2 Interval timer operation
The watchdog timer operates as an interval timer which generates interrupt requests repeatedly at an interval of
the preset count value when bit 3 (WDTM3) and bit 4 (WDTM4) of the watchdog timer mode register (WDTM) are
set to 1 and 0, respectively.
The interval time of interval timer is selected with bits 0 to 2 (WDCS0 to WDCS2) of the watchdog timer clock select
register (WDCS). When 1 is set to bit 7 (RUN) of WDTM, the watchdog timer operates as the interval timer.
When the watchdog timer operated as the interval timer, the interrupt mask flag (WDTMK) and priority specify flag
(WDTPR) are validated and the maskable interrupt request (INTWDT) can be generated. Among maskable interrupts,
INTWDT has the highest priority at default.
The interval timer continues operating in the HALT mode but it stops in STOP mode. Thus, set RUN to 1 before
the STOP mode is set, clear the interval timer and then execute the STOP instruction.
Cautions 1. Once bit 4 (WDTM4) of WDTM is set to 1 (this selects the watchdog timer mode), the interval
timer mode is not set unless RESET input is applied.
2. The interval time just after setting by WDTM may be shorter than the set time by a maximum
of 0.5%.
3. When the subsystem clock is selected for CPU clock, watchdog timer count operation is
stopped.
Table 9-5. Interval Timer Interval Time
Interval Time
2
12
×
1/f
X
(489
µ
s)
2
13
×
1/f
X
(978
µ
s)
2
14
×
1/f
X
(1.96 ms)
2
15
×
1/f
X
(3.91 ms)
2
16
×
1/f
X
(7.82 ms)
2
17
×
1/f
X
(15.6 ms)
2
18
×
1/f
X
(31.3 ms)
2
20
×
1/f
X
(125 ms)
Remarks 1. f
X
: Main system clock oscillation frequency
2. Figures in parentheses are for operation with f
X
= 8.38 MHz.