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CHAPTER 6 16-BIT TIMER/EVENT COUNTER
Preliminary User’s Manual U13420EJ2V0UM00
(10) Capture operation
If TI00 is specified as the valid edge of the count clock, capture operation by the capture register specified as
the trigger for TI00 is not possible.
(11) Compare operation
<1>
When 16-bit timer capture/compare register (CR00/CR01) is overwritten during timer operation, match
interrupt may be generated or clear operation may not be performed normally if that value is close to the
timer value and larger than the timer value.
<2>
Capture operation may not be performed for CR00/CR01 set in compare mode even if a capture trigger
has been input.
(12) Edge detection
<1>
To secure capture of the capture trigger, a pulse more than twice the length of the count clock to be selected
is required. When TI00 is high level just after system reset, the falling edge is detected just after the TM0
operation is permitted. Be aware of this if using pull-up resistors.
<2>
The sampling clock for noise elimination differs according to whether the TI00 valid edge is used as a count
clock or as a capture trigger. Sampling is performed by the count clock selected with f
X
/2
3
for the former,
or with prescaler mode register 0 (PRM0) for the latter. Because this counter does not operate until the
valid level is detected twice by sampling the valid edge, short-pulse width noise can be eliminated.
Summary of Contents for mPD780065 Series
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