NEC mPD780065 Series, Preliminary User'S Manual

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CHAPTER 3 CPU ARCHITECTURE
Preliminary User’s Manual U13420EJ2V0UM00
3.1.2 Internal data memory space
The
µ
PD780065 Subseries incorporates the following RAM.
(1) Internal high-speed RAM
The internal high-speed RAM has an 1024
×
8-bit (FB00H to FEFFH) configuration. Four general-purpose register
banks composed of eight 8-bit registers are allocated to the 32-byte area of FEE0H to FEFFH.
The internal high-speed RAM can also be used as a stack memory.
(2) Internal buffer RAM
An internal buffer RAM is allocated to the 32-byte area of FAC0H to FADFH. The internal buffer RAM is used
for storing transmitted/received data to/from the serial interface (SIO1) (a 3-wire serial I/O mode with automatic
transmission/reception function). When the internal buffer RAM is not used in the 3-wire serial I/O mode with
automatic transmission/reception function, it is used as a conventional RAM.
3.1.3 Special Function Register (SFR) area
An on-chip peripheral hardware special-function register (SFR) is allocated to the area FF00H to FFFFH. (Refer
to 3.2.3 Special Function Register (SFR) Table 3-3. Special Function Register List.)
Caution Do not access addresses where the SFR is not assigned.
3.1.4 External memory space
The external memory space is accessible via the memory expansion mode register (MEM). The external memory
space can store programs, table data, etc., and allocate peripheral devices.