NEC mPD703128 Preliminary User'S Manual Download Page 248 | Manualshive

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248

Chapter 9

Clock Generator

Preliminary User’s Manual U15839EE1V0UM00

9.3.6 SSCG Frequency Modulation Control Register (SCFMC)

This is a 5-bit register that controls the frequency modulation of SSCG in dithering mode and the post
scale factor of the SSCG.

This register can be read or written in 8- or 1-bit units.

Figure 9-7:

SSCG Frequency Modulation Control Register (SCFMC)

Cautions: 1. This register can only be written if the SSCG enable bit SCEN is cleared.

2. After the first initialization of the SCFMC register, no further write access is

allowed until the occurrence of a Reset or the release of a power-save mode hap-
pened. Afterwards a power-save mode has been released, one bit is allowed to be
changed.

7

6

5

4

3

2

1

0

Address

Initial
value

SCFMC

0

SCPS1

SCPS0

SCFMC4

SCFMC3

SCFMC2

SCFMC1

SCFMC0

FFFFF82AH

0AH

Bit name

Function

SCPS1,

SCPS0

Frequency modulation control bits

SCPS1 SCPS0

Post Scale Factor of the SSCG

0

0

f

XX

/3

Note: If SSCG operation is required for the CPU/BCU clock supply, the setting

of the bits SCPS0, SCPS1 = 0x00 is not supported at any time.
Therefore, the setting of these bits must be modified before the SSCG is
enabled.

0

1

f

XX

/4

1

0

f

XX

/6

1

1

f

XX

/8

SCFMC4

to

SCFMC0

Specifies the dithering frequency

The initial setting (0x0A) of these bits must not be changed at any time.

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Summary of Contents for mPD703128

Page 1: ...reliminary User s Manual V850E CA2TM JUPITER 32 16 bit Romless Microcontroller Hardware µPD703128 µPD703129 Document No U15839EE1V0UM00 Date Published August 2003 NEC Corporation 2003 Printed in Germany ...

Page 2: ...Note No connection for CMOS device inputs can be cause of malfunction If no connection is provided to the input pins it is possible that an internal input level may be generated due to noise etc hence causing malfunction CMOS devices behave differently than Bipolar or NMOS devices Input levels of CMOS devices must be fixed high or low by using a pull up or pull down circuitry Each unused pin shoul...

Page 3: ...hereof cannot be eliminated entirely To minimize risks of damage to property or injury including death to persons arising from defects in NEC Electronics products customers must incorporate sufficient safety measures in their design such as redundancy fire containment and anti failure features NEC Electronics products are classified into the following three quality grades Standard Special and Spec...

Page 4: ...8 588 6000 800 366 9782 Fax 408 588 6130 800 729 9288 NEC Electronics Europe GmbH Duesseldorf Germany Tel 0211 65 03 01 Fax 0211 65 03 327 Sucursal en España Madrid Spain Tel 091 504 27 87 Fax 091 504 28 60 Succursale Française Vélizy Villacoublay France Tel 01 30 67 58 00 Fax 01 30 67 58 99 NEC Electronics Hong Kong Ltd Hong Kong Tel 2886 9318 Fax 2886 9022 9044 NEC Electronics Hong Kong Ltd Seou...

Page 5: ...sed as follows Weight in data notation Left is high order column right is low order column Active low notation xxx pin or signal name is over scored or xxx slash before signal name Memory map address High order at high stage and low order at low stage Note Explanation of Note in the text Caution Item deserving extra attention Remark Supplementary explanation to the text Numeric notation Binary XXX...

Page 6: ...6 Preliminary User s Manual U15839EE1V0UM00 ...

Page 7: ...6 3 4 3 Wrap around of CPU address space 67 3 5 Memory Map 68 3 5 1 Area 70 3 5 2 Recommended use of address space 75 3 5 3 Peripheral I O Registers 76 3 5 4 Programmable peripheral I O registers 83 3 6 Specific Registers 103 3 6 1 Command Register PRCMD 104 3 6 2 Peripheral Command Register PHCMD 105 3 6 3 Peripheral Status Register PHS 106 3 6 4 Internal peripheral function wait control register...

Page 8: ...167 Chapter 7 DMA Functions DMA Controller 169 7 1 Features 169 7 2 Control Registers 170 7 2 1 DMA source address registers H0 to H3 DSAH0 to DSAH3 170 7 2 2 DMA destination address registers H0 to H3 DDAH0 to DDAH3 172 7 2 3 DMA transfer count registers 0 to 3 DBC0 to DBC3 174 7 2 4 DMA addressing control registers 0 to 3 DADC0 to DADC3 175 7 2 5 DMA channel control registers 0 to 3 DCHC0 to DCH...

Page 9: ...nterrupt Edge Detection Control Registers 223 8 5 Software Exception 227 8 5 1 Operation 227 8 5 2 Restore 228 8 5 3 Exception status flag EP 229 8 6 Exception Trap 230 8 6 1 Illegal opcode definition 230 8 6 2 Debug trap 232 8 7 Multiple Interrupt Processing Control 234 8 8 Interrupt Response Time 236 8 9 Periods in Which Interrupts Are Not Acknowledged 237 Chapter 9 Clock Generator 239 9 1 Featu...

Page 10: ...0 3 4 Control registers 313 10 3 5 Output delay operation 321 10 3 6 Explanation of basic operation 322 10 3 7 Operation in Free run mode 324 10 3 8 Match and clear mode 335 10 3 9 Edge noise elimination 346 10 3 10Precautions Timer Gn 347 Chapter 11 Watch Timer 349 11 1 Function 349 11 2 Configuration 350 11 3 Watch Timer Control Register 350 11 4 Operations 352 11 4 1 Selection of the Watch Time...

Page 11: ...2 14 3 5 CAN Module Registers 485 14 4 Operating Considerations 509 14 4 1 Rules to be observed for correct baud rate settings 509 14 4 2 Example for baudrate setting of CAN module 510 14 4 3 Ensuring data consistency 512 14 4 4 Operating states of the CAN modules 514 14 4 5 Initialisation routines 515 Chapter 15 A D Converter 523 15 1 Features 523 15 2 Configuration 524 15 3 Control Registers 527...

Page 12: ...S 577 16 3 12Port CT 579 16 3 13Port CM 581 Chapter 17 RESET 583 17 1 Reset Overview 583 17 2 Features 583 17 3 Pin Functions 583 17 4 Reset by RESET Pin 585 17 5 Reset by Watchdog Timer 587 17 6 Reset Output 587 17 7 Initialization 588 Appendix A List of Instruction Sets 589 Appendix B Index 601 ...

Page 13: ...within Word 117 Figure 4 6 Little Endian Addresses within Word 117 Figure 4 7 Example of Wait Insertion 133 Figure 5 1 Example of Connection to SRAM 138 Figure 5 2 SRAM External ROM External I O Access Timing 1 6 139 Figure 5 3 Example of Page ROM Connections 146 Figure 5 4 On Page Off Page Judgment during Page ROM Connection 1 2 147 Figure 5 5 Page ROM Configuration Register PRC 149 Figure 5 6 Pa...

Page 14: ...Interrupt Is Being Processed 1 2 213 Figure 8 9 Example of Processing Interrupt Requests Simultaneously Generated 215 Figure 8 10 Interrupt Control Register xxIC 216 Figure 8 11 Interrupt Mask Registers 0 to 3 IMR0 to IMR3 219 Figure 8 12 In Service Priority Register ISPR 220 Figure 8 13 Maskable Interrupt Status Flag ID 220 Figure 8 14 Port Interrupt Input Circuit P52 P53 P61 P62 P63 P64 221 Figu...

Page 15: ... Operation 1 2 302 Figure 10 24 Block Diagram of Timer Gn 308 Figure 10 25 Timer Gn Counter 0 Value Registers TMGn0 310 Figure 10 26 Timer Gn Counter 1 Value Registers TMGn1 310 Figure 10 27 Timer Gn counter TMGn0 assigned Capture Compare Register GCCn0 311 Figure 10 28 Timer Gn counter TMGn1 assigned Capture Compare Register GCCn5 311 Figure 10 29 Timer Gn free assignable Capture Compare Register...

Page 16: ...ception Completion Interrupt Timing 380 Figure 13 12 When Reception Error Interrupt Is Separated from INTSRn Interrupt ISRM Bit 0 381 Figure 13 13 When Reception Error Interrupt Is Included in INTSRn Interrupt ISRM Bit 1 381 Figure 13 14 Noise Filter Circuit 383 Figure 13 15 Timing of RXD5n Signal Judged as Noise 383 Figure 13 16 Baud Rate Generator BRG Configuration of UART5n n 0 1 384 Figure 13 ...

Page 17: ...gure 14 20 Internal CAN Test Bus Structure 466 Figure 14 21 CAN Interrupt Pending Registers CCINTPL CCINTPH 467 Figure 14 22 CAN Global Interrupt Pending Register CGINTP 1 2 468 Figure 14 23 CAN 1 to 4 Interrupt Pending Registers C1INTP to C4INTP 1 2 470 Figure 14 24 Message Identifier Registers L00 to L31 and H00 to H31 M_IDL00 to M_IDL31 M_IDH00 to M_IDH31 472 Figure 14 25 Message Configuration ...

Page 18: ...Configuration 546 Figure 16 2 Type A Block Diagram 551 Figure 16 3 Type B Block Diagram 552 Figure 16 4 Type C Block Diagram 553 Figure 16 5 Type D Block Diagram 554 Figure 16 6 Type E Block Diagram 555 Figure 16 7 Port 1 P1 556 Figure 16 8 Port 1 Mode Register PM1 557 Figure 16 9 Port 1 Mode Control Register PMC1 558 Figure 16 10 Port 2 P2 559 Figure 16 11 Port 2 Mode Register PM2 560 Figure 16 1...

Page 19: ...trol Register PMCCT 580 Figure 16 38 Port CM PCM 581 Figure 16 39 Port CM Mode Register PMCM 582 Figure 16 40 Port CM Mode Control Register PMCCM 582 Figure 17 1 Reset signal acknowledgment 585 Figure 17 2 Reset at power on 586 Figure A 1 How to Read Instruction Set List 589 ...

Page 20: ...20 Preliminary User s Manual U15839EE1V0UM00 ...

Page 21: ...in WATCH Mode 261 Table 9 10 Operation after SUB WATCH mode release by interrupt request 262 Table 9 11 Operating States in STOP Mode 265 Table 10 1 Timer C Configuration List 274 Table 10 2 TOC0 Output Control 291 Table 10 3 Timer Dn Configuration List n 0 1 297 Table 10 4 Timer Gn Configuration List 309 Table 10 5 Interrupt output and timer output states dependent on the register setting values ...

Page 22: ...me Handling upon Reception into a Transmit Message Buffer 451 Table 14 16 CAN Message Processing by TRQ and RDY Bits 476 Table 14 17 Address Offsets of the CAN 1 to 4 Mask Registers 486 Table 15 1 A D Converter Configuration 524 Table 15 2 Register format of A D Converter Control Register 527 Table 16 1 Functions of each port 547 Table 16 2 Port Pin Functions 548 Table 17 1 Operation Status of eac...

Page 23: ...50E CPU supports the RISC instruction set and through the use of basic instructions that can each be executed in 1 clock period and an optimized pipeline achieves marked improvements in instruction execution speed In addition in order to make it ideal for use in digital servo control a 32 bit hardware multiplier enables this CPU to support multiply instructions saturated multiply instructions bit ...

Page 24: ...ciative 4K Bytes Boot Loader Internal Boot Loader for downloading Flash Self Programming routines into RAM Support of virgin programming for external flash memories Clock Generator Internal Spread Spectrum PLL CPU Core BCU clock supply Internal PLL Peripheral clock supply 4 fold PLL Frequency range up to 32 MHz Crystal frequency range 4 MHz 5 MHz Internal Slow Running clock oscillator Built in pow...

Page 25: ...t counter 2 channel 16 bit multi purpose timer counter 1 channel 16 bit OS timer 2 channel Watch timer 1 channel Watchdog timer 1 channel Interrupts and exceptions Non maskable interrupts 2 source Maskable interrupts 57 sources µPD703128 63 sources µPD703129 Software exceptions 32 sources Exception trap 1 source Clock Correction of Sub Oscillator Package 144 QFP 0 5 mm pin pitch CMOS technology Re...

Page 26: ...of sophisticated periph eral functions and CAN network support is required 1 4 Ordering Information Part number Package Internal ROM bytes Internal RAM bytes Full CAN RAM bytes Channels µPD703128 A 144 pin QFP fine pitch 20 20 mm Rom less 12 K 1K 32 message buffers 2 FCAN Channels µPD703129 A 144 pin QFP fine pitch 20 20 mm Rom less 16 K 1K 32 message buffers 4 FCAN Channels µPD703129 A1 144 pin Q...

Page 27: ...P81 ANI9 P82 ANI10 P83 ANI11 MODE0 P97 AVREF AVSS AVDD VDD30 VSS30 P94 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 A0 PCT1 U...

Page 28: ...ator Power Supply SI00 SI01 SI02 Serial Input CVSS Clock Generator Ground SO00 SO01 SO02 Serial Output GND30 to GND36 Ground for 3 V Power Supply TIG00 to TIG05 TIG10 to TIG05 TIC00 TIC01 Timer Input GND50 to GND52 Ground for 5 V Power Supply TOG01 to TOG04 TOG11 to TOG14 TOC00 Timer Output INTP0 to INTP5 External interrupt request TXD50 to TXD51 Transmit Data Output INTPn0 INTPn5 INTP2n Interrupt...

Page 29: ...r TMC 16 bit Timer TMG1 TIG10 to TIC15 TOG11 to TOG14 TIC00 TIC01 TOC00 16 bit Timer TMD1 16 bit Timer TMD0 FCAN2 FCAN1 FCRXD1 FCTXD1 FCRXD2 FCTXD2 UART51 UART50 RXD50 TXD50 RXD51 TXD51 CSI00 SI00 SO00 SCK00 CSI01 SI01 SO01 SCK01 CSI02 SI02 SO02 SCK02 ANI0 ANI11 Watchdog Timer Watch Timer X1 X2 RESET RESOUT Oscillator and Clock Generator with Spread Spectrum PLL PLL Ports 10 bit ADC 12 channels P1...

Page 30: ... 8 to 128 bytes b DMA controller DMAC Instead of the CPU this controller controls data transfer between memory and I O There is one address mode 2 cycle transfer and there are three bus modes single transfer single step transfer and block transfer 3 ROM The µPD703128 µPD703129 is a ROM less MCU containing a 16 bit wide non multiplexed bus interface to be able to fetch instructions data from extern...

Page 31: ... 11 Ports As shown below the following ports have general port functions and control pin functions Port Port Function Control Function Port 1 8 bit input output Serial interface input output Port 2 8 bit input output Serial interface input output Port 3 6 bit input output Real time pulse unit input output external interrupt input PWM output Port 4 6 bit input output Real time pulse unit input outp...

Page 32: ...32 Preliminary User s Manual U15839EE1V0UM00 MEMO ...

Page 33: ...XD1 P11 FCTXD1 P12 FCRXD2 P13 FCTXD2 P14 FCRXD3Note P15 FCTXD3Note P16 RXD1 P17 TXD1 P20 I O Port 2 8 bit input output port SI0 P21 SO0 P22 SCK0 P23 SI1 P24 SO1 P25 SCK1 P26 RXD0 P27 TXD0 P30 I O Port 3 6 bit input output port TIG00 INTP00 P31 TIG01 TOG01 P32 TIG02 TOG02 P33 TIG03 TOG03 P34 TIG04 TOG04 P35 TIG05 INTP05 P40 I O Port 4 6 bit input output port TIG10 INTP10 P41 TIG11 TOG11 P42 TIG12 T...

Page 34: ...NTP0 P62 INTP1 P63 INTP2 P64 INTP3 P65 SI2 P66 SO2 P67 SCK2 P70 I Port 7 8 bit input port ANI0 P71 ANI1 P72 ANI2 P73 ANI3 P74 ANI4 P75 ANI5 P76 ANI6 P77 ANI7 P80 I Port 8 4 bit input port ANI8 P81 ANI9 P82 ANI10 P83 ANI11 P90 I O Port 9 8 bit input output port P91 P92 P93 P94 P95 P96 P97 Table 2 1 Port Pins 2 3 Port I O Function Alternate Note CAN module 3 and CAN module 4 are available in the der...

Page 35: ...PAH5 A21 PAH6 A22 PAH7 A23 PCS0 I O Port CS 3 bit input output port CS0 PCS3 CS3 PCS4 CS4 PCT0 I O Port CT 3 bit input output port LWR PCT1 UWR PCT4 RD PCM0 I O Port CM 1 bit input output port WAIT Table 2 1 Port Pins 3 3 Port I O Function Alternate Note CAN module 3 and CAN module 4 are available in the derivatives µPD703129 A and µPD703129 A1 only ...

Page 36: ...e input for A D converter NMI input non maskable interrupt input P60 ANI0 ANI7 input analog input to A D converter P77 to P70 ANI8 ANI11 input analog input to A D converter P80 to P83 SI00 input serial receive data input to CSI00 CSI02 P20 SI01 P23 SI02 P65 SO00 output serial transmit data output from CSI00 CSI02 P21 SO01 P24 SO02 P66 SCK00 I O serial clock I O from to CSI00 CSI02 P22 SCK01 P25 SC...

Page 37: ... 0 capture input 3 P33 TOG03 TIG04 input Timer G 0 capture input 4 P34 TOG04 TIG05 input Timer G 0 capture input 5 P35 TOG05 TOG01 output Timer G 0 compare output 1 P31 TIG01 TOG02 output Timer G 0 compare output 2 P32 TIG02 TOG03 output Timer G 0 compare output 3 P33 TIG03 TOG04 output Timer G 0 compare output 4 P34 TIG04 TIG10 input Timer G 1 capture input 0 P40 INTP10 TIG11 input Timer G 1 capt...

Page 38: ...trobe signal for lower byte bit 0 bit 7 PCT0 UWR output Write strobe signal for upper byte bit 0 bit 7 PCT1 RD output Read strobe signal for external bus PCT4 WAIT input Control signal input for external bus PCM0 CS0 output Chip select output for external bus PCS0 CS3 PCS3 CS4 PCS4 Table 2 2 Non Port Pins 3 3 Pin Name I O Function Alternate Notes 1 All VDD3 pins have to be connected to each other ...

Page 39: ...rate INTP15 to INTP10 N A operate operate operate operate operate operate INTP21 to INTP20 N A operate operate operate operate operate operate INTP5 to INTP0 N A operate operate operate operate operate operate NMI N A operate operate operate operate operate operate TOG04 to TOG01 N A HOLD HOLD HOLD HOLD operate operate TOG14 to TOG11 N A HOLD HOLD HOLD HOLD operate operate TOC0 N A HOLD HOLD HOLD ...

Page 40: ...control register PMC1 a Port mode P10 to P17 can be set to input or output in 1 bit units using the port 1 mode register PM1 b Control mode P10 to P17 can be set to port or control mode in 1 bit units using PMC1 c CTXD1 CTXD2 CTXD3 Transmit data for controller area network Output This pin outputs FCAN serial transmit data d CRXD1 CRXD2 CRXD3 Receive data for controller area network Input This pin ...

Page 41: ...2 mode control register PMC2 a Port mode P20 to P27 can be set to input or output in 1 bit units using the port 2 mode register PM2 b Control mode P20 to P27 can be set to port or control mode in 1 bit units using PMC2 c SO0 SO1 Serial output Output These pins output CSI0 and CSI1 serial transmit data d SI0 SI1 Serial input Input These pins input CSI0 and CSI1 serial receive data e SCK0 SCK1 Seria...

Page 42: ...t or control mode can be selected for each bit and specified by the port 3 mode control register PMC3 a Port mode P30 to P35 can be set to input or output in 1 bit units using the port 3 mode register PM3 b Control mode P30 to P35 can be set to port or control mode in 1 bit units using PMC3 c TOG01 to TOG04 Timer output Output These pins output a timer G 0 pulse signal d TIG00 to TIG05 Timer input...

Page 43: ...t or control mode can be selected for each bit and specified by the port 4 mode control register PMC4 a Port mode P40 to P45 can be set to input or output in 1 bit units using the port 4 mode register PM4 b Control mode P40 to P45 can be set to port or control mode in 1 bit units using PMC4 c TOG11 to TOG14 Timer output Output These pins output a timer G 1 pulse signal d TIG10 to TIG15 Timer input...

Page 44: ...0 to P56 can be set to input or output in 1 bit units using the port 5 mode register PM5 b Control mode P50 to P56 can be set to port or control mode in 1 bit units using PMC5 c TO0 Timer output Output This pin output a timer C pulse signal d TI0 TI1 Timer input Input These pins are the timer C external capture trigger input pins e CTXD4 Transmit data for controller area network Output This pin ou...

Page 45: ...e control register PMC6 a Port mode P60 to P67 can be set to input or output in 1 bit units using the port 6 mode register PM6 b Control mode P60 to P67 can be set to port or control mode in 1 bit units using PMC6 c SO2 Serial output Output This pin output CSI2 serial transmit data d SI2 Serial input Input This pin input CSI2 serial receive data e SCK2 Serial clock Input output This pin is the CSI...

Page 46: ...are not switchable c ANI0 to ANI11 Analog Input 0 to 11 These are the analog input pins for the A D converter Connect a capacitor between AVDD and AVSS to prevent noise related operation faults Also do not apply voltage that is outside the range for AVDD and AVSS to pins that are being used as inputs for the A D converter If it is possible for noise above the AVDD range or below the AVSS to enter ...

Page 47: ...the address bus on an external access 10 PCS0 PCS3 PCS4 Port CS Input output Port CS is a 3 bit input output port in which input or output can be set in 1 bit units Besides functioning as a port in control mode it operates as a chip select control signal output when memory is accessed externally An operation mode of port or control mode can be selected for each bit and specified by the port CS mod...

Page 48: ...t This is a strobe signal that shows that the executing bus cycle is a write cycle for SRAM external ROM or an external peripheral I O area e RD Read strobe Output This is a strobe signal that shows that the executing bus cycle is a read cycle for SRAM external ROM or external peripheral I O It is inactive in an idle state TI 12 PCM0 Port CM Input output Port CM is a 1 bit input output port in whi...

Page 49: ...o release a standby mode HALT IDLE Watch Sub Watch software STOP 16 RESOUT Reset Output RESOUT output is a 3 3 V reset output signal It is the internal system reset output RESOUT is active low in case of an external reset by RESET input pin or internal reset by watch dog timer If the RESOUT output pin is connected to a RESET IN of an external flash memory it can be used to terminate an embedded er...

Page 50: ...ground pins for the 3 3 V power supply 26 AVDD Analog power supply This is the analog positive power supply pin for the A D converter 27 AVSS Analog ground This is the ground pin for the A D converter 28 AVREF Analog reference voltage Input This is the reference voltage supply pin for the A D converter 29 A0 to A15 Address output Output These pins are the address output pins 30 D0 to D15 Data inpu...

Page 51: ...5 or VSS5 via a resistor For output leave open P11 FCTXD1 P12 FCRXD2 P13 FCTXD2 P14 FCRXD3 P15 FCTXD3 P16 RXD51 P17 TXD51 P20 SI00 5 K P21 SO00 P22 SCK00 P23 SI01 P24 SO01 P25 SCK01 P26 RXD50 P27 TXD50 P30 TIG00 INTP00 5 K P31 TIG01 TOG01 P32 TIG02 TOG02 P33 TIG03 TOG03 P34 TIG04 TOG04 P35 TIG05 INTP05 P40 TIG10 INTP10 5 K P41 TIG11 TOG11 P42 TIG12 TOG12 P43 TIG13 TOG13 P44 TIG14 TOG14 P45 TIG15 I...

Page 52: ...input individually connect to VDD5 or VSS5 via a resistor For output leave open P81 ANI9 P82 ANI10 P83 ANI11 P90 5 K For input individually connect to VDD5 or VSS5 via a resistor For output leave open P91 P92 P93 P94 P95 P96 P97 PAH0 A16 5 For input individually connect to VDD5 or VSS5 via a resistor For output leave open PAH1 A17 PAH2 A18 PAH3 A19 PAH4 A20 PAH5 A21 PAH6 A22 PAH7 A23 PCS0 CS0 5 Fo...

Page 53: ...IN11 9 C MODE0 2 MODE1 2 connect to VSS5X via a resistor MODE2 2 VDD3X RESET 2 RESOUT 3 connect to VDD3x via a resistor X2 16 Please refer to the datasheet XT1 16 Please refer to the data sheet XT2 16 Please refer to the data sheet AVDD VDD5X AVREF AVDD AVSS VSS5X A0 to A15 4 D0 to D15 5 Table 2 4 Types of Pin I O Circuit and Connection of Unused Pins 3 3 Pin I O Circuit Type Recommended connectio...

Page 54: ...ype 4 Data Output disable V P ch N ch IN OUT DD Type 5 data output disable input enable VDD P ch IN OUT N ch Type 5 K Data Output disable V P ch N ch IN OUT DD VSS Input enable Type 9 C P ch N ch Input enable VREF IN Comparator threshold voltage AVSS Type 16 P ch feedback cut off XT1 XT2 Data V P ch N ch OUT DD VSS ...

Page 55: ...ine control 3 1 Features Minimum instruction cycle 31 25 ns internal 32 MHz operation Memory space Program space 64 MB linear Data space 4 GB linear Thirty two 32 bit general registers Internal 32 bit architecture Five stage pipeline control Multiplication division instructions Saturated operation instructions One clock 32 bit shift instruction barrel shifter Long short instruction format Four typ...

Page 56: ...23 r24 r25 r26 r27 r28 r29 r30 r31 Zero Register Reserved for Assembler Interrupt Stack Pointer Stack Pointer SP Global Pointer GP Text Pointer TP Element Pointer EP Link Pointer LP PC Program Counter PSW Program Status Word ECR Interrrupt Source Register FEPC FEPSW Status Saving Register during NMI Status Saving Register during NMI EIPC EIPSW Status Saving Register during interrupt Status Saving ...

Page 57: ...een used 2 Program counter This register holds the instruction address during program execution The lower 26 bits of this register are valid and bits 31 to 26 are fixed to 0 If a carry occurs from bit 25 to 26 it is ignored Bit 0 is fixed to 0 and branching to an odd address cannot be performed Figure 3 2 Program Counter PC Table 3 1 Program Registers Name Usage Operation r0 Zero register Always h...

Page 58: ... CTPC use the even value bit 0 0 Remark O Access allowed Access prohibited Table 3 2 System Register Numbers No System Register Name Operand Specification LDSR Instruction STSR Instruction 0 Status saving register during interrupt EIPC Note 1 O O 1 Status saving register during interrupt EIPSW O O 2 Status saving register during NMI FEPC O O 3 Status saving register during NMI FEPSW O O 4 Interrup...

Page 59: ... U15839EE1V0UM00 Figure 3 3 Interrupt Source Register ECR Bit Position Bit Name Function 31 to 16 FECC Exception code of non maskable interrupt NMI 15 to 0 EICC Exception code of exception maskable interrupt 31 0 ECR FECC EICC After reset 00000000H 1615 ...

Page 60: ...peration result of a saturated operation processing instruction is sat urated due to overflow Due to the cumulative flag if the operation result is saturated by the saturation operation instruction this bit is set 1 but is not cleared 0 even if the operation results of subsequent instructions are not saturated To clear 0 this bit load the data in PSW Note that in a general arithmetic operation thi...

Page 61: ...esult Status of Operation Result Flag Status Saturation Processed Operation Result SAT OV S Maximum positive value exceeded 1 1 0 7FFFFFFFH Maximum negative value exceeded 1 1 1 80000000H Positive maximum not exceeded Retains the value before operation 0 0 Operation result itself Negative maximum not exceeded 1 ...

Page 62: ...Boot Loader offering the possibility to download programming algorithms and the new ROM code itself To be able to use this feature there s no need to have already a dedicated boot software being programmed in the external flash memory It is possible to program external flash memory devices even in the case that the flash memory is completely erased Support of Virgin programming The complete Boot L...

Page 63: ...o program erase the contents of the external memory device it is required to enable a Flash Pro gramming Mode The following operation modes are generally available for the V850E CA2 Jupiter device a µPD703128 µPD703129 Remarks 1 L Low level input 2 H High level input Table 3 4 Operation Modes MODE2 MODE1 MODE0 Operation Mode L L L ROM less mode 0 Direct Normal operation mode L L H ROM less mode 1 ...

Page 64: ...face Data and instructions in the internal boot ROM cannot be accessed or fetched 3 FLASH Programming Mode 0 In FLASH Programming Mode 0 external flash memory programming is enabled by starting from the internal boot ROM of Jupiter This boot ROM contains bootstrap code to download FLASH pro gramming routines into iRAM and execute these routines Address masking on the external mem ory interface is ...

Page 65: ...up to 4 GB of linear address space data space during operand addressing data access Also in instruction address addressing a maximum of 64 MB of linear address space program space is supported Figure 3 5 shows the CPU address space Figure 3 5 CPU Address Space FFFF FFFFH 0400 0000H 03FF FFFFH 0000 0000H Data area 4 Gbyte linear Program area 64 Mbyte linear CPU address space ...

Page 66: ...s the image of the virtual addressing space Physical address x000 0000H can be seen as CPU address 0000 0000H and in addition can be seen as address 0400 0000H address 0800 0000H address F800 0000H or address FC00 0000H Figure 3 6 Image on Address Space FFFF FFFFH FC00 0000H FBFF FFFFH 0000 0000H Image Image Image Internal RAM Peripheral I O External memory Physical address space x3FF FFFFH x000 0...

Page 67: ...ous like this Figure 3 7 Wrap around of Program Space Caution No instruction can be fetched from the 4 KB area of 03FF F000H to 03FF FFFFH because this area is defined as peripheral I O area Therefore do not execute any branch address calculation in which the result will reside in any part of this area 2 Data space The result of operand address calculation that exceeds 32 bits is ignored Therefore...

Page 68: ...reserves areas as shown in Figure 3 9 1 For µPD703128 Figure 3 9 Memory Map µPD703128 A x3FF FFFFH Internal peripheral I O area Internal RAM area External memory area Single chip mode 64 Mbytes 4 Kbytes x3FF F000H x3FF EFFFH x000 0000H x3FF B000H x3FF AFFFH x3FF 8000H x3FF 7FFFH 12 Kbytes 16 Kbytes ...

Page 69: ...or µPD703129 Figure 3 10 Memory Map µPD703129 A µPD703129 A1 x3FF FFFFH Internal peripheral I O area Internal RAM area External memory area Single chip mode 64 Mbytes 4 Kbytes x3FF F000H x3FF EFFFH x000 0000H x3FF C000H x3FF BFFFH x3FF 8000H x3FF 7FFFH 16 Kbytes 12 Kbytes ...

Page 70: ...led an interrupt exception table which is located in the external ROM area When an interrupt exception request is accepted execution jumps to the handler address and the program written at that memory is executed Table 3 5 shows the sources of interrupts exceptions and the corresponding addresses Table 3 5 Interrupt Exception Table 1 3 Start Address of Interrupt Exception Table Interrupt Exception...

Page 71: ...rsion end 0000 0260H MAC Interrupt CGINTP 1 2 0000 0270H CAN1 Receive Interrupt 0000 0280H CAN1 Transmit Interrupt 0000 0290H CAN1 Error Interrupt 0000 02A0H CAN2 Receive Interrupt 0000 02B0H CAN2 Transmit Interrupt 0000 02C0H CAN2 Error Interrupt 0000 02D0H CAN3 Receive Interrupt 0000 02E0H CAN3 Transmit Interrupt 0000 02F0H CAN3 Error Interrupt 0000 0300H CAN4 Receive Interrupt 0000 0310H CAN4 T...

Page 72: ...D0H DMA Channel 1 transfer completed 0000 03E0H DMA Channel 2 transfer completed 0000 03F0H DMA Channel 3 transfer completed 0000 0400H DMA Overflow 0000 0410H P30 0000 0420H P35 0000 0430H P40 0000 0440H P45 0000 0450H P54 0000 0460H P55 0000 0470H reservedNote Table 3 5 Interrupt Exception Table 3 3 Start Address of Interrupt Exception Table Interrupt Exception Source Note Reserved for internal ...

Page 73: ...F AFFFH are reserved for the internal RAM area In the µPD703129 the 16 KB of addresses 3FF 8000H to 3FF BFFFH are provided as internal physical RAM Figure 3 11 Internal RAM Area of µPD703129 Figure 3 12 Internal RAM Area of µPD703128 µPD703129 Internal RAM area 16 Kbytes 3FF BFFFH 3FF 8000H µPD703128 Internal RAM area 12 Kbytes 3FF AFFFH 3FF 8000H ...

Page 74: ...ess of the word area ignoring the lower 2 bits of the address 2 For registers in which byte access is possible if half word access is executed the higher 8 bits become undefined during the read operation and the lower 8 bits of data are written to the register during the write operation 3 Addresses that are not defined as registers are reserved for future expansion If these addresses are accessed ...

Page 75: ...64 MB space starting from address 0000 0000H unconditionally corresponds to the memory map of the program space 2 Data space For the efficient use of resources to be performed through the wrap around feature of the data space the continuous 16 MB address spaces 0000 0000H to 00FF FFFFH and FF00 0000H to FFFF FFFFH of the 4 GB CPU address space are used as the data space With the V850E CA2 64 MB ph...

Page 76: ... BHC R W 0000H FFFF F06E CPU VPB Strobe Wait Control register VSWC R W 77H FFFF F070 Instruction Cache Control Register ICC R W 0003H FFFF F072 Instruction Cache Index Register ICI R W FFFFH FFFF F074 Instruction Cache Data Configuration ICD R W undefined FFFF F080 DMA source address register 0L DSAL0 R W undefined FFFF F082 DMA source address register 0H DSAH0 R W undefined FFFF F084 DMA destinat...

Page 77: ...t control register 1 TMD0IC R W 47H FFFF F114 Interrupt control register 2 TMD1IC R W 47H FFFF F116 Interrupt control register 3 WTIIC R W 47H FFFF F118 Interrupt control register 4 P0IC R W 47H FFFF F11A Interrupt control register 5 P1IC R W 47H FFFF F11C Interrupt control register 6 P2IC R W 47H FFFF F11E Interrupt control register 7 P3IC R W 47H FFFF F120 Interrupt control register 8 P4IC R W 4...

Page 78: ...terrupt control register 42 FC4ERIC R W 47H FFFF F166 Interrupt control register 43 CSI0IC R W 47H FFFF F168 Interrupt control register 44 CSI1IC R W 47H FFFF F16A Interrupt control register 45 CSI2IC R W 47H FFFF F16C Interrupt control register 46 SER0IC R W 47H FFFF F16E Interrupt control register 47 SR0IC R W 47H FFFF F170 Interrupt control register 48 ST0IC R W 47H FFFF F172 Interrupt control ...

Page 79: ...rt 6 mode PM6 R W FFH FFFF F42E Port 9 mode PM9 R W FFH FFFF F440 Port 1 mode control PMC1 R W 00H FFFF F442 Port 2 mode control PMC2 R W 00H FFFF F444 Port 3 mode control PMC3 R W 00H FFFF F446 Port 4 mode control PMC4 R W 00H FFFF F448 Port 5 mode control PMC5 R W 00H FFFF F44A Port 6 mode control PMC6 R W 00H FFFF F480 MEMC Bus Cycle Type Control register 0 BCT0 R W 8888H FFFF F482 MEMC Bus Cyc...

Page 80: ...M0L R W 00H FFFF F643 TMGCM0H R W 00H FFFF F644 Output control register OCTLG0 R W 0000H OCTLG0L R W 00H FFFF F645 OCTLG0H R W 00H FFFF F646 State register TMGST0 R 00H FFFF F648 Timer Count Register 0 TMG00 R 0000H FFFF F64A Timer Count Register 1 TMG01 R 0000H FFFF F64C Capture Compare register 0 GCC00 R W 0000H FFFF F64E Capture Compare register 1 GCC01 R W 0000H FFFF F650 Capture Compare regis...

Page 81: ...R W 00H FFFF F842 DMA trigger source select register 1 DTFR1 R W 00H FFFF F844 DMA trigger source select register 2 DTFR2 R W 00H FFFF F846 DMA trigger source select register 3 DTFR3 R W 00H FFFF F880 Interrupt Mode Control Register 0 INTM0 R W 00H FFFF F882 Interrupt Mode Control Register 1 INTM1 R W 00H FFFF F884 Interrupt Mode Control Register 2 INTM2 R W 00H FFFF F886 Interrupt Mode Control Re...

Page 82: ...FFF FD44 Transmission data buffer register SOTB1 SOTBL1 R W 0000H 00H FFFF FD48 First transmission data buffer register SOTBF1 SOTBFL1 R W 0000H 00H FFFF FD4A Shift register SIO1 SIOL1 R O 0000H 00H FFFF FD80 CSI operation mode register CSIM2 R W CSIM_C SIC2 00H FFFF FD81 Clock selection register CSIC2 R W 00H FFFF FD82 Reception data buffer register SIRB2 SIRBL2 R O 0000H 00H FFFF FD84 Transmissi...

Page 83: ...ble peripheral I O area The base address of the programmable peripheral I O area is specified by the initialization of the peripheral area selection control register BPC Figure 3 15 Programmable Peripheral I O Register Outline Cautions 1 The CAN message buffer register can allocate address xxxx freely as a program mable peripheral I O register but once the address xxxx is set it cannot be changed ...

Page 84: ...the programmable peripheral area is located at 180 0000H Therefore the FCAN macro is mapped to the memory location 180 0000H to 180 11FFH 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value BPC PA15 0 PA13 PA12 PA11 PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 FFFF F064H 0000H Bit Position Bit Name Function 15 PA15 Enables disables usage of programmable peripheral I O area 13 to 0 PA13 to ...

Page 85: ...N message ID register H00 M_IDH00 R W x Undefined xxxxn014H CAN message configuration register 00 M_CONF00 R W x Undefined xxxxn015H CAN message status register 00 M_STAT00 R x Undefined xxxxn016H CAN status set cancel register 00 SC_STAT00 W x 0000H xxxxn020H CAN message event pointer 010 M_EVT010 R W x Undefined xxxxn021H CAN message event pointer 011 M_EVT011 R W x Undefined xxxxn022H CAN messa...

Page 86: ...AN message event pointer 030 M_EVT030 R W x Undefined xxxxn061H CAN message event pointer 031 M_EVT031 R W x Undefined xxxxn062H CAN message event pointer 032 M_EVT032 R W x Undefined xxxxn063H CAN message event pointer 033 M_EVT033 R W x Undefined xxxxn064H CAN message data length register 03 M_DLC03 R W x Undefined xxxxn065H CAN message control register 03 M_CTRL03 R W x Undefined xxxxn066H CAN ...

Page 87: ...N message event pointer 052 M_EVT052 R W x Undefined xxxxn0A3H CAN message event pointer 053 M_EVT053 R W x Undefined xxxxn0A4H CAN message data length register 05 M_DLC05 R W x Undefined xxxxn0A5H CAN message control register 05 M_DTRL05 R W x Undefined xxxxn0A6H CAN message time stamp register 05 M_TIME05 R W x Undefined xxxxn0A8H CAN message data register 050 M_DATA050 R W x Undefined xxxxn0A9H...

Page 88: ...essage data length register 07 M_DLC07 R W x Undefined xxxxn0E5H CAN message control register 07 M_CTRL07 R W x Undefined xxxxn0E6H CAN message time stamp register 07 M_TIME07 R W x Undefined xxxxn0E8H CAN message data register 070 M_DATA070 R W x Undefined xxxxn0E9H CAN message data register 071 M_DATA071 R W x Undefined xxxxn0EAH CAN message data register 072 M_DATA072 R W x Undefined xxxxn0EBH ...

Page 89: ...message time stamp register 09 M_TIME09 R W x Undefined xxxxn128H CAN message data register 090 M_DATA090 R W x Undefined xxxxn129H CAN message data register 091 M_DATA091 R W x Undefined xxxxn12AH CAN message data register 092 M_DATA092 R W x Undefined xxxxn12BH CAN message data register 093 M_DATA093 R W x Undefined xxxxn12CH CAN message data register 094 M_DATA094 R W x Undefined xxxxn12DH CAN ...

Page 90: ... message data register 111 M_DATA111 R W x Undefined xxxxn16AH CAN message data register 112 M_DATA112 R W x Undefined xxxxn16BH CAN message data register 113 M_DATA113 R W x Undefined xxxxn16CH CAN message data register 114 M_DATA114 R W x Undefined xxxxn16DH CAN message data register 115 M_DATA115 R W x Undefined xxxxn16EH CAN message data register 116 M_DATA116 R W x Undefined xxxxn16FH CAN mes...

Page 91: ...N message data register 133 M_DATA133 R W x Undefined xxxxn1ACH CAN message data register 134 M_DATA134 R W x Undefined xxxxn1ADH CAN message data register 135 M_DATA135 R W x Undefined xxxxn1AEH CAN message data register 136 M_DATA136 R W x Undefined xxxxn1AFH CAN message data register 137 M_DATA137 R W x Undefined xxxxn1B0H CAN message ID register L13 M_IDL13 R W x Undefined xxxxn1B2H CAN messag...

Page 92: ...N message data register 155 M_DATA155 R W x Undefined xxxxn1EEH CAN message data register 156 M_DATA156 R W x Undefined xxxxn1EFH CAN message data register 157 M_DATA157 R W x Undefined xxxxn1F0H CAN message ID register L15 M_IDL15 R W x Undefined xxxxn1F2H CAN message ID register H15 M_IDH15 R W x Undefined xxxxn1F4H CAN message configuration register 15 M_CONF15 R W x Undefined xxxxn1F5H CAN mes...

Page 93: ...CAN message data register 177 M_DATA177 R W x Undefined xxxxn230H CAN message ID register L17 M_IDL17 R W x Undefined xxxxn232H CAN message ID register H17 M_IDH17 R W x Undefined xxxxn234H CAN message configuration register 17 M_CONF17 R W x Undefined xxxxn235H CAN message status register 17 M_STAT17 R x Undefined xxxxn236H CAN status set cancel register 17 SC_STAT17 W x 0000H xxxxn240H CAN messa...

Page 94: ...message ID register H19 M_IDH19 R W x Undefined xxxxn274H CAN message configuration register 19 M_CONF19 R W x Undefined xxxxn275H CAN message status register 19 M_STAT19 R x Undefined xxxxn276H CAN status set cancel register 19 SC_STAT19 W x 0000H xxxxn280H CAN message event pointer 200 M_EVT200 R W x Undefined xxxxn281H CAN message event pointer 201 M_EVT201 R W x Undefined xxxxn282H CAN message...

Page 95: ...AN message status register 21 M_STAT21 R x Undefined xxxxn2B6H CAN status set cancel register 21 SC_STAT21 W x 0000H xxxxn2C0H CAN message event pointer 220 M_EVT220 R W x Undefined xxxxn2C1H CAN message event pointer 221 M_EVT221 R W x Undefined xxxxn2C2H CAN message event pointer 222 M_EVT222 R W x Undefined xxxxn2C3H CAN message event pointer 223 M_EVT223 R W x Undefined xxxxn2C4H CAN message d...

Page 96: ...N message event pointer 240 M_EVT240 R W x Undefined xxxxn301H CAN message event pointer 241 M_EVT241 R W x Undefined xxxxn302H CAN message event pointer 242 M_EVT242 R W x Undefined xxxxn303H CAN message event pointer 243 M_EVT243 R W x Undefined xxxxn304H CAN message data length register 24 M_DLC24 R W x Undefined xxxxn305H CAN message control register 24 M_CTRL24 R W x Undefined xxxxn306H CAN m...

Page 97: ...N message event pointer 262 M_EVT262 R W x Undefined xxxxn343H CAN message event pointer 263 M_EVT263 R W x Undefined xxxxn344H CAN message data length register 26 M_DLC26 R W x Undefined xxxxn345H CAN message control register 26 M_CTRL26 R W x Undefined xxxxn346H CAN message time stamp register 26 M_TIME26 R W x Undefined xxxxn348H CAN message data register 260 M_DATA260 R W x Undefined xxxxn349H...

Page 98: ...essage data length register 28 M_DLC28 R W x Undefined xxxxn385H CAN message control register 28 M_CTRL28 R W x Undefined xxxxn386H CAN message time stamp register 28 M_TIME28 R W x Undefined xxxxn388H CAN message data register 280 M_DATA280 R W x Undefined xxxxn389H CAN message data register 281 M_DATA281 R W x Undefined xxxxn38AH CAN message data register 282 M_DATA282 R W x Undefined xxxxn38BH ...

Page 99: ...essage time stamp register 30 M_TIME30 R W x Undefined xxxxn3C8H CAN message data register 300 M_DATA300 R W x Undefined xxxxn3C9H CAN message data register 301 M_DATA301 R W x Undefined xxxxn3CAH CAN message data register 302 M_DATA302 R W x Undefined xxxxn3CBH CAN message data register 303 M_DATA303 R W x Undefined xxxxn3CCH CAN message data register 304 M_DATA304 R W x Undefined xxxxn3CDH CAN m...

Page 100: ...find start register CGMSS W x 0000H xxxxn101AH CAN message find result register CGMSR R x 0000H xxxxn101CH CAN test bus register CTBR R W x x 0000H xxxxn101DH CAN Macro Version Register CGREV R x x Revision xxxxn101EH CAN Macro Revision Register CGVER R x x Version xxxxn101FH R x x xxxxn1020H CAN global interrupt pending register Note 1 CGINTP R W R x 00H xxxxn1022H CAN local interrupt pending reg...

Page 101: ... register C2BA R x x 00FFH xxxxn109CH CAN2 bit rate prescaler register C2BRP R W x x 0000H xxxxn109DH CAN2 bus diagnostic information register C2DINF R x x 0000H xxxxn109EH CAN2 synchronization control register C2SYNC R W x x 0218H xxxxn10C0H CAN3 address mask register L0 Note 2 C3MASKL0 R W x x Undefined xxxxn10C2H CAN3 address mask register H0 Note 2 C3MASKH0 R W x x Undefined xxxxn10C4H CAN3 ad...

Page 102: ...er H2 Note 2 C4MASKH2 R W x x Undefined xxxxn11CCH CAN4 address mask register L3 Note 2 C4MASKL3 R W x x Undefined xxxxn11CEH CAN4 address mask register H3 Note 2 C4MASKH3 R W x x Undefined xxxxn11D0H CAN4 control register Note 1 2 C4CTRL R W R x 0101H xxxxn11D2H CAN4 definition register Note 1 2 C4DEF R W R x 0000H xxxxn11D4H CAN4 information register Note 2 C4LAST R x x 00FFH xxxxn11D6H CAN4 err...

Page 103: ...and therefore the PRCMD register has to be written first The following 5 NOPs are necessary for waken from the STOP mode Example 1 MOV 0x02 r10 2 ST B r10 PRCMD r0 3 ST B r10 PSC r0 4 NOP dummy instruction 5 times NOP required No special sequence is required when reading the specific registers Remarks 1 A store instruction to a command register will not be received with an interrupt This presuppos...

Page 104: ...egister is read Only the first write access to a specific on chip register hereafter referred to as a specific register after data has been written to the PRCMD register is valid In this way the value of the specific register can be rewritten only in a specified sequence and an illegal write access is inhibited Figure 3 17 Command Register PRCMD Format REG7 to REG0 registration code any 8 bit data...

Page 105: ...r referred to as a specific register after data has been written to the PHCMD register is valid In this way the value of the specific register can be rewritten only in a specified sequence and an illegal write access is inhibited Figure 3 18 Peripheral Command Register PHCMD Format REG7 0 registration code any 8 bit data Caution The register must be written with store instruction execution by CPU ...

Page 106: ...er is not written to causing a protection error Writing 0 to the PRERR flag after the value is checked clears the error Operation conditions of PRERR flag Set condition 1 If the most recent store instruction for peripheral I O register operation is not an operation to write the PHCMD register and if data is written to the specific register 2 If the first store instruction operation after data has ...

Page 107: ...1 0 Address R W Reset Value VSWC 0 SUWL2 SUWL1 SUWL0 0 VSWL2 VSWL1 VSWL0 FFFFF06EH R W 77H 0 1 1 1 0 1 1 1 Bit Name Description SUWL2 SUWL1 SUWL0 Setup wait for internal peripheral bus length SUWL2 SUWL1 SUWL0 Number of data wait states n 7 0 0 0 0 0 0 0 1 1 system clock 0 1 0 2 system clock 0 1 1 3 system clock 1 0 0 4 system clock 1 0 1 5 system clock 1 1 0 6 system clock 1 1 1 7 system clock de...

Page 108: ...minary User s Manual U15839EE1V0UM00 Table 3 8 The Values of VSWC Register depending on System Clock System Clock Setup Wait Strobe Wait VSWC 4 0 MHz fCPU 16 6 MHz 0 0 00H 16 6 MHz fCPU 25 0 MHz 0 1 01H 25 0 MHz fCPU 32 0 MHz 1 1 11H ...

Page 109: ...s for each memory block External wait function through WAIT pin Idle state insertion function External device connection can be enabled via bus control port alternate function pins 4 2 Bus Control Pins The following pins are used for connecting to external devices Bus Control Pin Function when in Control Mode Function when in Port Mode Register for Port Control Mode Switching Address data Data bus...

Page 110: ... 000H 39FF FFFH 3800 000H 37FF FFFH 3400 000H 33FF FFFH 3000 000H 2FFF FFFH 2800 000H 27FF FFFH 1000 000H 0FFF FFFH 0C00 000H 0BFF FFFH 0400 000H 03FF FFFH 0200 000H 01FF FFFH 0000 000H Block 1 2 Mbytes Block 0 2 Mbytes Block 3 2 Mbytes Block 13 2 Mbytes Block 14 2 Mbytes Block 12 2 Mbytes Block 15 2 Mbytes CS7 CS5 CS6 CS4 CS6 CS4 CS4 CS3 Block 11 4 Mbytes Block 10 4 Mbytes Block 9 8 Mbytes Block ...

Page 111: ...order is controlled as follows CSC0 Peripheral I O area CS0 CS2 CS1 CS3 Note CSC1 Peripheral I O area CS7 CS5 CS6 CS4 Note Notes 1 Not all the chip area select signals are externally available on output pins Even so enabling chip area select signals other than CS0 CS3 or CS4 the setting for the corresponding memory blocks will be effective too regardless of an external chip select output pin 2 Aft...

Page 112: ... access CS23 CS2 active during block 3 access CS30 CS3 active during block 0 1 2 or 3 access CS31 CS3 active during block 4 or 5 access CS32 CS3 active during block 6 access CS33 CS3 active during block 7 access CS40 CS4 active during block 12 13 14 or 15 access CS41 CS4 active during block 10 or 11 access CS42 CS4 active during block 9 access CS43 CS4 active during block 8 access CS50 CS5 active ...

Page 113: ...a is allocated to the last 4 KB of the programmable peripheral I O register area Figure 4 3 Programmable Peripheral I O Register Outline Cautions 1 The programmable peripheral area must not be located above the address x1FFFFFFH 2 Once the address of the programmable peripheral area is se it cannot be changed 3 If the programmable peripheral I O area overlaps the following areas the pro grammable ...

Page 114: ...grammable peripheral area is mapped to x1800000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value BPC PA15 0 PA13 PA12 PA11 PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 FFFFF064H 0000H Bit Position Bit Name Function 15 PA15 Enables disables usage of programmable peripheral I O area PA15 Usage of Programmable Peripheral I O Area 0 Disables usage of programmable peripheral I O area 1 Enab...

Page 115: ...and BCT1 registers is finished However it is possible to access external memory areas whose initialization has been finished 2 The bits marked as 0 are reserved They have to leave to 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value BCT0 ME3 0 0 BT30 ME2 0 0 BT20 ME1 0 0 BT10 ME0 0 0 BT00 FFFFF480H 8888H CS3 CS2 CS1 CS0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value BCT1 M...

Page 116: ... BSC register is finished However it is possible to access external memory areas whose initialization has been finished 2 When the data bus width is specified as 8 bits only the LWR signal becomes active 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value BSC 0 BS70 0 BS60 0 BS50 0 BS40 0 BS30 0 BS20 0 BS10 0 BS00 FFFFF066H 5555H CS7 CS6 CS5 CS4 CS3 CS2 CS1 CS0 Bit Position Bit Name Functi...

Page 117: ...o Little Endian format n 0 to 7 3 In the following areas the data processing method is fixed to Little Endian method Any setting of Big Endian method for these areas according to the BEC register is invalid On chip peripheral I O area Internal RAM area Fetch area of external memory Figure 4 5 Big Endian Addresses within Word Figure 4 6 Little Endian Addresses within Word 15 14 13 12 11 10 9 8 7 6 ...

Page 118: ...ian format CS area and CS areas set as the following areas ROM area RAM area Peripheral I O area Programmable peripheral I O area 2 The bits marked as 0 are reserved They have to leave to 0 Note n 0 to 7 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value BEC 0 BH70 0 BH60 0 BH50 0 BH40 0 BH30 0 BH20 0 BH10 0 BH00 FFFFF06AH 0000H CS7 CS6 CS5 CS4 CS3 CS2 CS1 CS0 Bit Position Bit Name Functi...

Page 119: ...r starting from the lower order side 1 Byte access 8 bits a When the data bus width is 16 bits Little Endian 1 Access to even address 2n 2 Access to odd address 2n 1 b When the data bus width is 8 bits Little Endian 1 Access to even address 2n 2 Access to odd address 2n 1 7 0 7 0 Byte data 15 8 External data bus 2n Address 7 0 7 0 Byte data 15 8 External data bus 2n 1 Address 7 0 7 0 Byte data Ext...

Page 120: ...ddress 2n 2 Access to odd address 2n 1 d When the data bus width is 8 bits Big Endian 1 Access to even address 2n 2 Access to odd address 2n 1 7 0 7 0 Byte data 15 8 External data bus 2n Address 7 0 7 0 Byte data 15 8 External data bus 2n 1 Address 7 0 7 0 Byte data External data bus 2n Address 7 0 7 0 Byte data External data bus 2n 1 Address ...

Page 121: ...dress 2n 1 1 st Access 2 nd Access 7 0 7 0 Halfword data 15 8 15 8 External data bus 2n 1 Address 7 0 7 0 Halfword data 15 8 15 8 External data bus 2n 2 Address 7 0 7 0 Halfword data 15 8 External data bus 2n Address 15 8 2n 1 7 0 7 0 Halfword data 15 8 External data bus Address 7 0 7 0 Halfword data 15 8 External data bus 2n 1 Address 2n 1 st Access 2 nd Access 1 st Access 2 nd Access 7 0 7 0 Hal...

Page 122: ...t Access 2 nd Access 7 0 7 0 Halfword data 15 8 External data bus 2n 1 Address 15 8 2n 7 0 7 0 Halfword data 15 8 15 8 External data bus 2n 1 Address 7 0 7 0 Halfword data 15 8 15 8 External data bus 2n 2 Address 1 st Access 2 nd Access 1 st Access 2 nd Access 7 0 7 0 Halfword data 15 8 External data bus 2n Address 7 0 7 0 Halfword data 15 8 External data bus 2n 1 Address 7 0 7 0 Halfword data 15 ...

Page 123: ...a 15 8 External data bus 4n Address 15 8 4n 1 23 16 31 24 7 0 7 0 Word data 15 8 External data bus 4n 2 Address 15 8 4n 3 23 16 31 24 1 st Access 2 nd Access 7 0 7 0 Word data 15 8 External data bus Address 15 8 4n 1 23 16 31 24 7 0 7 0 Word data 15 8 External data bus 4n 2 Address 15 8 4n 3 23 16 31 24 7 0 7 0 Word data 15 8 External data bus 4n 4 Address 15 8 23 16 31 24 1 st Access 2 nd Access ...

Page 124: ...ess 15 8 4n 3 23 16 31 24 7 0 7 0 Word data 15 8 External data bus 4n 4 Address 15 8 4n 5 23 16 31 24 1 st Access 2 nd Access 7 0 7 0 Word data 15 8 External data bus Address 15 8 4n 3 23 16 31 24 7 0 7 0 Word data 15 8 External data bus 4n 4 Address 15 8 4n 5 23 16 31 24 7 0 7 0 Word data 15 8 External data bus 4n 6 Address 15 8 23 16 31 24 1 st Access 2 nd Access 3 rd Access ...

Page 125: ...1 24 7 0 7 0 Word data External data bus 4n 2 Address 15 8 23 16 31 24 7 0 7 0 Word data External data bus 4n 3 Address 15 8 23 16 31 24 1 st Access 2 nd Access 3 rd Access 4 th Access 7 0 7 0 Word data External data bus Address 15 8 4n 1 23 16 31 24 7 0 7 0 Word data External data bus 4n 2 Address 15 8 23 16 31 24 7 0 7 0 Word data External data bus 4n 3 Address 15 8 23 16 31 24 7 0 7 0 Word data...

Page 126: ...ta External data bus 4n 4 Address 15 8 23 16 31 24 7 0 7 0 Word data External data bus 4n 5 Address 15 8 23 16 31 24 1 st Access 2 nd Access 3 rd Access 4 th Access 7 0 7 0 Word data External data bus Address 15 8 4n 3 23 16 31 24 7 0 7 0 Word data External data bus 4n 4 Address 15 8 23 16 31 24 7 0 7 0 Word data External data bus 4n 5 Address 15 8 23 16 31 24 7 0 7 0 Word data External data bus 4...

Page 127: ...ernal data bus 4n 3 Addres 15 8 4n 2 23 16 31 24 7 0 7 0 Word data 15 8 External data bus 4n 1 Address 15 8 4n 23 16 31 24 1 st Access 2 nd Access 7 0 7 0 Word data 15 8 External data bus Address 15 8 4n 1 23 16 31 24 7 0 7 0 Word data 15 8 External data bus 4n 3 Address 15 8 4n 2 23 16 31 24 7 0 7 0 Word data 15 8 External data bus 4n 4 Address 15 8 23 16 31 24 1 st Access 2 nd Access 3 rd Access...

Page 128: ...ess 15 8 4n 4 23 16 31 24 7 0 7 0 Word data 15 8 External data bus 4n 3 Address 15 8 4n 2 23 16 31 24 1 st Access 2 nd Access 7 0 7 0 Word data 15 8 External data bus Address 15 8 4n 3 23 16 31 24 7 0 7 0 Word data 15 8 External data bus 4n 5 Address 15 8 4n 4 23 16 31 24 7 0 7 0 Word data 15 8 External data bus 4n 6 Address 15 8 23 16 31 24 1 st Access 2 nd Access 3 rd Access ...

Page 129: ...6 31 24 7 0 7 0 Word data External data bus 4n 1 Address 15 8 23 16 31 24 7 0 7 0 Word data External data bus 4n Address 15 8 23 16 31 24 1 st Access 2 nd Access 3 rd Access 4 th Access 7 0 7 0 Word data External data bus Address 15 8 4n 4 23 16 31 24 7 0 7 0 Word data External data bus 4n 3 Address 15 8 23 16 31 24 7 0 7 0 Word data External data bus 4n 2 Address 15 8 23 16 31 24 7 0 7 0 Word dat...

Page 130: ...ta External data bus 4n 3 Address 15 8 23 16 31 24 7 0 7 0 Word data External data bus 4n 2 Address 15 8 23 16 31 24 1 st Access 2 nd Access 3 rd Access 4 th Access 7 0 7 0 Word data External data bus Address 15 8 4n 6 23 16 31 24 7 0 7 0 Word data External data bus 4n 5 Address 15 8 23 16 31 24 7 0 7 0 Word data External data bus 4n 4 Address 15 8 23 16 31 24 7 0 7 0 Word data External data bus 4...

Page 131: ...he settings of registers DWC0 and DWC1 are invalid wait control is performed by each memory controller Page ROM on page access 3 Write to the DWC0 and DWC1 registers after reset and then do not change the set values Also do not access an external memory area other than that for this ini tialization routine until initial setting of the DWC0 and DWC1 registers is finished However it is possible to a...

Page 132: ...tten in 16 bit units Remark During address setup wait the external wait function is disabled by the WAIT pin 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value ASC AC71 AC70 AC61 AC60 AC51 AC50 AC41 AC40 AC31 AC30 AC21 AC20 AC11 AC10 AC01 AC00 FFFFF48AH FFFFH CS7 CS6 CS5 CS4 CS3 CS2 CS1 CS0 Bit Position Bit Name Function 15 to 0 ACn1 ACn0 n 0 to 7 Address Cycle Specifies the number of add...

Page 133: ...setup hold time at sampling timing is not satisfied the wait state may or may not be inserted in the next state 4 8 3 Relationship between programmable wait and external wait A wait cycle is inserted as the result of an OR operation between the wait cycle specified by the set value of the programmable wait and the wait cycle controlled by the WAIT pin In other words the number of wait cycles is de...

Page 134: ...atically programmed for all memory blocks 1 Bus cycle control register BCC This register can be read written in 16 bit units Cautions 1 The internal iCache area the internal RAM area and the internal peripheral I O area are not subject to insertion of an idle state 2 Write to the BCC register after reset and then do not change the set value Also do not access an external memory area other than tha...

Page 135: ...ity has the DMA cycle instruction fetch and operand data access in this order An instruction fetch may be inserted between read access and write access during read modify write access Also an instruction fetch may be inserted between bus access and bus access during CPU bus clock Table 4 2 Bus Priority Order Priority Order External Bus Cycle Bus Master High Low DMA cycle DMA controller Operand dat...

Page 136: ... Data space The V850E CA2 Jupiter is provided with an address misalign function Through this function regardless of the data format word data halfword data or byte data data can be placed in all addresses However in the case of word data and halfword data if data are not sub jected to boundary alignment the bus cycle will be generated a minimum of 2 times and bus efficiency will drop 1 In the case...

Page 137: ...akes a minimum of 2 states Up to 7 states of programmable data waits can be inserted through setting of the DWC0 and DWC1 registers Data wait can be controlled with input pin WAIT Up to 3 idle states can be inserted after the read write cycle through setting of the BCC register Up to 3 address set up wait states can be inserted through setting of the ASC register ...

Page 138: ...n to SRAM a When data bus width is 16 bits b When data bus width is 8 bits Remark CSn CS0 CS3 and CS4 2 Mbit SRAM 256 Kwords x 16 bits V850E CA2 D0 to D15 CSn LWR UWR LBE UBE RD WE A1 to A17 A1 to A17 D1 to D16 CS OE A0 to A16 D1 to D8 1 Mbit SRAM 128 Kwords x 8 bits CS OE WE A1 to A17 D0 to D7 CSn RD LWR D8 to D15 V850E CA2 UWR A0 to A16 D1 to D8 1 Mbit SRAM 128 Kwords x 8 bits CS OE WE ...

Page 139: ...gure 5 2 SRAM External ROM External I O Access Timing 1 6 a During read Remarks 1 The circles indicate the sampling timing 2 The broken line indicates the high impedance state 3 CSn CS0 CS3 and CS4 T1 T2 Address Data WAIT input D0 to D15 I O LWR output UWR output RD output CSn output A0 to A23 output System CLK Data Address TW T2 T1 ...

Page 140: ... I O Access Timing 2 6 b During read address setup wait idle state insertion Remarks 1 The circles indicate the sampling timing 2 The broken line indicates the high impedance state 3 CSn CS0 CS3 and CS4 TASW T1 Address Data WAIT input D0 to D15 I O LWR output UWR output RD output CSn output A0 to A23 output System CLK TI T2 ...

Page 141: ... ROM External I O Access Timing 3 6 c During write Remarks 1 The circles indicate the sampling timing 2 The broken line indicates the high impedance state 3 CSn CS0 CS3 and CS4 T1 T2 Address Data WAIT input D0 to D15 I O LWR output UWR output RD output A0 to A23 output System CLK Data Address TW T2 T1 CSn output ...

Page 142: ... I O Access Timing 4 6 d During write address setup wait idle state insertion Remarks 1 The circles indicate the sampling timing 2 The broken line indicates the high impedance state 3 CSn CS0 CS3 and CS4 TASW T1 Address Data WAIT input D0 to D15 I O LWR output UWR output RD output A0 to A23 output System CLK TI T2 CSn output ...

Page 143: ...ROM External I O Access Timing 5 6 e When read write operation Remarks 1 The circles indicate the sampling timing 2 The broken line indicates the high impedance state 3 CSn CS0 CS3 and CS4 T1 T2 Address Data Data WAIT input D0 to D15 I O LWR output UWR output RD output A0 to A23 output System CLK T2 T1 CSn output ...

Page 144: ...ROM External I O Access Timing 6 6 f When write read operation Remarks 1 The circles indicate the sampling timing 2 The broken line indicates the high impedance state 3 CSn CS0 CS3 and CS4 T1 T2 Address Data WAIT input D0 to D15 I O LWR output UWR output RD output A0 to A23 output System CLK T2 T1 CSn output Data ...

Page 145: ... 5 2 1 Features Direct connection to 8 bit 16 bit page ROM supported In case of 16 bit bus width 4 8 16 32 64 word page access supported In case of 8 bit bus width 8 16 32 64 128 word page access supported Page ROM access a minimum of 2 states On page judgment function Addresses to be compared can be changed through setting of the PRC register Up to 7 states of programmable data waits can be inser...

Page 146: ...of Page ROM Connections a In case of 16 bit data bus width b In case of 8 bit data bus width Remark CSn CS0 CS3 and CS4 A0 to A19 O1 to O16 CE OE 16 Mbit page ROM 1 Mword x 16 bits A1 to A20 D0 to D15 CSn RD V850E CA2 A0 to A20 O1 to O8 CE OE 16 Mbit page ROM 2 Mwords x 8 bits A1 to A21 D0 to D7 CSn RD D8 to D15 V850E CA2 A0 to A20 O0 to O8 CE OE 16 Mbit page ROM 2 Mwords x 8 bits ...

Page 147: ... of 16 Mbit 1 M 16 bits page ROM 4 word page access b In case of 16 Mbit 1 M 16 bits page ROM 8 word page access a23 a22 a21 a20 a7 a6 a5 a4 a3 A23 A22 A21 A20 A7 A6 A5 A4 A3 A2 A1 A1 A0 A0 Internal address latch immediately preceding address V850E CA2 address output Page ROM address A19 Off page address On page address A6 A5 A4 A3 A2 MA6 0 MA5 0 MA4 0 MA3 0 PRC register setting Comparison Continu...

Page 148: ... M 16 bits page ROM 16 word page access a23 a22 a21 a20 a7 a6 a5 a4 a3 A23 A22 A21 A20 A7 A6 A5 A4 A3 A2 A1 A1 A0 A0 Internal address latch immediately preceding address V850E CA2 address output Page ROM address A19 Off page address On page address Continuous reading possible 16 bit data bus width 16 words A6 A5 A4 A3 A2 MA6 0 MA5 0 MA4 1 MA3 1 PRC register setting Comparison ...

Page 149: ...emory areas whose initialization has been finished 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value PRC 0 PRW2 PRW1 PRW0 0 0 0 0 0 0 0 0 MA6 MA5 MA4 MA3 FFFFF49AH 7000H Bit Position Bit Name Function 14 to 12 PRW2 to PRW0 Page ROM On page Wait Control Sets the number of waits corresponding to the internal system clock The number of waits set by this bit are inserted only when on page Wh...

Page 150: ...ord word access with 8 bit bus width or when word access with 16 bit bus width Remarks 1 The circles indicate the sampling timing 2 The broken line indicates the high impedance state 3 CSn CS0 CS3 and CS4 T1 TW Off page address Data WAIT input D0 to D15 I O D0 to D7 I O LWR output UWR output RD output CSn output A0 to A23 output System CLK Data On page address TO1 TO2 T2 ...

Page 151: ...8 bit bus width or when byte half word access with 16 bit bus width Remarks 1 The circles indicate the sampling timing 2 The broken line indicates the high impedance state 3 CSn CS0 CS3 and CS4 T1 TW Off page address Data WAIT input D0 to D15 I O D0 to D7 I O LWR output UWR output RD output CSn output A0 to A23 output System CLK Data On page address TO1 TO2 T2 ...

Page 152: ...lf word word access with 8 bit bus width or when word access with 16 bit bus width Remarks 1 The circles indicate the sampling timing 2 The broken line indicates the high impedance state 3 CSn CS0 CS3 and CS4 TASW T1 Off page address Data WAIT input D0 to D15 I O D0 to D7 I O LWR output UWR output RD output CSn output A0 to A23 output System CLK Data On page address TASW TO1 TO2 TI T2 ...

Page 153: ...te access with 8 bit bus width or when byte half word access with 16 bit bus width Remarks 1 The circles indicate the sampling timing 2 The broken line indicates the high impedance state 3 CSn CS0 CS3 and CS4 TASW T1 Off page address Data WAIT input D0 to D15 I O D0 to D7 I O LWR output UWR output RD output CSn output A0 to A23 output System CLK Data On page address TASW TO1 TO2 TI T2 ...

Page 154: ...154 Preliminary User s Manual U15839EE1V0UM00 MEMO ...

Page 155: ...thm replaces the cache line that has not been used since the longest time The probability of a instruction cache hit is mostly higher compared to the direct mapped type Using the tag clear function the contents of all tags can be cleared invalidated Using the autofill function instructions for one way can be filled automatically way 0 only A filled way is locked automatically and replacing data in...

Page 156: ...m s performance the V850E CA2 Jupiter device provides a 4 KByte 2 way associative instruction cache memory The instruction cache is organ ized as 4 words x 128 entries x 2 ways Figure 6 1 Instruction Cache Configuration Instruction Cache Instruction Cache Interface Bus Control Unit BCU CPU NB85E V850E System Bus VSB Memory Controller MEMC External Memory ...

Page 157: ...e has two ways each consisting of a block of 128 entries of 4 words per line for a total capacity of 4 KB Figure 6 2 Configuration of 4 KB 2 Way Set Associative Instruction Cache INDEX TAG 3 0 1 2 10 11 25 Tag part 128 entries Data part 4 words 2 7 15 Internal bus 1 word 1 word 1 word 1 word Internal bus Comparator 15 15 32 32 Selector Instruction data 4 Way selection control signal on hit IIHIT 3...

Page 158: ...ing bit 4 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value ICC 0 0 0 LOCK0 0 0 0 0 0 0 0 FILL0 0 0 TCLR1 TCLR0 FFFFF070H 03H Bit Position Bit Name Function 12 LOCK0 This bit shows the cache lock status of way 0 When way 0 is filled the cache is locked and this bit is set 1 automatically Clearing 0 this bit releases the cache lock of way 0 0 Way 0 is not locked 1 Way 0 is locked 4 FILL0 ...

Page 159: ...he Initial Register ICI The ICI register controls the iCache operation by the MODE bit The ICI register can be accessed by 16 bit access Figure 6 5 Instruction Cache Initial Register ICI Caution All bits of the ICI register must be cleared immediately following a system reset The following procedure must be executed to clear the ICI register Example st h r0 0xfffff072 r0 15 14 13 12 11 10 9 8 7 6 ...

Page 160: ...ng the cache configuration register BHC 2 Operation on Instruction Cache Hit 1 On a fetch access from memory the CPU outputs the instruction fetch request and the concerned address to the instruction cache 2 If a hit occurs due to the address existing in the instruction cache the instruction data is read from the instruction cache and passed through to the CPU Figure 6 6 Operation on Instruction C...

Page 161: ...struction cache to the BCU 3 The BCU then outputs the address to external memory via the VSB and refills the instruction cache with one line 4 words at the address to be read 4 The instruction cache then transfers the data to be read among the 4 words of refill data to the CPU Caution The miss penalty time when a miss occurs varies depending on such things as mem ory controller specifications for ...

Page 162: ...ruction Cache 16 bit Data Bus Remarks 1 The numbers within pointed brackets indicate the refill sequence 2 Adrs n Data of address in n 0H to FH 128 entries Higher address Lower address Data part 4 words 1 word 1 word 1 word 1 word 8 Addr EH 7 Addr CH 6 Addr AH 5 Addr 8H 4 Addr 6H 3 Addr 4H 2 Addr 2H 1 Addr 0H ...

Page 163: ...yNote a Set the TCLR0 bit b Read the TCLR0 bit to confirm that this bit is cleared c Perform a and b above again d Set the TCLR1 bit e Read the TCLR1 bit to confirm that this bit is cleared f Perform d and e above again Note The setting can also be made in order of d e f a b c 3 Way 0 shares the counter to clear tags with way 1 Therefore a clear tag operation must not be started set the TCLR0 bit ...

Page 164: ...P2 Second TAG clear 13 Id h ICC r0 r1 14 cmp r0 r1 15 bnz LOP2 Remark The clock count required for a tag clear operation is 256 clocks To actually clear tags the required clock count is doubled because a tag clear operation is performed twice sequen tially Note During reset active the value of the bits TCLR0 and TCLR1 becomes set 1 and tag initializa tion begins automatically Upon completion of ta...

Page 165: ...r and confirm that bit is cleared 0 Remarks 1 A lock is released by clearing bit LOCK0 of the ICC register 2 While the iCache autofill operation is ongoing neither interrupt nor NMI will be served by CPU until the iCache autofill procedure is finished Even for the situation that a required interrupt service function is by chance already available in the second way of iCache CPU can not access thes...

Page 166: ...et 1 Wait until the contents of the ICC register becomes 0000H TAG initialization is completed 2 Clear all bits of the ICI register using the following instruction st h r0 0xfffff072 r0 3 Set the ICC and ICD registers 4 Make the instruction cache settings of the cache configuration register BHC Caution Be sure to make the BHC register settings running the code from an uncacheable area an instructi...

Page 167: ... ICCNote Instruction cache data configuration register ICD Note Excluding bit 4 3 Initial program settings Always execute the following instruction before setting the cache configuration register BHC with the initial settings of the user program immediately following system reset st h r0 0xfffff072 r0 Following execution of this instruction the cache is enabled by setting cache enable BHn0 bit 1 a...

Page 168: ...ed if the memory boundary is continuously accessed by instruction other than a branch instruction An example is shown below Suppose that the cache area settings are as shown in figure iCache Area Setting Example In this case access to the memory areas is as follows From CS0 area to CS1 area access is possible only by using a branch instruction From CS1 area to CS2 area continuous access is possibl...

Page 169: ...Transfer units 8 16 and 32 bits Maximum transfer count 65 536 216 Two types of transfer two cycle transfer Four transfer modes Single transfer mode Single step transfer mode Line transfer mode Four bus cycle transfer mode Block transfer mode Transfer requests Request by interrupts from on chip peripheral I O Requests by software trigger Transfer objects Between internal RAM and I O Between interna...

Page 170: ...al I O register image 3FFF000H to 3FFFFFFH must not be specified Figure 7 1 DMA Source Address Registers DSAH0 to DSAH3 DSAH0 to DSAH3 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value DSAH0 IR 0 0 0 SA26 SA26 SA25 SA24 SA23 SA22 SA21 SA20 SA19 SA18 SA17 SA16 FFFFF082H undef 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value DSAH1 IR 0 0 0 SA26 SA26 SA25 SA24 SA23 SA22 SA21 SA20...

Page 171: ...f 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value DSAL1 SA15 SA14 SA13 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 FFFFF088H undef 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value DSAL2 SA15 SA14 SA13 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 FFFFF090H undef 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value DSAL3 SA15 SA14 SA13 SA12 SA11 SA1...

Page 172: ...register image 3FFF000H to 3FFFFFFH must not be specified Figure 7 3 DMA Destination Address Registers 0H to 3H DDA0H to DDA3H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value DDAH0 IR 0 0 0 DA27 DA26 DA25 DA24 DA23 DA22 DA21 DA20 DA19 DA18 DA17 DA16 FFFFF086H undef 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value DDAH1 IR 0 0 0 DA27 DA26 DA25 DA24 DA23 DA22 DA21 DA20 DA19 DA...

Page 173: ...5 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value DDAL1 DA15 DA14 DA13 DA12 DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 FFFFF08CH undef 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value DDAL2 DA15 DA14 DA13 DA12 DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 FFFFF094H undef 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value DDAL3 DA15 DA14 DA13 DA12 DA11 DA10 D...

Page 174: ...lied 2 For a setting of the DBCn register in which the transfer count cannot be divided by 4 the sections that can be line transferred are line transferred first then the remaining indivisible sections are transferred as single transfer Remark n 0 to 3 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value DBC0 BC15 BC14 BC13 BC12 BC11 BC10 BC9 BC8 BC7 BC6 BC5 BC4 BC3 B2C BC1 BC0 FFFFF0C0H un...

Page 175: ...0 DAD1 DAD0 TM1 TM0 0 0 FFFFF0D2H 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value DADC2 DS1 DS0 0 0 0 0 0 0 SAD1 SAD0 DAD1 DAD0 TM1 TM0 0 0 FFFFF0D4H 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value DADC3 DS1 DS0 0 0 0 0 0 0 SAD1 SAD0 DAD1 DAD0 TM1 TM0 0 0 FFFFF0D6H 0000H Bit Position Bit Name Function 15 14 DS1 DS0 Sets the transfer data size for DMA transfer DS...

Page 176: ...eration Remark n 0 to 3 Bit Position Bit Name Function 5 4 DAD1 DAD0 Sets the count direction of the destination address for DMA channel n n 0 to 3 DAD1 DAD0 Count Direction 0 0 Increment 0 1 Decrement 1 0 Fixed 1 1 Setting prohibited 3 2 TM1 TM0 Sets the transfer mode during DMA transfer TM1 TM0 Transfer Mode 0 0 Single transfer mode 0 1 Single step transfer mode 1 0 Line transfer mode 1 1 Block ...

Page 177: ...r through DMA channel n has ended or not It is read only and is set to 1 when DMA transfer ends and cleared 0 when it is read 0 DMA transfer had not ended 1 DMA transfer had ended 3 MLEn When this bit is set to 1 at terminal count output the Enn bit is not cleared to 0 and the DMA transfer enable state is retained Moreover the next DMA transfer request can be accepted even when the TCn bit is not ...

Page 178: ...ng the ENn bit of the corresponding channel to 1 This register can be read written in 8 bit or 1 bit units Figure 7 9 DMA Restart Register DRST Remark n 0 to 3 7 6 5 4 3 2 1 0 Address Initial value DDIS 0 0 0 0 CH3 CH2 CH1 CH0 FFFFF0F0H 00H Bit Position Bit Name Function 3 to 0 CH3 to CH0 Reflects the contents of the ENn bit of the DCHCn register during NMI input The con tents of this register are...

Page 179: ...ware is not possible A 0 must be written to the respective bit location to reset DRQ or DOFL Cautions 1 Be sure to stop DMA operation before making changes to DTFR0 register set tings 2 An interrupt request input in a standby mode IDLE or software STOP mode can not be used as a DMA transfer start factor 7 6 5 4 3 2 1 0 Address Initial value DTFR0 DRQ DOFL 0 0 0 IFC2 IFC1 IFC0 FFFFF840H 00H Bit Pos...

Page 180: ...ware is not possible A 0 must be written to the respective bit location to reset DRQ or DOFL Cautions 1 Be sure to stop DMA operation before making changes to DTFR1 register set tings 2 An interrupt request input in a standby mode IDLE or software STOP mode can not be used as a DMA transfer start factor 7 6 5 4 3 2 1 0 Address Initial value DTFR1 DRQ DOFL 0 0 0 IFC2 IFC1 IFC0 FFFFF842H 00H Bit Pos...

Page 181: ...e is not possible A 0 must be written to the respective bit location to reset DRQ or DOFL Cautions 1 Be sure to stop DMA operation before making changes to DTFR2 register set tings 2 An interrupt request input in a standby mode IDLE or software STOP mode can not be used as a DMA transfer start factor 7 6 5 4 3 2 1 0 Address Initial value DTFR2 DRQ DOFL 0 0 0 IFC2 IFC1 IFC0 FFFFF844H 00H Bit Positi...

Page 182: ...re is not possible A 0 must be written to the respective bit location to reset DRQ or DOFL Cautions 1 Be sure to stop DMA operation before making changes to DTFR3 register set tings 2 An interrupt request input in a standby mode IDLE or software STOP mode can not be used as a DMA transfer start factor 7 6 5 4 3 2 1 0 Address Initial value DTFR3 DRQ DOFL 0 0 0 IFC2 IFC1 IFC0 FFFFF846H 00H Bit Posit...

Page 183: ...ewritten with the value that was set immediately before Therefore during DMA transfer transfer is automatically started when a new DMA transfer setting is made for these registers and the MLEn bit of the DCHCn register is set however the DMA transfer end interrupt may be issued even if DMA transfer is automatically started Figure 7 14 Buffer Register Configuration on page 183 shows the configurati...

Page 184: ...In the last T2R state read data is sampled After entering the last T2R state the bus invariably enters the T1W state 6 T2RI state State in which the bus is ready for DMA transfer to on chip peripheral I O or internal RAM state in which the bus mastership is acquired for DMA transfer to on chip peripheral I O or internal RAM After entering the last T2RI state the bus invariably enters the T1W state...

Page 185: ...ansfers If the next transfer is executed in block transfer mode the DMAC moves to the T1FH state after the T2FH state In other modes if a wait has occurred the DMAC transitions to the T1FHI state If no wait has occurred the bus is released and the DMAC transitions to the TE state 13 TE state The TE state corresponds to DMA transfer completion The DMAC generates the internal DMA transfer completion...

Page 186: ...UM00 7 4 2 DMAC bus cycle state transition Except for the block transfer mode each time the processing for a DMA transfer is completed the bus mastership is released Figure 7 15 DMAC Bus Cycle State Transition Diagram a Two cycle transfer T1W T2RI T1R T0 TI T1RI T2R T1WI T2W TE TI ...

Page 187: ...ated lower priority DMA transfer request Figure 7 16 Single Transfer Example 1 on page 187 shows a DMAC transfer in single transfer mode In this example the DMA channel 3 is used for a single transfer Figure 7 16 Single Transfer Example 1 Figure 7 17 Single Transfer Example 2 on page 187 shows DMAC transfers in single transfer mode in which a higher priority DMA transfer request is generated DMA c...

Page 188: ...ted within one clock after the end of a sin gle transfer DMA channels 0 2 and 3 are used for this single transfer example When three or more DMA transfer request signals are activated at the same time always the two highest priority DMA trans fers are performed alternately Figure 7 19 Single Transfer Example 4 Note The bus is always released DMA Transfer Request CH0 DMA Transfer Request CH3 DMA ch...

Page 189: ...s a DMA transfer example in single step transfer mode Figure 7 20 Single Step Transfer Example 1 Figure 7 21 Single Step Transfer Example 2 on page 189 shows a DMA transfer example in single step transfer mode in which a higher priority DMA transfer request is generated while the lower DMA channel has released the bus Figure 7 21 Single Step Transfer Example 2 Note The bus is always released DMA1 ...

Page 190: ... released for the CPU is a transfer based on the newly generated lower priority DMA transfer request Figure 7 22 Line Transfer Example 1 on page 190 shows a DMA transfer example in line transfer mode Figure 7 22 Line Transfer Example 1 Figure 7 23 Line Transfer Example 2 on page 190 shows DMAC transfers in line transfer mode in which a higher priority DMA transfer request is generated DMA channels...

Page 191: ... for the line transfer example Figure 7 24 Line Transfer Example 3 DMA channel 0 in Figure 7 25 Line Transfer Example 4 on page 191 is used for a single transfer and channel 3 is used for the line transfer Figure 7 25 Line Transfer Example 4 Note The bus is always released DMA Transfer Request CH0 DMA channel 0 terminal count DMA Transfer Request CH3 DMA channel 3 terminal count DMA3 CPU DMA0 CPU ...

Page 192: ... ends and the DMAC releases the bus and another DMA transfer can be acknowledged Figure 7 26 Block Transfer Example on page 192 shows a block transfer mode example It is a block transfer mode example in which a higher priority DMA transfer request is generated DMA channels 2 and 3 are used for the block transfer example Figure 7 26 Block Transfer Example DMA Transfer Request CH2 DMA Transfer Reque...

Page 193: ... one clock idle period is always inserted between a read cycle and a write cycle 7 7 Transfer Object 7 7 1 Transfer type and transfer object Table 7 1 Relationship Between Transfer Type and Transfer Object on page 193 lists the relation ships between transfer type and transfer object Table 7 1 Relationship Between Transfer Type and Transfer Object Caution Addresses between 3FFF000H and 3FFFFFFH ca...

Page 194: ... while the bus is released in the TI state the higher priority DMA transfer request is acknowledged 7 9 DMA Transfer Start Factors There are two types of DMA transfer start factors as shown below 1 Request from on chip peripheral I O If the ENn and the TCn bits of the DCHCn register are set as shown below and an interrupt request is issued from the on chip peripheral I O that is set in the DTFRn r...

Page 195: ... bit is set the next DMA transfer request is acknowledged and DMA transfer begins Figure 7 27 Example of Forcible Interruption of DMA Transfer Caution To forcibly interrupt DMA transfer and stop the next transfer from occurring the NMI signal must be made active before the end of the DMA transfer currently under exe cution Moreover although it is possible to restart DMA transfer following an inter...

Page 196: ...l register Figure 7 28 DMA Transfer Forcible Termination Example 1 Remarks 1 The next condition can be set even during DMA transfer because the DSAn DDAn and DBCn registers are buffered registers However the setting to the DADCn register is invalid refer to 7 3 Next Address Setting Function and 7 2 4 DMA addressing control registers 0 to 3 DADC0 to DADC3 2 n 0 to 3 DMA Transfer Request CH2 DMA Tra...

Page 197: ... 0 to 3 7 12 DMA Transfer Completion 7 12 1 DMA transfer end interrupt When DMA transfer ends and the TCn bit of the DCHCn register is set a DMA transfer end interrupt INTDMAn is issued to the interrupt controller INTC Remark n 0 to 3 7 12 2 Terminal count output upon DMA transfer end The terminal count signal becomes active for one clock during the last DMA transfer cycle DMA Transfer Request CH1...

Page 198: ... not supported 3 Times related to DMA transfer The overhead before and after DMA transfer and the minimum execution clock for DMA transfer are shown below Internal RAM access 2 clocks 4 Bus arbitration for CPU The CPU can access on chip peripheral I O and internal RAM not undergoing DMA transfer While data transfer is being executed between internal RAMs the CPU can access external mem ory and per...

Page 199: ...on or by generation of an exception event i e fetching of an illegal opcode exception trap Eight levels of software programmable priorities can be specified for each interrupt request Interrupt servicing starts after no fewer than 11 system clocks 343 ns 32 MHz following the generation of an interrupt request 8 1 Features Interrupts Non maskable interrupts 2 sources Maskable interrupts 63 sources ...

Page 200: ...Port Module 9 0110H 00000110H nextPC Interrupt INTTMG00 TMG00IC Time base 0 Overflow Timer G0 10 0120H 00000120H nextPC Interrupt INTTMG01 TMG01IC Time base 1 Overflow Timer G0 11 0130H 00000130H nextPC Interrupt INTGCC00 GCC00IC CC coincidence Channel 0 Timer G0 12 0140H 00000140H nextPC Interrupt INTGCC01 GCC01IC CC coincidence Channel 1 Timer G0 13 0150H 00000150H nextPC Interrupt INTGCC02 GCC0...

Page 201: ...tPC Interrupt Note 2 INTFC4RX FC4RXIC CAN4 Receive Interrupt FCAN machine 4 40 0300H 00000300H nextPC Interrupt Note 2 INTFC4TX FC4TXIC CAN4 Transmit Interrupt FCAN machine 4 41 0310H 00000310H nextPC Interrupt Note 2 INTFC4ER FC4ERIC CAN4 Error Interrupt FCAN machine 4 42 0320H 00000320H nextPC Interrupt INTCSI0 CSI0IC Transmission Reception Completion CSI0 43 0330H 00000330H nextPC Interrupt INT...

Page 202: ...t INTDMA2 DMA2IC DMA Channel 2 transfer completed DMA2 54 03E0H 000003E0H nextPC Interrupt INTDMA3 DMA3IC DMA Channel 3 transfer completed DMA3 55 03F0H 000003F0H nextPC Interrupt INTDOVF DOVFIC DMA Overflow DMA Trigger 56 0400H 00000400H nextPC Interrupt INTP00 P00IC P30 Port Module 57 0410H 00000410H nextPC Interrupt INTP05 P05IC P35 Port Module 58 0420H 00000420H nextPC Interrupt INTP10 P10IC P...

Page 203: ...MI0 is generated while NMI0 is being serviced The new NMI0 request is held pending regardless of the value of the PSW NP bit The pending NMIVC request is acknowledged after servicing of the current NMI0 request has finished after execution of the RETI instruction 2 If a NMIWDT request is generated while NMI0 is being serviced If the PSW NP bit remains set 1 while NMI0 is being serviced the new NMI...

Page 204: ...9EE1V0UM00 Figure 8 1 Example of Non Maskable Interrupt Request Acknowledgement Operation 1 2 a Multiple NMI requests generated at the same time NMI0 and NMIWDT requests generated simultaneously NMI0 and NMIWDT requests generated simultaneously Main routine NMIWDT servicing System reset ...

Page 205: ...DT request generated during NMI0 servicing NP 0 set before NMIWDT request NMIWDT NMI0 request generated during NMIWDT servicing NMI1 request generated during NMIWDT servicing Main routine NMI0 request NMI0 request NMI0 servicing Held pending Servicing of pending NMI0 Main routine NMI0 request Invalid System reset Main routine Invalid System reset Main routine NMI0 request NMI0 servicing System res...

Page 206: ...fword FECC of ECR 4 Sets the NP and ID bits of the PSW and clears the EP bit 5 Sets the handler address corresponding to the non maskable interrupt to the PC and transfers control The processing configuration of a non maskable interrupt is shown in Figure 8 2 Figure 8 2 Processing Configuration of Non Maskable Interrupt Non maskable interrupt request FEPC Restored PC FEPSW PSW ECR FECC Exception c...

Page 207: ...ess of the restored PC and PSW Figure 8 3 illustrates how the RETI instruction is processed Figure 8 3 RETI Instruction Processing Caution When the PSW EP bit and PSW NP bit are changed by the LDSR instruction during non maskable interrupt processing in order to restore the PC and PSW correctly during recovery by the RETI instruction it is necessary to set PSW EP back to 0 and PSW NP back to 1 usi...

Page 208: ...n be read written in 8 bit or 1 bit units Figure 8 5 Interrupt Mode Register 3 INTM3 Notes 1 This register can be written only once ESN0 is cleared to 0 by Reset 2 This register should always be programmed even if the user needs to use the reset value This will prevent unintended write to this register afterwards 3 NMI functionality is masked by PMC60 Selection of valid edge for NMI must be perfor...

Page 209: ...ority than the interrupt request in progress specified by the interrupt control register Note that only interrupts with a higher priority will have this capability interrupts with the same priority level cannot be nested However if multiple interrupts are executed the following processing is necessary 1 Save EIPC and EIPSW in memory or a general purpose register before executing the EI instruc tio...

Page 210: ...unmasked or when PSW NP 0 and PSW ID 0 as set by the RETI and LDSR instructions input of the pending INT starts the new maskable interrupt processing INT input xxIF 1 No xxMK 0 No Is the interrupt mask released Yes Yes No No No Maskable interrupt request Interrupt request pending PSW NP PSW ID 1 1 Interrupt request pending 0 0 Interrupt processing CPU processing INTC accepted Yes Yes Yes Priority ...

Page 211: ... PSW Figure 8 7 illustrates the processing of the RETI instruction Figure 8 7 RETI Instruction Processing Note For the ISPR register see 8 3 6 In service priority register ISPR on page 220 Caution When the PSW EP bit and the PSW NP bit are changed by the LDSR instruction dur ing maskable interrupt processing in order to restore the PC and PSW correctly dur ing recovery by the RETI instruction it i...

Page 212: ...ister xxICn When two or more interrupts having the same prior ity level specified by the xxPRn bit are generated at the same time interrupts are serviced in order depending on the priority level allocated to each interrupt request type default priority level before hand For more information refer to Table 8 1 Interrupt Exception Source List on page 200 The programmable priority control customizes ...

Page 213: ...equests Main routine EI EI Interrupt request a level 3 Processing of a Processing of b Processing of c Interrupt request c level 3 Processing of d Processing of e EI Interrupt request e level 2 Processing of f EI Processing of g Interrupt request g level 1 Interrupt request h level 1 Processing of h Interrupt request b is acknowledged because the priority of b is higher than that of a and interrup...

Page 214: ...nterrupt request p level 2 Interrupt request q level 1 Interrupt request r level 0 Interrupt request u level 2 Note 2 Interrupt request t level 2 Note 1 Processing of p Processing of q Processing of r EI If levels 3 to 0 are acknowledged Interrupt request j is held pending because its priority is lower than that of i k that occurs after j is acknowledged because it has the higher priority Interrup...

Page 215: ...after executing the DI instruction Remark a to c in the figure are the temporary names of interrupt requests shown for the sake of explanation Default priority a b c Main routine EI Interrupt request a level 2 Interrupt request b level 1 Interrupt request c level 1 Processing of interrupt request b Processing of interrupt request c Processing of interrupt request a Interrupt request b and c are ac...

Page 216: ... Control Registers on page 217 7 6 5 4 3 2 1 0 Address Initial value xxIC xxIF xxMK 0 0 0 xxPR2 xxPR1 xxPR0 FFFFF110H to FFFF18EH 47H Bit Position Bit Name Function 7 xxIF This is an interrupt request flag 0 Interrupt request not issued 1 Interrupt request issued The flag xxIFn is reset automatically by the hardware if an interrupt request is acknowl edged 6 xxMK This is an interrupt mask flag 0 E...

Page 217: ... 0 TMG11PR2 TMG11PR1 TMG11PR0 FFFFF138H GCC10IC GCC10IF GCC10MK 0 0 0 GCC10PR2 GCC10PR1 GCC10PR0 FFFFF13AH GCC11IC GCC11IF GCC11MK 0 0 0 GCC11PR2 GCC11PR1 GCC11PR0 FFFFF13CH GCC12IC GCC12IF GCC12MK 0 0 0 GCC12PR2 GCC12PR1 GCC12PR0 FFFFF13EH GCC13IC GCC13IF GCC13MK 0 0 0 GCC13PR2 GCC13PR1 GCC13PR0 FFFFF140H GCC14IC GCC14IF GCC14MK 0 0 0 GCC14PR2 GCC14PR1 GCC14PR0 FFFFF142H GCC15IC GCC15IF GCC15MK 0...

Page 218: ...R1IC SER1IF SER1MK 0 0 0 SER1PR2 SER1PR1 SER1PR0 FFFFF174H SR1IC SR1IF SR1MK 0 0 0 SR1PR2 SR1PR1 SR1PR0 FFFFF176H ST1IC ST1IF ST1MK 0 0 0 ST1PR2 ST1PR1 ST1PR0 FFFFF178H DMA0IC DMA0IF DMA0MK 0 0 0 DMA0PR2 DMA0PR1 DMA0PR0 FFFFF17AH DMA1IC DMA1IF DMA1MK 0 0 0 DMA1PR2 DMA1PR1 DMA1PR0 FFFFF17CH DMA2IC DMA2IF DMA2MK 0 0 0 DMA2PR2 DMA2PR1 DMA2PR0 FFFFF17EH DMA3IC DMA3IF DMA3MK 0 0 0 DMA3PR2 DMA3PR1 DMA3P...

Page 219: ...3 Remark xx Identification name of each peripheral unit WT TMD P TMG GCC AD MAC FC CSI UART DMA 15 14 13 12 11 10 9 8 Address Initial value IMR0 GCC03MK GCC02MK GCC01MK GCC00MK TMG01MK TMG00MK P5MK P4MK FFFFF100H FFFFH 7 6 5 4 3 2 1 0 P3MK P2MK P1MK P0MK WTIMK TMD1MK TMD0MK WTMK 15 14 13 12 11 10 9 8 Address Initial value IMR1 FC1RXMK MACMK ADMK CCC01MK CCC00MK TMC0MK GCC15MK GCC14MK FFFFF102H FFF...

Page 220: ...Figure 8 13 Maskable Interrupt Status Flag ID 7 6 5 4 3 2 1 0 Address Initial value ISPR ISPR7 ISPR6 ISPR5 ISPR4 ISPR3 ISPR2 ISPR1 ISPR0 FFFFF19AH 00H Bit Position Bit Name Function 7 to 0 ISPR7 to ISPR0 Indicates priority of interrupt currently acknowledged 0 Interrupt request with priority n not acknowledged 1 Interrupt request with priority n acknowledged 31 8 7 6 5 4 3 2 1 0 Initial value PSW ...

Page 221: ...are equipped with edge detection and need only noise suppression Figure 8 14 Port Interrupt Input Circuit P52 P53 P61 P62 P63 P64 Figure 8 15 Timer G Input Circuit P30 P35 P40 P45 P54 P55 Figure 8 16 NMI Input Circuit Note Edge select circuit is different for NMI and INTPn NMI can only configured as rising or falling edge sensitive whereas INTPn can be triggered by rising falling or both edges Inp...

Page 222: ...mpares the input pin level against a delayed input pin level The filter output follows the filter input if this compare operation matches 8 4 2 Interrupt Trigger Mode Selection The valid edge of the INTP pins can be selected by the program The edge that can be selected as the valid edge is one of the following Rising edge Falling edge Both the rising and the falling edges ...

Page 223: ... value INTM0 ES031 ES030 ES021 ES020 ES011 ES010 ES001 ES000 FFFFF880H 00H Bit Position Bit Name Function 7 6 ES031 ES030 Edge selection for INTP3 to interrupt controller Selects active edge for interrupt generation ES031 ES030 Edge selection 0 0 Falling edge 0 1 Rising edge 1 0 Reserved 1 1 Both edges 5 4 ES021 ES020 Edge selection for INTP2 to interrupt controller ES021 ES020 Edge selection 0 0 ...

Page 224: ...tion 7 6 ES071 ES070 Edge selection for INTP05 to interrupt controller Selects active edge for interrupt generation ES071 ES070 Edge selection 0 0 Falling edge 0 1 Rising edge 1 0 Reserved 1 1 Both edges 5 4 ES061 ES060 Edge selection for INTP00 to interrupt controller ES061 ES060 Edge selection 0 0 Falling edge 0 1 Rising edge 1 0 Reserved 1 1 Both edges 3 2 ES051 ES050 Edge selection for INTP5 t...

Page 225: ...ion 7 6 ES111 ES110 Edge selection for INTP21 to interrupt controller Selects active edge for interrupt generation ES111 ES110 Edge selection 0 0 Falling edge 0 1 Rising edge 1 0 Reserved 1 1 Both edges 5 4 ES101 ES100 Edge selection for INTP20 to interrupt controller ES101 ES100 Edge selection 0 0 Falling edge 0 1 Rising edge 1 0 Reserved 1 1 Both edges 3 2 ES091 ES090 Edge selection for INTP15 t...

Page 226: ...ionality is masked by PMC60 Selection of valid edge for NMI must be performed while PMC60 is 0 2 Install appropriate interrupt handler for NMI before reprogramming edge detection or port function 7 6 5 4 3 2 1 0 Address Initial value INTM3 ESN0 FFFFF886H 00H Bit Position Bit Name Function 0 ESN0 Edge selection for NMI Selects active edge for interrupt generation 0 Falling edge 1 Rising edge ...

Page 227: ... ECR interrupt source 4 Sets the EP and ID bits of the PSW 5 Sets the handler address 00000040H or 00000050H corresponding to the software exception to the PC and transfers control Figure 8 21 illustrates the processing of a software exception Figure 8 21 Software Exception Processing Note TRAP Instruction Format TRAP vector the vector is a value from 0 to 1FH The handler address is determined by ...

Page 228: ...ntrol to the address of the restored PC and PSW Figure 8 22 illustrates the processing of the RETI instruction Figure 8 22 RETI Instruction Processing Caution When the PSW EP bit and the PSW NP bit are changed by the LDSR instruction dur ing the software exception processing in order to restore the PC and PSW correctly during recovery by the RETI instruction it is necessary to set PSW EP back to 1...

Page 229: ...te that exception processing is in progress It is set when an exception occurs Figure 8 23 Exception Status Flag EP 31 8 7 6 5 4 3 2 1 0 Initial value PSW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NP EP ID SAT CY OV S Z 00000020H Bit Position Bit Name Function 6 EP Shows that exception processing is in progress 0 Exception processing not in progress 1 Exception processing in progress ...

Page 230: ...ated when an instruction applicable to this illegal instruction is executed Remark Arbitrary 1 Operation If an exception trap occurs the CPU performs the following processing and transfers control to the handler routine 1 Saves the restored PC to DBPC 2 Saves the current PSW to DBPSW 3 Sets the NP EP and ID bits of the PSW 4 Sets the handler address 00000060H corresponding to the exception trap to...

Page 231: ...uction the CPU carries out the following processing and controls the address of the restored PC 1 Loads the restored PC and PSW from DBPC and DBPSW 2 Transfers control to the address indicated by the restored PC and PSW Figure 8 25 illustrates the restore processing from an exception trap Figure 8 25 Restore Processing from Exception Trap DBRET instruction PC PSW DBPC DBPSW Jump to address of rest...

Page 232: ...is generated the CPU performs the following processing transfers control to the debug monitor routine and shifts to debug mode 1 Saves the restored PC to DBPC 2 Saves the current PSW to DBPSW 3 Sets the NP EP and ID bits of the PSW 4 Sets the handler address 00000060H corresponding to the debug trap to the PC and transfers control Figure 8 26 illustrates the processing of the debug trap Figure 8 2...

Page 233: ...truction the CPU carries out the following processing and controls the address of the restored PC 1 Loads the restored PC and PSW from DBPC and DBPSW 2 Transfers control to the address indicated by the restored PC and PSW Figure 8 27 illustrates the restore processing from a debug trap Figure 8 27 Restore Processing from Debug Trap DBRET instruction PC PSW DBPC DBPSW Jump to address of restored PC...

Page 234: ...ocessing control is executed when an interrupt has an enable status ID 0 Thus if multiple interrupts are executed it is necessary to have an interrupt enable status ID 0 even for an interrupt processing routine If a maskable interrupt enable or a software exception is generated in a maskable interrupt or software exception service program it is necessary to save EIPC and EIPSW This is accomplished...

Page 235: ... PPRn0 to PPRn2 bits The priority order of maskable interrupts is as follows High Level 0 Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 Low Interrupt processing that has been suspended as a result of multiple processing control is resumed after the processing of the higher priority interrupt has been completed and the RETI instruction has been executed A pending interrupt request is ackn...

Page 236: ...ardware STOP mode When an external bus is accessed When there are two or more successive interrupt request non sampling instructions see 8 9 Periods in Which Interrupts Are Not Acknowledged on page 237 When the interrupt control register is accessed Figure 8 28 Pipeline Operation at Interrupt Request Acknowledgment Outline Remark INT1 to INT4 Interrupt acknowledgement processing IFx Invalid instru...

Page 237: ...are as follows EI instruction DI instruction LDSR reg2 0x5 instruction for PSW The store instruction for the interrupt control register PlCn in service priority register ISPR and command register PRCMD Table 8 3 Interrupt Response Time Interrupt Response Time Internal System Clocks Condition Internal Interrupt External interrupt Minimum 5 5 analog delay time The following cases are exceptions In I...

Page 238: ...238 Preliminary User s Manual U15839EE1V0UM00 MEMO ...

Page 239: ...ad Spectrum PLL for CPU BCU clock supply Clock sources Oscillation through oscillator connection Oscillation through sub oscillator connection during sub watch mode Power save modes WATCH mode Sub WATCH mode HALT mode IDLE mode STOP mode low power sub clock for watch timer and watchdog timer to reduce power consumption in watch mode ...

Page 240: ...ucture 64 fX 4 MHz 50 fX 5 MHz 1 2 fCPU 1 128 fX fXT fXXP fXX 1 2 SSCG Main System Clock OSC Subsystem Clock OSC XT1 XT2 X1 X2 STOP WATCH S WATCH PLL Circuit 8 STOP WATCH S WATCH Prescaler 8 fXX 6 fXX 4 fXX 3 fXX Selector Selector STOP WATCH S WATCH IDLE WATCH S WATCH HALT CPU BCU Selector Selector fPCLK IDLE WATCH Peripherals fWDT Watchdog Timer Prescaler Selector fXXT Selector fXXT fCKSEL2 Watch...

Page 241: ...zation time the software must remain in a loop and the CPU and the peripherals are supplied by the main oscillator clock Switching to an unstable clock source is not protected by hardware SCEN SSCG enable bit This bit enables or disables Spread Spectrum Clock Generation 0 SSCG disabled 1 SSCG enabled Caution The SSCG is enabled when this bit is set 1 Before applying the SSCG clock as the clock sup...

Page 242: ...LLEN bit and the SCEN bit are allowed to be set 1 when the system remains in the main oscillation mode CPU and peripherals are using the main oscillator as the clock supply To write data to the CKC register use the store instruction ST SST and bit manipulation instruction SET1 CLR1 NOT1 The contents of this register can be read in the normal sequence Bit name Function WTSEL1 Sub clock source selec...

Page 243: ...ister can be read in 8 or 1 bit units Figure 9 3 Clock Generator Status Register CGSTAT 7 6 5 4 3 2 1 0 Address Initial value CGSTAT 0 0 0 0 0 0 OSCSTAT SCSTAT FFFFF824H 00H Bit name Function OSCSTAT Main clock stabilization indication bit determined by counter 0 Main oscillator is not stabilized 1 Main oscillator is stabilized SCSTAT SSCG lock status determined by SSCG Lock signal 0 SSCG is not s...

Page 244: ...the set data to the destination register WCC Remarks 1 If it is required to switch to another WDT clock source it is recommended to monitor the status of the concerned clock source to be selected before Switching to an unstable clock source is not protected by hardware 2 The WCC register should be programmed immediately after occurrence of a system Reset even in the case that the default settings ...

Page 245: ...gister can be read or written in 8 bit units Figure 9 5 Processor Clock Control Register PCC 1 2 7 6 5 4 3 2 1 0 Address Initial value PCC FRC 0 MFRC CLS 0 0 CKS1 CKS0 FFFFF828H 00H Bit name Function FRC Sub system clock oscillation circuit control of internal return resistance 0 Resistance connected 1 Resistance disconnected Remark The FRC bit must always remain cleared 0 while sub system clock o...

Page 246: ...ot protected by hardware 2 It is only possible to change the contents of the PCC register for one time after the occurrence of a Reset or if a power save mode has been released 3 After release from Watch mode Idle mode or Stop mode the register PCC is set to Main oscillator mode After release from Sub Watch mode the register PCC is set to Main oscillator mode in case that the bit OSCDIS is cleared...

Page 247: ...urce of the last system reset This register can only be read in 8 or 1 bit units Figure 9 6 Reset Source Monitor Register RSM 7 6 5 4 3 2 1 0 Address Initial value RSM 0 0 0 0 0 0 0 RESM FFFFF830H 00 01H Bit name Function RESM Reset Source Monitor flag 0 Last Reset was caused by external RESET input 1 Last Reset was caused by internal Watchdog timer overflow ...

Page 248: ... until the occurrence of a Reset or the release of a power save mode hap pened Afterwards a power save mode has been released one bit is allowed to be changed 7 6 5 4 3 2 1 0 Address Initial value SCFMC 0 SCPS1 SCPS0 SCFMC4 SCFMC3 SCFMC2 SCFMC1 SCFMC0 FFFFF82AH 0AH Bit name Function SCPS1 SCPS0 Frequency modulation control bits SCPS1 SCPS0 Post Scale Factor of the SSCG 0 0 fXX 3 Note If SSCG opera...

Page 249: ...r can only be written if the SSCG enable bit SCEN is cleared 7 6 5 4 3 2 1 0 Address Initial value SCFC0 SCFC07 SCFC06 SCFC05 SCFC04 SCFC03 SCFC02 SCFC01 SCFC00 FFFFF82CH 3FH Bit Position Bit Name Function 7 to 0 SCFC07 to SCFC00 Specifies the first frequency divider of the SSCG fX 4 MHz fX 5 MHz The initialization of the SCFC0 register depends to the output frequency supplied by the main oscillat...

Page 250: ...aution This register can only be written if the SSCG enable bit SCEN is cleared 7 6 5 4 3 2 1 0 Address Initial value SCFC1 SCFC17 SCFC16 SCFC15 SCFC14 SCFC13 SCFC12 SCFC11 SCFC10 FFFFF82EH 40H Bit Position Bit Name Function 7 to 0 SCFC17 to SCFC10 Specifies the second frequency divider of the SSCG fX 4 MHz fX 5 MHz The initialization of the SCFC1 register depends to the output frequency supplied ...

Page 251: ...saving functions These modes can be combined and switched to suit the target application which enables effective implementation of low power systems Table 9 1 Power Saving Modes Overview Remarks 1 Operates 2 Stopped Notes 1 If the OSCDIS bit 1 than the Main Oscillator is stopped 2 If the SOSTP bit 0 than the Sub Oscillator operates Clock Source Mode Operation of Clock Supply to Oscillator SSCG PLL...

Page 252: ...0 Power Save Mode State Transition Diagram Notes 1 The SSCG and PLL is deactivated per hardware 2 Enable SSCG and PLL manual Normal operation mode Software STOP mode Set STOP mode IDLE mode Set IDLE mode Release by RESET NMI or maskable interrupt Set HALT mode HALT mode Release by RESET NMI or maskable interrupt Release by RESET NMI or maskable interrupt NMI or maskable interrupt Release by RESET ...

Page 253: ... provides low power consumption where the power is only consumed from the OSC Main oscillator Sub Oscillator and Watch timer Watchdog timer This mode is entered by set ting registers with software 3 WATCH mode In this mode the clock generator PLL and SSCG stops operation Therefore the entire system excluding Watch timer Watchdog timer unit stops This mode provides low power consumption where the p...

Page 254: ...on on on on on on on on on on on SSCG off SCEN Note SCEN Note SCEN Note SCEN Note off off off off off off PLL off PLLEN Note PLLEN Note PLLEN Note PLLEN Note off off off off off off CPU clock CLS CKS 000 fX fX fX off fX off fX off fX off fX CLS CKS 001 N A fXX fXX off N A off N A off N A off N A CLS CKS 01x N A fXXP fXXP off N A off N A off N A off N A CLS CKS 1xx N A fXT fXT off N A off N A off N...

Page 255: ... H H H H operate RD Hi Z H H H H operate WAIT operate RESOUT LOW HIGH HIGH HIGH HIGH HIGH TIG05 to TIG00 TIG15 to TIG10 TIC01 to TIC00 N A operate INTP05 INTP00 INTP15 INTP10 INTP21 INTP20 INTP5 to INTP0 NMI N A operate operate operate operate operate TOG04 to TOG01 TOG14 to TOG11 TOC0 N A HOLD HOLD HOLD HOLD operate SO02 SO01 SO00 N A HOLD HOLD HOLD HOLD operate SI02 SI01 SI00 N A operate SCK02 S...

Page 256: ...ed maskable inter rupt request or RESET signal input 1 Release by interrupt request The HALT mode is released unconditionally by an unmasked maskable interrupt request regardless of its priority level However if the HALT mode is entered during execution of an interrupt handler the operation differs on interrupt priority levels as follows a If an interrupt request less prioritized than the currentl...

Page 257: ...ked interrupt request with a higher priority than the previous one is subsequently generated the program branches to the vector address for the latter interrupt 2 Release by RESET pin input This operation is the same as normal reset operation Release cause EI state DI state NMI request Branches to handler address Maskable interrupt request Branches to handler address or executes the next instructi...

Page 258: ...w Table 9 6 Operating States in IDLE Mode IDLE mode release Release operation is same as release from HALT mode The IDLE mode is released by NMI RESET signal input or an unmasked maskable interrupt request a Release by Interrupt input When the IDLE mode is released the NMI request is acknowledged If the IDLE mode is entered during the execution of NMI handler the IDLE mode is released but the inte...

Page 259: ...t or RESET signal input 1 Release by interrupt request The WATCH mode is released unconditionally by an unmasked maskable interrupt request regardless of its priority level After oscillator stabilization time has passed CPU starts operation However if the WATCH mode is entered during execution of an interrupt handler the operation differs on interrupt priority levels as follows a If an interrupt r...

Page 260: ...tion Remark Before entering the WATCH mode the SSCG and PLL are switched off by hardware After the WATCH mode has been released the SSCG and PLL can be switched on by software once However the start up of the SSCG and PLL cause always a certain delay of some Milliseconds During this time the clock operates but the CPU operation is suspended due to clock security reasons If it is required to have a...

Page 261: ... stopped but the contents of all registers and internal RAM prior to entering this mode are retained On chip other peripheral hardware operation is also stopped The state of the various hardware units in the WATCH mode is tabulated below Table 9 9 Operating States in WATCH Mode Sub WATCH mode release The SUB WATCH mode can be released by a non maskable interrupt request an unmasked maskable interr...

Page 262: ...terrupt is not acknowledged The interrupt request itself is retained b If an interrupt request including a non maskable one priorities than the currently serviced interrupt request is generated the interrupt request is acknowledged along with the SUB WATCH mode release Table 9 10 Operation after SUB WATCH mode release by interrupt request Remark If SUB WATCH mode is entered during execution of a p...

Page 263: ...eset operation The Oscillator stabilization time must be ensured by reset input Figure 9 11 Sub Watch mode released by RESET input Main Oscillation circuit stop Sub Watch mode setting Main Oscillation circuit System clock Main OSC STOP state RESET signal Internal system reset signal Ensuring elapse of oscillation stabilization time by RESET ...

Page 264: ...eleased the PLL can be switched on by soft ware again once However the start up of the PLL causes always a certain delay of some Milliseconds During this time the clock operates but the CPU operation is suspended due to clock security reasons If it is required to have a fast response when waking up from SUB WATCH mode the PLL should not be re enabled after waking up as this causes again the delay ...

Page 265: ...s but the contents of all registers and internal RAM prior to entering this mode are retained V850E CA2 peripherals operations are also stopped except Sub oscillator and Watchdog timer in case of SOSTP bit 1 The state of the various hardware units in the software STOP mode is tabulated below Table 9 11 Operating States in STOP Mode Note When the VDD value is within the operating range However even...

Page 266: ...me as normal reset operation Oscillator stabilization time must be ensured by reset input Figure 9 13 STOP mode released by RESET input Oscillation circuit stop STOP mode setting Main Oscillation circuit System clock STOP state RESET signal Internal system reset signal Ensuring elapse of oscillation stabilization time by RESET ...

Page 267: ... PLL can be switched on any software again once However the start up of the SSCG and PLL cause always a certain delay of some Milliseconds During this time the clock operates but the CPU operation is suspended due to clock security reasons If it is required to have a fast response when waking up from STOP mode the SSCG and PLL should not be re enabled after waking up as this causes again the delay...

Page 268: ...struction Bit manipulation instruction SET1 CLR1 NOT1 instruction 2 Prepare data in any one of the general purpose registers to set to the specific register 3 Write arbitrary data to the command register PRCMD 4 Set the power save control register PSC with the following instructions Store instruction ST SST instruction Bit manipulation instruction SET1 CLR1 NOT1 instruction 5 Assert the NOP instru...

Page 269: ...am may result 2 Although the data written to the PHCMD register is dummy data use the same register as the general register used in specific register setting 4 for writing to the PHCMD register 3 The same method should be applied when using a general register for addressing 3 At least 5 NOP instructions must be inserted after executing a store instruction to the PSC register to set software STOP o...

Page 270: ... Main clock oscillator enable control bit 1 Main oscillator remains stopped after sub Watch mode release The CPU will start from sub clock 0 Main oscillator will be enabled after sub Watch mode release and used for CPU clock gener ation after the oscillation stabilization counter expires If this bit is cleared after sub Watch mode release the main oscillator will start After the oscilla tion stabi...

Page 271: ... bit timer counter that can perform the following operations 2 capture compare register Programmable pulse generator function Interval timer function PWM output External signal cycle measurement sub oscillator calibration function Remark In this Timer C chapter following indexes were consequently used n 0 1 for each of the 2 Timer C Capture Compare Channels ...

Page 272: ...generated by CCC01 match signal Overflow interrupt request 1 source INTTMC0 generated upon overflow of TMC0 register Timer counter count clock sources 1 type internal peripheral clock cycle One of two operation modes when the timer counter overflows can be selected free running mode or overflow stop mode The timer counter can be cleared by match of timer counter and compare register External pulse...

Page 273: ... 1 Block Diagram of Timer C Remark fPCLK internal peripheral clock PSM CMODE Sub Clock Calibration TIC00 Edge Detection TIC01 Edge Detection INTWT fPCLK fX 1 2 1 4 1 8 1 16 1 32 1 64 1 128 1 256 R Q S Q TMC1 16 bit CCC00 CCC01 INTTMC0 INTCCC0 INTCCC1 TOC0 Clear start fCOUNT ...

Page 274: ...y be read If writing is performed to the TMC0 register the subsequent operation is undefined 2 If the CAE bit of the TMCC00 register is cleared to 0 a reset is performed asynchronously TMC0 performs the count up operations of an internal count clock Timer starting and stopping are controlled by the CE bit of Timer C control register 0 TMCC00 Timer Count Clock Register Read Write Generated Interrup...

Page 275: ... fPCLK 64 fPCLK 128 and fPCLK 256 by the TMCC00 register Remark fPCLK internal peripheral clock An overflow interrupt can be generated if the timer overflows Caution The count clock cannot be changed while the timer is operating The conditions when the TMC0 register becomes 0000H are a Asynchronous reset CAE bit of TMCC00 register 0 RESET input b Synchronous reset CE bit of TMCC00 register 0 The C...

Page 276: ...1 bit and CMS0 bit specifications of Timer C control register 1 TMCC01 These registers can be read written in 16 bit units However write operations can only be performed in compare mode Figure 10 3 Capture Compare Register 0 CCC00 Figure 10 4 Capture Compare Register 1 CCC01 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value CCC00 FFFF F602H 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Add...

Page 277: ...etting CCC0n registers to compare registers CMS1 and CMS0 of TMCC01 1 When these registers are set to compare registers the TMC0 and register values are compared for each timer count clock and an interrupt is generated by a match If the CCLR bit of Timer C control register 1 TMCC01 is set 1 the TMC0 value is cleared 0 at the same time as a match with the CCC00 register it is not cleared 0 by a mat...

Page 278: ...C0 overflow 0 No overflow 1 Overflow The OVF bit becomes 1 when TMC0 changes from FFFFH to 0000H An overflow interrupt request INTTMC0 is generated at the same time However if CCC00 is set to the compare mode CMS0 bit of the TMCC01 register 1 and match clear during comparison of TMC0 and CCC00 is enabled CCLR bit of TMCC01 register 1 and TMC0 is cleared to 0000H following match at FFFFH TMC0 is co...

Page 279: ...K internal peripheral clock 1 CE Controls the operation of TMC0 0 Disable count timer stopped at 0000H and does not operate 1 Perform count operation Caution If CE 0 the external pulse output TOC0 becomes inactive level The active level of TOC0 output is set with the ALV bit of the TMCC01 register 0 CAE Controls the internal count clock fCOUNT 0 Asynchronously reset entire TMC0 unit Stop base cloc...

Page 280: ...r the flip flop of the TOC0 output Figure 10 6 Timer C control Register 1 TMCC01 1 2 7 6 5 4 3 2 1 0 Address Initial value TMCC01 OST ENTO ALV 0 CCLR 0 CMS1 CMS0 FFFF F608H 20H Bit Position Bit name Function 7 OST Setting of the timer operation after overflow 0 After overflow the count operation is continued free running mode 1 After overflow the count operation is stopped overflow stop mode The c...

Page 281: ...eration 0 Disable clearing 1 Enable clearing TMC0 is cleared when CCC00 and TMC0 match during com pare operation 1 CMS1 Selects operation mode of capture compare register CCC01 0 Register operates as capture register 1 Register operates as compare register 0 CMS0 Selects operation mode of capture compare register CCC00 0 Register operates as capture register 1 Register operates as compare register...

Page 282: ...ange the bits of SESC0 register during timer operation If they have to be changed they must be changed after setting the CE bit of the TMCC00 register to 0 If the SESC0 register is overwritten during timer operation the operation is not guaranteed Figure 10 7 Valid Edge Selection Register SESC0 Remark n 0 1 7 6 5 4 3 2 1 0 Address Initial value SESC0 0 0 0 0 IES11 IES10 IES01 IES00 FFFF F609H 00H ...

Page 283: ...timer output signal TOC0 can be set or reset Also a capture operation that holds the TMC0 count value in the CCC00 or CCC01 register is performed synchronized with the valid edge that was detected from the external interrupt request input pin as an external trigger The capture value is held until the next capture trigger is generated Figure 10 8 Timing of basic operation of Timer C 0001H 0000H 000...

Page 284: ...000H Also the overflow interrupt INTTMC0 is not generated When the TMC0 counter register is changed from FFFFH to 0000H because the CE bit changes from 1 to 0 the TMC0 register is considered to be cleared but the OVF bit is not set to 1 and no INTTMC0 interrupt is generated Also timer operation can be stopped after an overflow by setting the OST bit of the TMCC01 register to 1 When the timer is st...

Page 285: ...INTCCC00 or INTCCC01 n 0 1 is generated by TICn0 or TICn1 signal input and is used as an external trigger capture trigger The valid edge of the capture trigger is set by valid edge selection register SESC0 The TMC0 count value during counting is captured and held in the capture register synchronized with that capture trigger signal The capture register value is held until the next capture trigger ...

Page 286: ... rising and falling edges are set as capture triggers the input pulse width from an external source can be measured Figure 10 11 Timing of capture for pulse width measurement both edges Remark D0 to D2 TMC0 count values TMC0 Count start CE 1 Overflow OVF 1 D0 D1 D2 D0 D1 D2 TIC01 TMC0 count values Capture register CCC00 ...

Page 287: ...ponding port pins P5 to Timer C input PM5 to input PMC5 to Timer C0 2 set CAE bit of TMCC00 register to 1 for activating the Timer C peripheral 3 set the valid edge of the TICn0 pin with the IES01 and IES00 bits of the SESC0 register here for rising edge IES01 0 IES00 1 4 set CMS1 and CMS0 bits of TMCC01 register to 0 5 set CE bit to enable the counter and start operation Operation 1 the valid edg...

Page 288: ... Dx that was captured in the CCC01 register according to the x th valid edge input of the TIC01 pin and the TMC0 register s count value D x 1 that was captured in the CCC01 register according to the x 1 th valid edge input of the TIC01 pin and multiplying the value of this difference by the cycle of the clock control signal Figure 10 12 Timing of cycle measurement operation Caution An overflow mus...

Page 289: ...A compare operation that compares the value that was set in the compare register and the TMC0 count value is performed If the TMC0 count value matches the value of the compare register which had been set in advance a match signal is sent to the output control circuit The match signal causes the timer output pin TOC0 to change and an interrupt request signal INTCCC00 INTCCC01 to be generated at the...

Page 290: ...he value that was set in advance in the CCC00 register as the interval Setting method 1 set corresponding port pins P5 to Timer C input PM5 to input PMC5 to Timer C0 2 set CAE bit to 1 for activate the Timer C peripheral 3 set CLR and CMS0 bit of TMCC01 register to 1 4 set CE bit to enable the counter and start operation Operation 1 When the counter value of the TMC0 register matches the setting v...

Page 291: ... TOC0 pin is reset The output level set reset depends on the settings of the ALV and ENTO bits of the TMCC01 register Table 10 2 TOC0 Output Control Figure 10 15 Timing of PWM output operation overview ENTO ALV TOC0 Output External Pulse Output Output Level 0 0 Disable High level 0 1 Disable Low level 1 0 Enable When the CCC00 register is matched Low level When the CCC01 register is matched High l...

Page 292: ...ration 1 When the counter value of the TMC0 register matches the setting value of the CCC00 register the TOC0 output becomes active 2 When the counter value of the TMC0 register matches the setting value of the CCC01 register the TOC0 output becomes inactive This enables a PWM of an arbitrary frequency to be output Figure 10 16 Timing of PWM output operation detail Remarks 1 p Setting value of CCC...

Page 293: ...s between the peripheral macro clock prescaler output and direct clock from the main oscillator input In the Jupiter device the Timer C0 will be used to meas ure the sub clock frequency by capture operation of the Watch timer interrupts The device can be switched to Watch mode during measurement operation To enable usage of the sub watch mode for real watch timer applications a sub oscillator cali...

Page 294: ...on calibration feature in Jupiter clock controller by setting the CMODE bit in the PSM register to 1 3 Enable Timer C0 and set CCC01 to capture mode 4 On the next watch timer wake up interrupt the captured value of CCC01 gives the modulo counter for main oscillator clocks per watch timer interrupt To achieve a higher accuracy measurement capture value of the n th watch timer interrupt should be ta...

Page 295: ...an the analog noise elimination time two cycles of the input clock 4 The operation of an interrupt output INTCCC00 or INTCCC01 is automatically determined according to the operating state of the capture compare registers CCC00 CCC01 When the capture compare registers are used for a capture mode the external trigger TIC00 TIC01 is used for valid edge detection When the capture compare registers are...

Page 296: ...os can be selected related to the internal peripheral clock fPCLK The range is from fPCLK 2 to fPCLK 256 Interrupt request sources 1 Compare match interrupt INTTMDn generated with CMDn match signal Timer clear TMDn register can be cleared by CMDn register match Remark In this Timer D chapter following indexes is consequently used n 0 1 for each of the 2 Timer D fPCLK Internal peripheral clock Figu...

Page 297: ... Dn Configuration List n 0 1 Remarks 1 fPCLK Internal peripheral clock 2 S R Set Reset Timer Count Clock Register R W Generated Interrupt Signal Capture Trigger Timer Output S R Other Functions Timer Dn fPCLK 2 fPCLK 4 fPCLK 8 fPCLK 16 fPCLK 32 fPCLK 64 fPCLK 128 fPCLK 256 TMDn R CMDn R W INTTMDn TMCDn R W ...

Page 298: ...formed asynchronously 2 If the CE bit of the TMCDn register is cleared to 0 a reset is performed synchronized with the internal clock Similarly a synchronized reset is performed after a match with the CMDn register and after an overflow 3 The count clock must not be changed during a timer operation If it is to be overwritten it should be overwritten after the CE bit is cleared to 0 4 Up to fPCLK 2...

Page 299: ...er side is read out CMDn can be read written in 16 bit units Figure 10 20 Timer Dn Compare Register CMDn n 0 1 Cautions 1 A write operation to the a CMDn register requires fPCLK 2 clocks until the value that was set in the CMDn register is transferred to internal units When writing continuously to the CMDn register be sure to reserve a time interval of at least fPCLK 2 clocks 2 The CMDn register c...

Page 300: ...al U15839EE1V0UM00 Figure 10 21 Timing of Timer Dn Operation a When TMDn CMDn b When TMDn CMDn Remarks 1 p TMDn value when overwritten 2 q CMDn value when overwritten 3 n 0 1 TMDn CAE CE CMDn INTTMDn q p q q TMDn CAE CE CMDn INTTMDn m FFFFH n n n ...

Page 301: ...t change the CS2 to CS0 bits during timer operation If they are to be changed they must be changed after setting the CE bit to 0 If the CS2 to CS0 bits are overwritten during timer operation the operation is not guaranteed 1 CE Count Enable Controls the operation of TMDn n 0 1 0 Disable count timer stopped at 0000H and does not operate 1 Perform count operation Caution CE bit is not cleared even i...

Page 302: ...o be cleared to 0 at the next count timing This function enables Timer Dn to be used as an interval timer CMDn can also be set to 0 In this case when an overflow occurs and TMDn becomes 0 a match is detected and INTTMDn is generated Although the TMDn value is cleared to 0 at the next count timing INTTMDn is not generated according to this match Figure 10 23 Timing of Compare Operation 1 2 a When C...

Page 303: ...User s Manual U15839EE1V0UM00 Figure 10 23 Timing of Compare Operation 2 2 b When CMDn is set to 0 Remark Interval time FFFFH 2 Count clock cycle 1 0 0 0 FFFFH Overflow TMDn CMDn TMDn clear Match detected INTTMDn Count up Clear fCOUNT ...

Page 304: ...s refer to Figure 10 23 Timing of Com pare Operation 1 2 on page 302 The setup procedure is shown below n 0 1 1 Set the CAE bit to 1 2 Set each register Select the count clock using the CS2 to CS0 bits of the TMCDn register Set the compare value in the CMDn register 3 Start counting by setting the CE bit to 1 4 If the TMDn register and CMDn register s values match an INTTMDn interrupt is generated...

Page 305: ...n the CMDn register is transferred to internal units When writing continuously to the CMDn register be sure to secure a time interval of at least fPCLK 2 clocks 5 The CMDn register can be overwritten only once during a timer counter operation from 0000H until an INTTMDn interrupt is generated due to a match of the TMDn register and CMDn register If this cannot be secured make sure that the CMDn re...

Page 306: ...lse interval and frequency measurement counter event counter Interval timer Programmable pulse output PWM output timer Remark In this Timer Gn chapter following indexes were consequently used m 1 to 4 for the free assignable Input Output channels n 0 1 for each of the 2 Timer G instance in Jupiter x 0 1 for bit index i e one of the 2 counters of each Timer Gn y 0 to 5 for all of the 6 capture comp...

Page 307: ...overflow interrupt requests 2 types In free run mode the INTTMGn0 INTTMGn1 interrupt is generated when the count value of TMGn0 TMGn1 toggles from FFFFH to 0000H In match and clear mode the INTTMGn0 INTTMGn1 interrupt is generated when the count value of TMGn0 TMGn1 matches the GCC0 GCC1 value PWM output function Control of the outputs of TOGn1 through TOGn4 pin in the compare mode PWM output can ...

Page 308: ...Gn5 INTCCGn0 INTCCGn1 INTCCGn2 INTCCGn3 INTCCGn4 INTCCGn5 TOGn1 Clear TOGn3 TOGn4 Clear Noise Elimination Edge Detection Noise Elimination Edge Detection Noise Elimination Edge Detection Noise Elimination Edge Detection Noise Elimination Edge Detection fCOUNT0 fCOUNT1 GCCn1 16 bit capture compare GCCn2 16 bit capture compare GCCn3 16 bit capture compare GCCn4 16 bit capture compare GCCn5 16 bit ca...

Page 309: ...ripheral clock 2 n 0 1 Timer Count Clock Register R W Generated Interrupt Signal Capture Trigger Timer Output PWM Timer Gn fPCLK fPCLK 2 fPCLK 4 fPCLK 8 fPCLK 16 fPCLK 32 fPCLK 64 fPCLK 128 TMGn0 R INTTMGn0 TMGn1 R INTTMGn1 GCCn0 R W INTCCGn0 TIGn0 GCCn1 R W INTCCGn1 TIGn1 TOGn1 GCCn2 R W INTCCGn2 TIGn2 TOGn2 GCCn3 R W INTCCGn3 TIGn3 TOGn3 GCCn4 R W INTCCGn4 TIGn4 TOGn4 GCCn5 R W INTCCGn5 TIGn5 ...

Page 310: ...ters GCCn0 GCCn5 Counter clear can be set by software Counter stop can be set by software These registers can be read in 16 bit units Figure 10 25 Timer Gn Counter 0 Value Registers TMGn0 Figure 10 26 Timer Gn Counter 1 Value Registers TMGn1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value TMG00 FFFF F648H 0000H TMG10 FFFF F688H 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initia...

Page 311: ...h and clear mode is used to reduce the number of valid bits of the counter TMGn0 TMGn1 These registers can be read written in 16 bit units Caution If in Compare Mode write to this registers before POWER and ENFGx bit x 0 1 are 1 at the same time Figure 10 27 Timer Gn counter TMGn0 assigned Capture Compare Register GCCn0 Remark This register is assigned fix to timebase TMGn0 Figure 10 28 Timer Gn c...

Page 312: ... compare value and the TOGnm Output m 1 to 4 can generate a PWW if they are activated These registers can be read written in 16 bit units Figure 10 29 Timer Gn free assignable Capture Compare Registers GCCnm m 1 to 4 Remarks 1 In capture mode only reading is possible 2 In compare mode read write is possible 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value GCC01 FFFF F64EH 0000H GCC11 FF...

Page 313: ...ster are cleared the TOGnm pins m 1 to 4 are inactive all the time 1 operation enable Remark At least 7 peripheral clocks fPCLK are need to start the timer function 14 OLDE Set Output Delay Operation 0 Don t perform output delay operation 1 Set output delay to n count clocks Caution When the POWER Bit is set the rewriting of this Bit is prohibited Simultaneously writing with the POWER bit is allow...

Page 314: ...unter is cleared and the interrupt INTCCGn5 INTCCGn0 occurs Caution When the POWER bit is set the rewriting of this Bits are prohibited Simultaneously writing with the POWER bit is allowed 3 1 CLRGx Specifies software clear for TMGx x 0 1 0 Continue TMGx operation 1 Clears 0 the count value of TMGx the corresponding TOGx is deactivated Remark TMGx starts 1 peripheral clock after this bit is set th...

Page 315: ... 0 1 This register is the high byte of the TMGMn register This register can be read written in 8 bit or 1 bit units Figure 10 32 Timer Gn Mode Register Low TMGMnH The explanation of the bit 7 to 0 is the same as the bit 15 to 8 of the TMGMn register 7 6 5 4 3 2 1 0 Address Initial value TMGM0L CCSG5 CCSG0 0 0 CLRG1 TMG1E CLRG0 TMG0E FFFF F640H 00H TMGM1L CCSG5 CCSG0 0 0 CLRG1 TMG1E CLRG0 TMG0E FFF...

Page 316: ... IEG11 IEG10 IEG01 IEG00 FFFF 642H 0000H TMGCM1H TBG4 TBG3 TBG2 TBG1 IEG51 IEG50 IEG41 IEG40 IEG31 IEG30 IEG21 IEG20 IEG11 IEG10 IEG01 IEG00 FFFF 682H 0000H Bit Position Bit Name Function 15 to 12 TBGm Assigns Capture Compare registers GCCn1 to GCCn4 to one of the 2 counters TMGn0 or TMGn1 0 Set TMGn0 as the corresponding counter to GCCnm register and TIGm TOGnm pin 1 Set TMGn1 as the correspondin...

Page 317: ...This register is the high byte of the TMGCMnH register This register can be read written in 8 bit or 1 bit units Figure 10 35 Timer Gn Channel Mode Register TMGCMnH The explanation of the bit 7 to 0 is the same as the bit 15 to 8 of the TMGCMnH register 7 6 5 4 3 2 1 0 Address Initial value TMGCM0L IEG31 IEG30 IEG21 IEG20 IEG11 IEG10 IEG01 IEG00 FFFF F642H 00H TMGCM1L IEG31 IEG30 IEG21 IEG20 IEG11...

Page 318: ...OCTLG1H SWFG4 ALVG4 CCSG4 0 SWFG3 ALVG3 CCSG3 0 SWFG2 ALVG2 CCSG2 0 SWFG1 ALVG1 CCSG1 0 FFFF F684H 4444H Bit Position Bit Name Function 15 11 7 3 SWFGm Fixes the TOGnm pin output level according to the setting of ALVGm bit 0 disable TOGnm to inactive level 1 enable TOGnm 14 10 6 2 ALVGm Specifies the active level of the TGOm pin output 0 Active level is 0 1 Active level is 1 Caution Don t write th...

Page 319: ...r High OCTLGnH This register is the low byte of the OCTLGnH register This register can be read written in 8 bit or 1 bit units Figure 10 38 Timer Gn Output Control Register High OCTLGnH The explanation of the bit 7 to 0 is the same as the bit 15 to 8 of the OCTLGn register 7 6 5 4 3 2 1 0 Address Initial value OCTLG0L SWFG2 ALVG2 CCSG2 0 SWFG1 ALVG1 CCSG1 0 FFFF F644H 44H OCTLG1L SWFG2 ALVG2 CCSG2...

Page 320: ...Address Initial value TMGST0 ENFG1 ENFG2 CCFG5 CCFG4 CCFG3 CCFG2 CCFG1 CCFG0 FFFF F646H 00H TMGST1 ENFG1 ENFG2 CCFG5 CCFG4 CCFG3 CCFG2 CCFG1 CCFG0 FFFF F686H 00H Bit Position Bit Name Function 5 to 0 CCFGy Indicates TMGn0 or TMGn1 overflow status 0 No overflow 1 Overflow Caution The CCFGy bit is set if a TMGn0 TMGn1 overflow occurs This flag is only updated if the corresponding GCCy register was r...

Page 321: ...e where the count clock is set to fPCLK 2 However 0FFFH is set in GCCn0 Similar delays are added also when a transition is made from the active to inactive level So a relative pulse width is guaranteed Figure 10 40 Timing of Output delay operation In this case the count clock is set to fPCLK 2 Output pin delay 1 fCOUNT TOGn1 0 TOGn2 1 TOGn3 2 TOGn4 3 FFFEH 0002H 0003H 0001H 0000H FFFFH 0004H TMGCn...

Page 322: ...nerated only when the value of the GCCn0 register is FFFFH 2 An interrupt is generated only when the value of the GCCn0 register is not FFFFH Remark The setting of the CCSGm bit in combination with the SWFGm bit sets the mode for the tim ing of the actualization of new compare values In compare mode the new compare value will be immediately active In PWM mode the new compare value will be active f...

Page 323: ...re values In compare mode the new compare value will be immediately active In PWM mode the new compare value will be active first after the next overflow or match clear of the assigned counter TMG0 TMG1 Register setting value State of each output pin CCSG5n TBGm SWFGm CCSGm INTTMGn1 INTCCGn5 INTCCGnm TOGnm 0 Free run mode 1 0 0 Overflow interrupt TI5 edge detection TIm edge detection Tied to inact...

Page 324: ...nting up from 0000H to FFFFH generates an overflow and start again In the match and clear mode which is described in Chapter 10 3 8 on page 335 the fixed assigned register GCCn0 GCCn5 is used to reduce the bit size of the counter TMGn0 TMGn1 1 Capture operation free run Basic settings m 1 to 4 Bit Value Remark CCSGn0 0 free run mode CCSGn5 0 SWFGm 0 disable TOGnm TBGm X assign counter for GCCnm 0 ...

Page 325: ... is stored in GCCny and an edge detection interrupt INTCCGny is output 2 When the counter overflows an overflow interrupt INTTMGn0 or INTTMGn1 is generated 3 If an overflow has occurred between capture operations the CCFGy flag is set when GCCny is read Correct capture data by checking the value of CCFGy Using CCFGy When using GCCny as a capture register use the procedure below 1 After INTCCGny ed...

Page 326: ...uitry 3 to 4 periods of the count up signal are required from the input of a waveform to TIGn0 until a capture interrupt is output See Chapter 10 1 3 Basic configuration 1 16 bit counter TMC0 b Synchronous reset on page 275 0000H 0001H D0 D1 TMGn0 D0 GCCn0 Count start t FFFFH 0000H D2 D3 TIGn0 D1 D2 D3 Clear INTCCGn0 INTTMGn0 No overflow Overflow CCFGn0 No overflow fPCLK fCOUNTx ...

Page 327: ...ount clock are required from edge input until an interrupt signal is output and capture operation is performed The timing chart is shown below Basic settings x 0 1 and y 0 to 5 Figure 10 42 Timing of capture trigger edge detection free run Bit Value Remark CSEx2 0 Count clock fPCLK 4 CSEx1 1 CSEx0 0 IEGy1 1 detection of both edges IEGy0 1 t 2 t 3 t 4 t 5 t 6 t 7 t 7 t t 1 t 4 t 8 TMGn0 TMGn1 TIGn0...

Page 328: ... masking is performed to prevent the initial TIGny level from being recognized as an edge by mistake The timing chart for starting edge detection is shown below Basic settings x 0 1 and y 0 to 5 Figure 10 43 Timing of starting capture trigger edge detection Bit Value Remark CSEx2 0 Count clock fPCLK 4 CSEx1 1 CSEx0 0 IEGy1 1 detection of both edges IEGy0 1 0001H 0002H 0003H 0004H 0005H 0006H 0005H...

Page 329: ...MGn0 register 3 Write data to GCCnm 4 Start timer operation by setting POWER and TMG0E or TMG1E Compare Operation 1 When the value of the counter matches the value of GCCnm m 0 to 4 a match interrupt INTCCGnm is output 2 When the counter overflows an overflow interrupt INTTMGn0 INTTMGn1 is generated Figure 10 44 Timing of compare mode free run Data N is set in GCCn1 and the counter TMGn0 is select...

Page 330: ...m and INTTMGn0 INTTMGn1 are activated when the value of the counter changes from FFFFH to 0000H d When GCCnm is rewritten during operation When GCCn1 is rewritten from 5555H to AAAAH TMGn0 is selected as the counter The following operation is performed Figure 10 45 Timing when GCCn1 is rewritten during operation free run Caution To perform successive write access during operation for rewriting the...

Page 331: ... CSE02 to CSE00 bits TMGn0 register 3 Specify the active level of a timer output TOGnm pin with the ALVGm bit 4 When using multiple timer outputs the user can prevent TOGnm from becoming active simultaneously by setting the OLDE bit of TMGMHn register to provide step by step delays for TOGnm This capability is useful for reducing noise and current 5 Write data to GCCnm 6 Start timer operation by s...

Page 332: ...ransition until the next overflow occurs After the first overflow occurs TOGnm is activated 4 When the value of the counter matches the value of GCCnm TOGnm is deactivated and a match interrupt INTCCGnm is output The counter is not cleared but continues count up operation 5 The counter overflows and INTTMGn0 or INTTMGn1 is output to activate TOGnm The counter resumes count up operation starting wi...

Page 333: ...n FFFFH is set in GCCnm m 1 to 4 When FFFFH is set in GCCnm TOGnm outputs the inactive level for one clock period immediately after each counter overflow except the first overflow The figure shows the state of TOGn1 when FFFFH is set in GCCn1 and TMGn0 is selected Figure 10 48 Timing when FFFFH is set in GCCnm free run GCCn1 and TMGn0 are selected 0000H ENFG0 TMGn0 GCCn1 INTCCGn1 INTTMGn0 TOGn1 AL...

Page 334: ...peration free run GCCn1 and TMGn0 are selected If GCCn1 is rewritten to AAAAH after the second INTCCGn1 is generated as shown in the figure above AAAAH is reloaded to the GCCn1 register when the next overflow occurs The next match interrupt INTCCGn1 is generated when the value of the counter is AAAAH The pulse width also matches accordingly 5555H AAAAH AAAAH 5555H Match Match Match FFFFH ENFG0 TMG...

Page 335: ...k cycle with the CSE12 to CSE10 TMGn1 bits or CSE02 to CSE00 TMGn0 bits 3 Select a valid TIGm edge with the IEGm1 and IEGm0 bit A rising edge falling edge or both edges can be selected 4 Set an upper limit on the value of the counter in GCCn0 or GCCn5 5 Start timer operation by setting POWER bit and TMG0E bit or TMG1E bit Operation 1 When a specified edge is detected the value of the counter is st...

Page 336: ... page 327 Caution If two or more match and clear events occur between captures a software based measure needs to be taken to count INTCCGn0 or INTCCGn5 c When 0000H is set in GCCn0 or GCCn5 match and clear When 0000H is set in GCCn0 GCCn5 the value of the counter is fixed at 0000H and does not operate Moreover INTCCGn0 INTCCGn5 continues to be active d When FFFFH is set in GCCn0 or GCCn5 match and...

Page 337: ...e of the counter in GCCn0 or GCCn5 4 Write data to GCCnm 5 Start timer operation by setting the POWER bit and TMGxE bit x 0 1 Operation 1 When the value of the counter matches the value of GCCnm a match interrupt INTCCGnm is output 2 When the value of GCCn0 or GCCn5 matches the value of the counter INTCCGn0 or INTCCGn5 is output and the counter is cleared This operation is referred to as match and...

Page 338: ...is set in GCCn0 or GCCn5 match and clear When FFFFH is set in GCCn0 or GCCn5 operation equivalent to the free run mode is performed When an overflow occurs INTTMGn0 or INTTMGn1 is generated but INTCCGn0 or INTCCGn5 is not generated d When 0000H is set in GCCnm m 1 to 4 match and clear INTCCGnm is activated when the value of the counter becomes 0001H Note however that even if no data is set in GCCn...

Page 339: ...MGn0 is selected as the counter and 0FFFH is set in GCCn0 Figure 10 52 Timing when GCCnm is rewritten during operation match and clear Caution To perform successive write access during operation for rewriting the GCCny register n 1 to 4 you have to wait for minimum 7 peripheral clocks periods fPCLK Match Match 0555H 0AAAH 0AAAH 0555H INTCCGn1 TMGn0 ENFG0 Reload in 5 clock periods fPCLK GCCn1 Slave...

Page 340: ...TMGn0 bits 3 Specify the active level of a timer output TOGnm with the ALVGm bit 4 When using multiple timer outputs the user can prevent TOGnm from making transitions simultaneously by setting the OLDE bit of TMGMHn register This capability is useful for reducing noise and current 5 Set an upper limit on the value of the counter in GCCn0 or GCCn5 Timer Dn 0000H is forbidden 6 Write data to GCCnm ...

Page 341: ...ent 5 When the value of the counter matches the value of GCCnm TOGnm makes a transition to the inactive level and a match interrupt INTCCGnm is output 6 When the next match and clear event occurs INTCCGn0 INTCCGn5 is output and the counter is cleared The counter resumes count up operation starting with 0000H Example where the data N is set and the counter TMGn0 is selected 0FFFH is set in GCCn0 an...

Page 342: ...enerated but INTCCGn0 INTCCGn5 is not generated b When 0000H is set in GCCnm match and clear When 0000H is set in GCCnm TOGnm is tied to the inactive level The figure below shows the state of TOGn1 when 0000H is set in GCCn1 and TMGn0 is selected Note however that 0FFFH is set in GCCn0 Figure 10 54 Timing when 0000H is set in GCCnm match and clear 0000H ENFG0 TMGn0 GCCn1 INTCCGn1 INTCCGn0 Low High...

Page 343: ...e inactive level for only one clock period immediately after each match and clear event excluding the first match and clear event The figure below shows the state of TOGn1 when 0FFFH is set in GCCn0 and GCCn1 and TMGn0 is selected Figure 10 55 Timing when the same value as set in GCCn0 GCCn5 is set in GCCnm match and clear Match ENFG0 TMGn0 GCCn1 INTCCGn1 INTCCGn0 0FFFH 0FFFH 0FFFH 0FFFH TOGn1 ALV...

Page 344: ...nm TOGnm starts and continues outputting the active level immediately after the first match and clear event until count operation stops The figure shows the state of TOGn1 when 0FFFH is set in GCCn0 1FFFH is set in GCCn1 and TMGn0 is selected Figure 10 56 Timing when the value of GCCnm exceeding GCCn0 or GCCn5 match and clear Low ENFG0 TMGn0 GCCn1 INTCCGn1 INTCCGn0 0FFFH 0FFFH 0FFFH 1FFFH TOGn1 AL...

Page 345: ... GCCnm is rewritten during operation match and clear If GCCn1 is rewritten to 0AAAH after the second INTCCGn1 is generated as shown in the figure above 0AAAH is reloaded to the GCCn1 register when the next overflow occurs The next match interrupt INTCCGn1 is generated when the value of the counter is 0AAAH The pulse width also matches accordingly 0555H 0AAAH 0AAAH 0555H Match Match 0FFFH TMGn0 ENF...

Page 346: ...nding on the timing This is because the count up signal of the counter is used for sampling timing The upper figure below shows the timing chart for performing edge detection The lower figure below shows the timing chart for not performing edge detection Basic settings x 0 1 and y 0 to 5 Figure 10 58 Timing of Edge detection noise elimination Bit Value Remark CSEx2 0 Count clock fPCLK 4 CSEx1 1 CS...

Page 347: ...e level of the TOGnm pins m 1 to 4 When in compare mode the rewriting of the GCCn0 or GCCn5 register is prohibited In compare mode these registers set the value for the match and clear mode of the TMGn0 and TMGn1 counter 3 Functionality When the POWER bit is set to 0 regardless of the SWFGm bit OCTLGnL and OCTLGnH registers the TOGnm pins are tied to the inactive level The SWFGm bit enables or dis...

Page 348: ...ter than POWER bit than the Timer Gn needs 4 peripheral clocks periods fPCLK to start counting When a capture register GCCny is read the capturing is disable during read operation This is intended to prevent undefined data during reading So if a contention occurs between an external trigger signal and the read operation capture operation may be cancelled and old data may be read GCCnm register m 1...

Page 349: ... watch timer generates an interrupt request INTWT at time intervals of 500 µs to 16 4 s by using the clock selector for the Watch Timer see Chapter 8 2 Configuration on page 198 2 Interval timer The interval timer generates an interrupt request INTWTI at time intervals of 500 µs to 2 1 s fW 210 Selector 11 bit prescaler fW 28 fW 2 7 fW 26 fW 25 fW 24 5 bit counter INTWT INTWTI WTM0 WTM1 WTM3 WTM4 ...

Page 350: ... of the 5 bit counter and sets the set time of the watch flag WTM is set by a 1 bit or 8 bit memory manipulation instruction Figure 11 2 Watch Timer Mode Control Register WTM 1 2 Item Configuration Counter 5 bits 1 Prescaler 11 bits 1 Control register Watch timer mode control register WTM 7 6 5 4 3 2 1 0 Address R W After Reset WTM WTM7 WTM6 WTM5 WTM4 WTM3 WTM2 WTM1 WTM0 FFFF F560H R W 00H WTM7 Se...

Page 351: ...WTM 2 2 Remark fW Watch timer clock frequency WTM3 WTM2 Selects Set Time of Watch Flag 0 0 214 fW 0 1 213 fW 1 0 25 fW 1 1 24 fW WTM1 Controls Operation of 5 bit Counter 0 Clears after operation stops 1 Starts WTM0 Enables Operation of Watch Timer 0 Stops operation clears both prescaler and timer 1 Enables operation ...

Page 352: ...o the Watch Timer With the WTSELn bits n 0 1 of the CKC register 6 different clocks can be switched as the Watch Timer clock Table 11 2 Selection of the Watch Timer Clock Note WTSEL1 bit of CKC register Remark X don t care CKC Register WTM Register fW WDTSEL1 fXXT WDTSEL0 WTM7 fX 4 MHz fX 5 MHz 0 fX 128 0 1 31250 Hz 39063 Hz 1 7813 Hz 9766 Hz X 0 977 Hz 1221 Hz 1 fXT 0 1 32000 Hz 1 8000 Hz X 0 100...

Page 353: ...of the watch timer mode control register WTM are set to 1 The WTM0 bit has to be set to 1 either it was 1 before In that case the frequency of the running 11 bit prescaler is not influenced The 5 bit watch timer function prescaler is stopped and cleared if the WTM1 bit is set to 0 Caution If the 5 bit watch timer function prescaler is clocked by fW 29 WTM3 0 This prescaler is started with the next...

Page 354: ...rval of the Watch Timer The interval time can be selected by the WTM4 through WTM6 bits of the watch timer mode control register WTM Table 11 4 Example for Interval Time of Interval Timer Remarks 1 fX 4 MHz 2 WTSEL0 bit 1 CKC register fCKSEL2 fXXT 32 3 fW Watch timer clock frequency 4 interval times change accordingly if fX 4 MHz WTM6 WTM5 WTM4 Interval Time fW fCKSEL2 fX 4096 fW fCKSEL1 fXT 32 KH...

Page 355: ... CKC register Clock Generator and the WTM Watch Timer register Remarks 1 fW Watch timer clock frequency 2 n Interval timer operation numbers Start 5 bit counter Overflow Overflow 0H Interrupt time of watch timer Interrupt time of watch timer Interval time T Count clock fW or fW 211 Watch timer interrupt INTWT Interval timer interrupt INTWTI nT nT Note Note Interval time T ...

Page 356: ...356 Preliminary User s Manual U15839EE1V0UM00 MEMO ...

Page 357: ... Remark fWD Watchdog Timer clock frequency depends on clock tree settings 1 Interrupt mode This mode detects program runaway When runaway is detected a non maskable interrupt can be generated 2 RESET mode This mode detects program runaway When runaway is detected a hardware RESET is generated f Clear Prescaler Internal bus Selector fx 213 fx 214 fx 215 fx 216 fx 217 fx 218 fx 219 fx 221 Output Con...

Page 358: ...tion The watchdog timer consists of the following hardware Table 12 1 Watchdog Timer Configuration Item Configuration Control registers Watchdog timer clock selection register WDCS Watchdog timer mode register WDTM Watch Dog Timer command register WCMD Watch Dog Timer command status register WPHS ...

Page 359: ...struction Figure 12 2 Watchdog Timer Clock Selection Register WDCS Note This are only 2 examples for fWD The clock depends on the clock tree settings and the external main oscillator resonators 4 or 5 MHz 7 6 5 4 3 2 1 0 Address R W After reset WDCS 0 0 0 0 0 WDCS2 WDCS1 WDCS0 FFFF F571H R W 00H WDCS2 WDCS1 WDCS0 Clock Overflow TimeNote fWD fX 4 MHz main clock fWD fXT 32 KHz sub clock 0 0 0 213 fW...

Page 360: ...register cannot be cleared to 0 by software Therefore when the count starts the count cannot be stopped except by RESET input 2 The WDTM4 bit has to set to 1 at the initialisation of the WDT Cautions 1 Data is set to the CKC register by the following sequence Write any 8 bit data to the command register WCMD Write the set data to the destination register WDTM 2 If RUN is set to 1 and the watchdog ...

Page 361: ...imer Mode Register WCMD 4 Watchdog timer command status register WPHS The WPHS register monitors the success of a write instruction to the WDTM register If the write to WDTM fails because of violating the special instruction sequence writing WCMD immediately before WDTM the WPRERR flag is set WPHS can be accessed by 8 bit or 1 bit memory instructions Caution The WPERR bit can only be reset by soft...

Page 362: ...atchdog timer when operating the HALT mode since the watchdog timer is running in HALT mode For details of the possible time settings please refer to Figure 12 2 Watchdog Timer Clock Selec tion Register WDCS on page 359 2 Watchdog Timer Mode 2 RESET Set WDTM4 bit and WDTM3 bit of the watchdog timer mode register WDTM to 1 to operate as a watchdog timer in RESET request mode to detect program runaw...

Page 363: ...ls Clocked serial interfaces CSI00 to CSI02 3 channels FCAN controller 4 channels Remark For details about the FCAN controller refer to Chapter 13 FCAN Interface Function UART50 and UART51 transmit receive 1 byte serial data following a start bit and support full duplex communication CSI00 to CSI02 perform data transfer according to three types of signals namely serial clocks SCK00 to SCK02 serial...

Page 364: ...or Framing error Overrun error Interrupt sources 3 types Reception error interrupt INTSERn Interrupt is generated according to the logical OR of the three types of reception errors Reception completion interrupt INTSRn Interrupt is generated when receive data is transferred from the shift register to the reception buffer register after serial transfer is completed during a reception enabled state ...

Page 365: ...ch indicates the hold status of TXBn data and the transmission shift register data flag which indicates whether transmission is in progress 4 Reception control parity check The receive operation is controlled according to the contents set in the ASIMn register A check for parity errors is also performed during a receive operation and if an error is detected a value corresponding to the error conte...

Page 366: ...rol parity A transmit operation is controlled by adding a start bit parity bit or stop bit to the data that is written to the TXBn register according to the contents that were set in the ASIMn register Figure 13 1 Asynchronous Serial Interfaces Block Diagram Remark n 0 1 Parity Framing Overrun Internal bus Asynchronous serial interface mode register n ASIMn Reception buffer register n RXBn Recepti...

Page 367: ...eration clock stops fixed to low level and an asynchronous reset is applied to internal UART5n latch The TXDn pin output is low level when the Power bit 0 and high level when the Power bit 1 Therefore perform Power setting in combination with port mode regis ter PM1 PM2 PM6 so as to avoid malfunction on the other side at start up Set the port to the output mode after setting the Power bit to 1 Inp...

Page 368: ...may not be successful For details about the base clock refer to 13 2 6 Dedicated baud rate generators BRG of UART5n n 0 1 on page 384 4 3 PS1 PS0 Controls parity bit PS1 PS0 Transmit Operation Receive Operation 0 0 Don t output parity bit Receive with no parity 0 1 Output 0 parity Receive as 0 parity 1 0 Output odd parity Judge as odd parity 1 1 Output even parity Judge as even parity Cautions 1 T...

Page 369: ...7 bits 1 8 bits Caution To overwrite the CL bit first clear 0 the TXE and RXE bits 1 SL Specifies stop bit length of transmit data 0 1 bit 1 2 bits Caution To overwrite the SL bit first clear 0 the TXE bit Since reception is always done using a single stop bit the SL bit setting does not affect receive operations 0 ISRM Enables disables generation of reception completion interrupt requests when an...

Page 370: ...Registers ASIS0 ASIS1 7 6 5 4 3 2 1 0 Address Initial value ASIS0 0 0 0 0 0 PE FE OVE FFFF FA03H 00H ASIS1 0 0 0 0 0 PE FE OVE FFFF FA43H 00H Bit Position Bit Name Function 2 PE This is a status flag that indicates a parity error 0 When the ASIMn register s Power and RXE bits are both set to 0 or when the ASISn register has been read 1 When reception was completed the transmit data parity did not ...

Page 371: ... cannot be guaranteed when data is written to TXBn register 7 6 5 4 3 2 1 0 Address Initial value ASIF0 0 0 0 0 0 0 TXBF0 TXSF0 FFFF FA05H 00H ASIF1 0 0 0 0 0 0 TXBF0 TXSF0 FFFF FA45H 00H Bit Position Bit Name Function 1 TXBF This is a transmission buffer data flag 0 When the ASIMn register s Power or TXE bits is 0 or when data has been transferred to the transmission shift register Data to be tra...

Page 372: ...Bn register are retained and no processing is performed for transferring data to the RXBn register even when the shift in processing of one frame is completed Also no reception completion interrupt is generated When 7 bits is specified for the data length bits 6 to 0 of the RXBn register are transferred for the receive data and the MSB bit 7 is always 0 However if an overrun error OVE occurs the r...

Page 373: ...and a transmission completion interrupt request INTSTn is generated synchronized with the completion of the transmission of one frame from the transmission shift register For information about the timing for generating this interrupt request refer to 13 2 5 2 Transmit operation on page 376 When TXBF bit 1 in the ASIFn register writing must not be performed to TXBn register This register can be rea...

Page 374: ...r a reception completion interrupt INTSRn is generated when an error occurs can be specified according to the ISRM bit of the ASIMn register When reception is disabled no reception error interrupt is generated 2 Reception completion interrupt INTSR0 INTSR1 When reception is enabled a reception completion interrupt is generated when data is shifted in to the reception shift register and transferred...

Page 375: ... in Figure 13 7 The character bit length within one data frame the type of parity and the stop bit length are specified according to the asynchronous serial interface mode register ASIMn n 0 1 Also data is transferred with LSB first Figure 13 7 Asynchronous Serial Interface Transmit Receive Data Format Start bit 1 bit Character bits 7 bits or 8 bits Parity bit Even parity odd parity 0 parity or no...

Page 376: ...ransmission shift register outputs data to the TXD5n pin the transmit data is transferred sequential starting with the start bit The start bit parity bit and stop bits are added automatically c Transmission interrupt request When the transmission shift register becomes empty a transmission completion interrupt request INTSTn is generated The timing for generating the INTSTn interrupt differs accor...

Page 377: ... the transmission status and whether or not data can be written to the TXBn register n 0 1 Caution Transmit data should be written when the TXBF bit is 0 The transmission unit should be initialized when the TXSF bit is 0 If these actions are performed at other times the transmit data cannot be guaranteed Table 13 2 Transmission Status and Whether or Not Writing Is Enabled TXBF TXSF Transmission St...

Page 378: ...ate start bit Start data 1 transmissionNote 0 1 4 Read ASIFn register confirm that TXBF bit 0 Write data 2 1 1 Transmission in progress 5 Generate transmission completion interrupt INTSTn 0 1 6 Read ASIFn register confirm that TXBF bit 0 Write data 3 1 1 7 Generate start bit Start data 2 transmission Transmission in progress 8 Generate transmission completion interrupt INTSTn 0 1 9 Read ASIFn regi...

Page 379: ...ion in progress 5 Generate transmission completion interrupt INTSTn 0 1 6 Read ASIFn register confirm that TXSF bit 1 There is no write data 7 Generate start bit Start data n transmission Transmission in progress 8 Generate transmission completion interrupt INTSTn 0 0 9 Read ASIFn register confirm that TXSF bit 0 Clear 0 the Power bit or TXE bit of ASIMn register Initialize internal circuits Start...

Page 380: ...0 1 c Reception completion interrupt When RXE bit 1 in the ASIMn register and the reception of one frame of data is completed the stop bit is detected a reception completion interrupt INTSRn is generated and the receive data within the reception shift register is transferred to RXBn at the same time Also if an overrun error OVE occurs the receive data at that time is not transferred to the recepti...

Page 381: ... INTSERn interrupt by clearing the ISRM bit of the ASIMn register to 0 Figure 13 12 When Reception Error Interrupt Is Separated from INTSRn Interrupt ISRM Bit 0 a No error occurs during reception b An error occurs during reception Figure 13 13 When Reception Error Interrupt Is Included in INTSRn Interrupt ISRM Bit 1 a No error occurs during reception b An error occurs during reception Error Flag R...

Page 382: ... number is odd b Odd parity During transmission In contrast to even parity the parity bit is controlled so that the number of bits with the value 1 within the transmit data including the parity bit is odd The parity bit value is as follows If the number of bits with the value 1 within the transmit data is odd 0 If the number of bits with the value 1 within the transmit data is even 1 During recept...

Page 383: ...is not delivered to the internal circuit see Figure 12 15 Refer to 12 2 6 1 a Basic clock Clock regarding the basic clock Also since the circuit is configured as shown in Figure 12 14 internal processing during a receive operation is delayed by up to 2 clocks according to the external signal status Figure 13 14 Noise Filter Circuit Figure 13 15 Timing of RXD5n Signal Judged as Noise Remark n 0 1 R...

Page 384: ...eception 1 Baud rate generator configuration Figure 13 16 Baud Rate Generator BRG Configuration of UART5n n 0 1 Remark n 0 1 a Basic clock Clock When Power bit 1 in the ASIMn register the clock selected according to the TPS3 to TPS0 bits of the CKSRm register is supplied to the transmission reception unit This clock is called the basic clock Clock and its frequency is referred to as fCLK When Powe...

Page 385: ...y the TPS3 to TPS0 bits becomes the basic clock Clock of the transmission reception module Its frequency is referred to as fCLK This register can be read or written in 8 bit or 1 bit units Figure 13 17 Clock Select Registers CHKSR0 CHKSR1 7 6 5 4 3 2 1 0 Address Initial value CHKSR0 0 0 0 0 TPS3 TPS2 TPS1 TPS0 FFFF FA06H 00H CHKSR1 0 0 0 0 TPS3 TPS2 TPS1 TPS0 FFFF FA46H 00H Bit Position Bit Name F...

Page 386: ... to TPS3 to TPS0 bits of CKSRm register 2 k Value set according to MDL7 to MDL0 bits k 8 9 10 255 3 The baud rate is the output clock for the 8 bit counter divided by 2 4 x don t care 7 6 5 4 3 2 1 0 Address Initial value BRGC0 MDL7 MDL6 MDL5 MDL4 MDL3 MDL2 MDL1 MDL0 FFFF FA07H FFH BRGC1 MDL7 MDL6 MDL5 MDL4 MDL3 MDL2 MDL1 MDL0 FFFF FA47H FFH Bit Position Bit Name Function 7 to 0 MDL7 to MDL0 MDL7 ...

Page 387: ...s 1 Make sure that the baud rate error during transmission does not exceed the allowable error of the reception destination 2 Make sure that the baud rate error during reception is within the allowable baud rate range during reception which is described in chapter 13 2 6 3 Allowable baud rate range during reception on page 389 Example Basic clock frequency 10 MHz Settings of MDL7 to MDL0 bits in B...

Page 388: ...16 fPCLK 128 104 0 16 fPCLK 32 130 0 16 fPCLK 32 104 0 16 1200 fPCLK 64 130 0 16 fPCLK 64 104 0 16 fPCLK 16 130 0 16 fPCLK 16 104 0 16 2400 fPCLK 32 130 0 16 fPCLK 32 104 0 16 fPCLK 8 130 0 16 fPCLK 8 104 0 16 4800 fPCLK 16 130 0 16 fPCLK 16 104 0 16 fPCLK 4 130 0 16 fPCLK 4 104 0 16 9600 fPCLK 8 130 0 16 fPCLK 8 104 0 16 fPCLK 2 130 0 16 fPCLK 2 104 0 16 19200 fPCLK 4 130 0 16 fPCLK 4 104 0 16 fP...

Page 389: ...ure 13 19 after the start bit is detected the receive data latch timing is determined according to the counter that was set by the BRGCm register If all data up to the final data stop bit is in time for this latch timing the data can be received normally Applying this to 11 bit reception is theoretically as follows FL BR 1 BR UART5n baud rate k BRGCm register setting value FL 1 bit data length FL ...

Page 390: ...on can be obtained as follows from the expressions described above for computing the minimum and maximum baud rate values Table 13 5 Maximum and Minimum Allowable Baud Rate Error Remarks 1 The reception precision depends on the number of bits in one frame the basic clock frequency and the division ratio k The higher the basic clock frequency and the larger the division ratio k the higher the preci...

Page 391: ...n Therefore the transfer rate during continuous transmission is as follows 13 2 7 Precautions When the supply of clocks to UART5n n 0 1 is stopped for example IDLE or STOP mode operation stops with each register retaining the value it had immediately before the supply of clocks was stopped The TXD5n pin output also holds and outputs the value it had immediately before the supply of clocks was stop...

Page 392: ...st Eight clock signals can be selected 7 master clocks and 1 slave clock 3 wire type SO0n Serial transmit data output SI0n Serial transmit data input SCK0n Serial clock input output Interrupt sources 1 type Transmission reception completion interrupt INTCSI0n Transmission reception mode and reception only mode can be specified Two transmission buffers SOTBFn SOTBFLn SOTBn SOTBLn and two reception ...

Page 393: ...tual transmission reception operations are started up by access of the buffer register 5 Clocked serial interface reception buffer registers SIRB0 to SIRB2 The SIRBn register is a 16 bit buffer register that stores receive data 6 Clocked serial interface reception buffer registers Low SIRBL0 to SIRBL2 The SIRBLn register is an 8 bit buffer register that stores receive data 7 Clocked serial interfa...

Page 394: ...er Counts the serial clock output or input during transmission reception operation and checks whether 8 bit data transmission reception has been performed 16 Interrupt control circuit Controls the interrupt request timing Figure 13 21 Block Diagram of Clocked Serial Interfaces Remark n 0 to 2 Selector Transmission control SO selection SO latch Transmit data buffer register SOTBn SOTBLn Receive dat...

Page 395: ...SIE bit to 0 For the SCK0n and SO0n pin output status when the CSIE bit 0 refer to 13 3 5 Output pins on page 422 6 TRMD Specifies transmission reception mode 0 Receive only mode 1 Transmission reception mode When the TRMD bit 0 receive only transfer is performed and the SO0n pin output is fixed to low level Data reception is started by reading the SIRBn register When the TRMD bit 1 transmission r...

Page 396: ...s Initial value CSIC0 0 0 0 CKP DAP CKS2 CKS1 CKS0 FFFF FD01H 00H CSIC1 0 0 0 CKP DAP CKS2 CKS1 CKS0 FFFF FD41H 00H CSIC2 0 0 0 CKP DAP CKS2 CKS1 CKS0 FFFF FD81H 00H Bit Position Bit Name Function 4 3 CKP DAP Specifies operation mode CKP DAP Operation Mode 0 0 0 1 1 0 1 1 Remark n 0 to 2 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 DI7 SO0n SCK0n DI6 DI5 DI4 DI3 DI2 DI1 DI0 SI0n DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0...

Page 397: ...he CSIMn register 0 Bit Position Bit Name Function 2 to 0 CKS2 to CKS0 Specifies input clock CKS2 CKS1 CKS0 Input Clock Mode 0 0 0 fPCLK 4 Master mode 0 0 1 Internal BRG Channel 0 Master mode 0 1 0 Internal BRG Channel 1 Master mode 0 1 1 fPCLK 8 Master mode 1 0 0 fPCLK 16 Master mode 1 0 1 fPCLK 32 Master mode 1 1 0 fPCLK 64 Master mode 1 1 1 External clock SCK0n Slave mode Remarks 1 fPCLK intern...

Page 398: ...the SIRBn register only when the 16 bit data length has been set CCL bit of CSIMn register 1 2 When the single transfer mode has been set AUTO bit of CSIMn register 0 perform read operation only in the idle state CSOT bit of CSIMn register 0 If the SIRBn register is read during data transfer the data cannot be guaranteed 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value SIRB0 SIRB15 SIRB...

Page 399: ...he lower bytes of the SIRBn register Figure 13 25 Clocked Serial Interface Reception Buffer Registers Low SIRBL0 to SIRBL2 Cautions 1 Read the SIRBLn register only when the 8 bit data length has been set CCL bit of CSIMn register 0 2 When the single transfer mode is set AUTO bit of CSIMn register 0 perform read operation only in the idle state CSOT bit of CSIMn register 0 If the SIRBLn register is...

Page 400: ...egisters SIRBE0 to SIRBE2 Cautions 1 The receive operation is not started even if data is read from the SIRBEn register 2 The SIRBEn register can be read only if the 16 bit data length is set CCL bit of CSIMn register 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value SIRBE0 SIRBE15 SIRBE14 SIRBE13 SIRBE12 SIRBE11 SIRBE10 SIRBE9 SIRBE8 SIRBE7 SIRBE6 SIRBE5 SIRBE4 SIRBE3 SIRBE2 SIRBE1 SI...

Page 401: ...ed to read the contents of the SIRBLn register Figure 13 27 Clocked Serial Interface Read Only Reception Buffer Registers Low SIRBEL0 to SIRBEL1 Cautions 1 The receive operation is not started even if data is read from the SIRBELn register 2 The SIRBELn register can be read only if the 8 bit data length has been set CCL bit of CSIMn register 0 7 6 5 4 3 2 1 0 Address Initial value SIRBEL0 SIRBE7 S...

Page 402: ...ingle transfer mode is set AUTO bit of CSIMn register 0 perform access only in the idle state CSOT bit of CSIMn register 0 If the SOTBn register is accessed during data transfer the data cannot be guaranteed 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value SOTB0 SOTB15 SOTB14 SOTB13 SOTB12 SOTB11 SOTB10 SOTB9 SOTB8 SOTB7 SOTB6 SOTB5 SOTB4 SOTB3 SOTB2 SOTB1 SOTB0 FFFF FD04H 0000H 15 14 1...

Page 403: ...9 Clocked Serial Interface Transmission Buffer Registers Low SOTBL0 to SOTBL2 Cautions 1 Access the SOTBLn register only when the 8 bit data length has been set CCL bit of CSIMn register 0 2 When the single transfer mode is set AUTO bit of CSIMn register 0 perform access only in the idle state CSOT bit of CSIMn register 0 If the SOTBLn register is accessed during data transfer the data cannot be g...

Page 404: ...ngth has been set CCL bit of CSIMn register 1 and only in the idle state CSOT bit of CSIMn register 0 If the SOTBFn register is accessed during data transfer the data cannot be guaranteed 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value SOTBF0 SOTBF15 SOTBF14 SOTBF13 SOTBF12 SOTBF11 SOTBF10 SOTBF9 SOTBF8 SOTBF7 SOTBF6 SOTBF5 SOTBF4 SOTBF3 SOTBF2 SOTBF1 SOTBF0 FFFF FD08H 0000H SOTBF1 SOT...

Page 405: ...1 Clocked Serial Interface Initial Transmission Buffer Registers Low SOTBFL0 to SOTBFL2 Caution Access the SOTBFLn register only when the 8 bit data length has been set CCL bit of CSIM0 register 0 and only in the idle state CSOT bit of CSIMn register 0 If the SOTBFLn register is accessed during data transfer the data cannot be guaranteed 7 6 5 4 3 2 1 0 Address Initial value SOTBFL0 SOTBF7 SOTBF6 ...

Page 406: ...egister only when the 16 bit data length has been set CCL bit of CSIMn register 1 and only in the idle state CSOT bit of CSIMn register 0 If the SIOn register is accessed during data transfer the data cannot be guaranteed 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value SIO0 SIO15 SIO14 SIO13 SIO12 SIO11 SIO10 SIO9 SIO8 SIO7 SIO6 SIO5 SIO4 SIO3 SIO2 SIO1 SIO0 FFFF FD0AH 0000H SIO1 SIO15...

Page 407: ... the lower bytes of the SIOn register Figure 13 33 Serial I O Shift Registers Low SIOL0 to SIOL2 Caution Access the SIOLn register only when the 8 bit data length has been set CCL bit of CSIMn register 0 and only in the idle state CSOT bit of CSIMn register 0 If the SIOLn register is accessed during data transfer the data cannot be guaranteed 7 6 5 4 3 2 1 0 Address Initial value SIOL0 SIO7 SIO6 S...

Page 408: ...ted the value of the CSOT bit of the CSIMn register becomes 1 transmission execution status Upon transfer completion the transmission reception completion interrupt INTCSI0n is set 1 and the CSOT bit is cleared 0 The next data transfer request is then waited for Notes 1 When the 16 bit data length CCL bit of CSIMn register 1 has been set read the SIRBn register When the 8 bit data length CCL bit o...

Page 409: ...ration mode CKP bit 0 DAP bit 0 Remarks 1 n 0 to 2 2 Reg_R W Internal signal This signal indicates that receive data buffer register SIRBn SIRBLn read or transmit data buffer register SOTBn SOTBLn write was performed 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 55H AAH AAH AAH ABH 56H ADH 5AH B5H 6AH D5H SCK0n input output SO0n output SI0n input Reg_R W SOTBLn register SIOLn register SIRBLn register CSOT bit I...

Page 410: ...on mode CKP bit 0 DAP bit 1 Remarks 1 n 0 to 2 2 Reg_R W Internal signal This signal indicates that receive data buffer register SIRBn SIRBLn read or transmit data buffer register SOTBn SOTBLn write was performed 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 AAH AAH ABH 56H ADH 5AH B5H 6AH D5H SCK0n input output SO0n output SI0n input output Reg_R W SOTBLn register SIOLn register SIRBLn register CSOT bit INTCSI...

Page 411: ...nal delay control CSIT bit of CSIMn register 0 Figure 13 35 Timing Chart According to Clock Phase Selection 1 2 a When CKP bit 0 DAP bit 0 b When CKP bit 1 DAP bit 0 Remarks 1 n 0 to 2 2 Reg_R W Internal signal This signal indicates that receive data buffer register SIRBn SIRBLn read or transmit data buffer register SOTBn SOTBLn write was performed DI7 DI6 DI5 DI4 DI3 DI2 DI1 DO7 DO6 DO5 DO4 DO3 D...

Page 412: ...ternal signal This signal indicates that receive data buffer register SIRBn SIRBLn read or transmit data buffer register SOTBn SOTBLn write was performed DI7 DI6 DI5 DI4 DI3 DI2 DI1 DO7 DO6 DO5 DO4 DO3 DO2 DO1 SCK0n input output SI0n input SO0n output Reg_R W INTCSIn interrupt CSOT bit DI0 DO0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DO7 DO6 DO5 DO4 DO3 DO2 DO1 SCK0n input output SI0n input SO0n output Reg_R W...

Page 413: ...e not 111B The delay mode cannot be set when the slave mode is set bits CKS2 to CKS0 111B Figure 13 36 Timing Chart of Interrupt Request Signal Output in Delay Mode 1 2 a When CKP bit 0 DAP bit 0 Remarks 1 n 0 to 2 2 Reg_R W Internal signal This signal indicates that receive data buffer register SIRBn SIRBLn read or transmit data buffer register SOTBn SOTBLn write was performed DI7 DI6 DI5 DI4 DI3...

Page 414: ...hen CKP bit 1 DAP bit 1 Remarks 1 n 0 to 2 2 Reg_R W Internal signal This signal indicates that receive data buffer register SIRBn SIRBLn read or transmit data buffer register SOTBn SOTBLn write was performed DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 Input clock SCK0n input output SI0n input SO0n output Reg_R W INTCSIn interrupt CSOT bit Delay ...

Page 415: ... by reading the SIOn register Figure 13 37 Repeat Transfer Receive Only Timing Chart Remarks 1 n 0 to 2 2 Reg_RD Internal signal This signal indicates that the receive data buffer register SIRBn SIRBLn has been read rq_clr Internal signal Transfer request clear signal trans_rq Internal signal Transfer request signal In the case of the repeat transfer mode two transfer requests are set at the start...

Page 416: ...completion interrupt request INTCSI0n 5 When the transmission reception completion interrupt request INTCSI0n has been set to 1 write the next data to the SOTBn register reserve next transfer and read the SIRBn register to load the receive data 6 Repeat steps 4 and 5 as long as data to be sent remains 7 Wait for the INTCSI0n interrupt When the interrupt request signal is set to 1 read the SIRBn re...

Page 417: ...ion completion interrupt request INTCSI0n transfer is continued if the SOTBn register can be written within the next transfer reservation period If the SOTBn register cannot be written transfer ends and the SIRBn register does not receive the new value of the SIOn register The last receive data can be obtained by reading the SIOn register following completion of the transfer dout 1 dout 1 SCK0n in...

Page 418: ...epared with the period shown in Figure 13 39 Figure 13 39 Timing Chart of Next Transfer Reservation Period 1 2 a When data length 8 bits operation mode CKP bit 0 DAP bit 0 b When data length 16 bits operation mode CKP bit 0 DAP bit 0 SCK0n input output INTCSIn interrupt Reservation period 7 SCK0n cycles SCK0n input output INTCSIn interrupt Reservation period 15 SCK0n cycles ...

Page 419: ... Transfer Reservation Period 2 2 c When data length 8 bits operation mode CKP bit 0 DAP bit 1 d When data length 16 bits operation mode CKP bit 0 DAP bit 1 Remark n 0 to 2 SCK0n input output INTCSIn interrupt Reservation period 6 5 SCK0n cycles SCK0n input output INTCSIn interrupt Reservation period 14 5 SCK0n cycles ...

Page 420: ...urs In case of contention between transfer request clear and register access Since request cancellation has higher priority the next transfer request is ignored Therefore transfer is interrupted and normal data transfer cannot be performed Figure 13 40 Transfer Request Clear and Register Access Contention Remarks 1 n 0 to 2 2 rq_clr Internal signal Transfer request clear signal Reg_WR Internal sig...

Page 421: ... results refer to Figure 13 41 In the transmission reception mode the value of the SOTBFn register is retransmitted and illegal data is sent Figure 13 41 Interrupt Request and Register Access Contention Remarks 1 n 0 to 2 2 rq_clr Internal signal Transfer request clear signal Reg_WR Internal signal This signal indicates that the transmit data buffer register SOTBn SOTBLn has been written SCK0n inp...

Page 422: ... 1 When any of bits TRMD CCL DIR AUTO and CSICn of the CSIMn register or DAP bit of the CSICn register is overwritten the SO0n pin output changes 2 SOTBm Bit m of SOTBn register m 0 7 15 3 SOTBFm Bit m of SOTBFn register m 0 7 15 4 n 0 to 2 CKP CKS2 CKS1 CKS0 SCK0n Pin Output 0 Don t care Don t care Don t care Fixed to high level 1 1 1 1 Fixed to high level Other than above Fixed to low level TRMD...

Page 423: ...ters CSIC0 and CSIC1 refer to 12 3 3 2 Clocked serial interface clock selection registers 0 1 CSIC0 CSIC1 If the dedicated baud rate generator output is specified BRG0 or BRG1 respectively is selected as the clock source Since the same serial clock can be shared for transmission and reception baud rate is the same for the transmission reception Figure 13 42 Baud Rate Generators 0 1 BRG0 BRG1 Block...

Page 424: ... 8 bit or 1 bit units n 0 to 2 Figure 13 43 Prescaler Mode Registers 0 1 PRSM0 PRSM1 Cautions 1 Do not change the value of the BGCS1 BGCS0 bits during transmission reception operation 2 Set the PRSMn register prior to setting the CE bit to 1 7 6 5 4 3 2 1 0 Address Initial value PRSM0 0 0 0 CE 0 0 BGCS1 BGCS0 FFFF FDC0H 00H 7 6 5 4 3 2 1 0 Address Initial value PRSM1 0 0 0 CE 0 0 BGCS1 BGCS0 FFFF ...

Page 425: ...ontents of the PRSCMn register are overwritten when the value of the CE bit is 1 the cycle of the baud rate signal is not guaranteed d Baud rate signal cycle The baud rate signal cycle is calculated as follows When setting value of PRSCMn register is 00H Cycle of signal selected with bits BGCS1 BGCS0 of PRSMn register 256 2 In cases other than above Cycle of signal selected with bits BGCS1 BGCS2 o...

Page 426: ...l below the minimum value of 200 ns of the SCK0n cycle tCYSK1 prescribed in the electrical specifications BGCS1 BGCS0 PRSCM Register Value Clock Hz 0 0 1 4000000 0 0 2 2000000 0 0 4 1000000 0 0 8 500000 0 0 16 250000 0 0 40 100000 0 0 80 50000 0 0 160 25000 0 1 200 10000 1 0 200 5000 BGCS1 BGCS0 PRSCM Register Value Clock Hz 0 0 2 2500000 0 0 5 1000000 0 0 10 500000 0 0 20 250000 0 0 50 100000 0 0...

Page 427: ... messages BasicCAN channels 4 masks per CAN module each mask can be assigned to each message Buffered reception FIFO Message buffers can be redefined in normal operation mode FCAN interface and CPU share common RAM area Interrupt on receive transmit and error condition Time stamp and global time system function Two power save modes SLEEP mode wake up at CAN bus activity STOP mode no wake up at CAN...

Page 428: ...vide no memory for the necessary data buffers rather all CAN mod ules have access to the common CAN memory area via a memory access controller MAC The MAC allows integration of machines other than CAN modules e g CAN bridge The CPU also accesses to the common CAN memory via the MAC The MAC offers data scan capability beside con trolling the arbitration of CAN modules or CPU accesses to the CAN mem...

Page 429: ... the BPC register 3 The memory area of the FCAN system is divided into certain functional sections The start and end addresses of those sections are given as an address offset value Caution Before accessing any register or buffer of the FCAN system the base address PP_BASE must be fixed by the BPC register CAN message buffer section with 32 message buffer 32 bytes message buffer 0000H 03FFH CAN in...

Page 430: ... write accesses by CPU while the FCAN system is active 1 CAN message buffer section The message buffer section consists of 32 message buffers Each message buffer allocates 32 bytes The message buffers are not statically distributed and linked to the CAN modules rather the user must determine the link of a message buffer to a CAN module by software As a consequence the message buffers can be alloca...

Page 431: ... 801H M_EVTm1 Message event register 1Note 3 R W m 20H 802H M_EVTm2 Message event register 2Note 3 m 20H 803H M_EVTm3 Message event register 3Note 3 484 R W m 20H 804H M_DLCm Message data length code register 480 R W m 20H 805H M_CTRLm Message control register 481 R W m 20H 806H M_TIMEm Message time stamp register 483 R W m 20H 808H M_DATAm0 Message data byte 0 478 R W m 20H 809H M_DATAm1 Message ...

Page 432: ...effective address PP_BASE address offset Address OffsetNote Symbol Name Ref Page Access Type Comment R W 1 bit 8 bits 16 bits 1004H CCINTP CAN interrupt pending register 467 R 1020H CGINTP CAN global interrupt pending register 468 R W bit set function only 1022H C1INTP CAN1 interrupt pending register 470 R W bit clear function only 1024H C2INTP CAN2 interrupt pending register 470 R W bit clear fun...

Page 433: ... Name Ref Page Access Type Comment R W 1 bit 8 bits 16 bits 1000H CSTOP CAN stop register 454 R W 1010H CGST CAN global status register 457 R W bit set clear function 1012H CGIE CAN global interrupt enable register 460 R W bit set clear function 1014H CGCS CAN main clock select register 455 R W only if GOM bit 0 1016H CGTEN CAN timer event enable register 462 R W 1018H CGTSC CAN global time system...

Page 434: ...C1MASKL0 CAN1 mask 0 register L 485 R W lower half word 1042H C1MASKH0 CAN1 mask 0 register H R W upper half word 1044H C1MASKL1 CAN1 mask 1 register L R W lower half word 1046H C1MASKH1 CAN1 mask 1 register H R W upper half word 1048H C1MASKL2 CAN1 mask 2 register L R W lower half word 104AH C1MASKH2 CAN1 mask 2 register H R W upper half word 104CH C1MASKL3 CAN1 mask 3 register L R W lower half w...

Page 435: ...r half word 108EH C2MASKH3 CAN2 mask 3 register H R W upper half word 1090H C2CTRL CAN2 control register 487 R W bit set clear function 1092H C2DEF CAN2 definition register 492 R W bit set clear function 1094H C2LAST CAN2 information register 496 R read only 1096H C2ERC CAN2 error counter register 497 R read only 1098H C2IE CAN2 interrupt enable register 498 R W bit set clear function 109AH C2BA C...

Page 436: ... W upper half word 10D0H C3CTRL CAN3 control register 487 R W bit set clear function 10D2H C3DEF CAN3 definition register 492 R W bit set clear function 10D4H C3LAST CAN3 information register 496 R read only 10D6H C3ERC CAN3 error counter register 497 R read only 10D8H C3IE CAN3 interrupt enable register 498 R W bit set clear function 10DAH C3BA CAN3 bus activity register 501 R W bit set clear fun...

Page 437: ... W upper half word 1110H C4CTRL CAN4 control register 487 R W bit set clear function 1112H C4DEF CAN4 definition register 492 R W bit set clear function 1114H C4LAST CAN4 information register 496 R read only 1116H C4ERC CAN4 error counter register 497 R read only 1118H C4IE CAN4 interrupt enable register 498 R W bit set clear function 111AH C4BA CAN4 bus activity register 501 R W bit set clear fun...

Page 438: ...system is integrated in the FCAN system That functional block is supplied by the global time system clock fGTS which is derived from fMEM The time system prescaler scales fGTS and is controlled by the CGCS register The time base of the global time system is realised by the 16 bit free running counter the CAN global time system counter CGTSC Time stamp information is captured from the CGTSC counter...

Page 439: ...nalyse which particular interrupt event caused the interrupt request by scanning the interrupt pending flags of a bundled interrupt signal group After the particular interrupt has been identified the corresponding interrupt pending flag must be reset by soft ware at least before leaving the interrupt service routine Figure 14 4 FCAN Interrupt Bundling of V850E CA2 Note CAN module 3 and CAN module ...

Page 440: ...ing register C3INTP CAN module 3 interrupt pending register C4INTP CAN module 4 interrupt pending register Additionally the entire interrupt pending flags are summarized in one register the CAN interrupt pend ing register CCINTP However the CCINTP register is a read only register and cannot be used for clearing the interrupt pending flags For details on the interrupt pending registers refer to the...

Page 441: ...essage is detected as valid i e if no error was detected until the last but one bit of the end of frame EOF was received The selection of the two trigger options is controlled by the TMR bit in the CxCTRL register x 1 to 2 for the derivative µPD703128 A x 1 to 4 for the derivatives µPD703129 A and µPD703129 A1 The capture value itself is stored in the M_TIMEm register m 00 to 31 of the message buf...

Page 442: ...SOF Remark m 00 to 31 M_DLC m Bus Data 1 Bus Data 2 Bus Data 3 Bus Data 4 Bus Data 5 Bus Data 6 Bus Data 7 Bus Data 8 1 M_DATAm 0 2 lower 8 bit of CGTSC Note upper 8 bit of CGTSC Note 3 M_DATAm 0 lower 8 bit of CGTSC Note upper 8 bit of CGTSC Note 4 M_DATAm 0 M_DATAm 1 lower 8 bit of CGTSC Note upper 8 bit of CGTSC Note 5 M_DATAm 0 M_DATAm 1 M_DATAm 2 lower 8 bit of CGTSC Note upper 8 bit of CGTSC...

Page 443: ...s against lower prior messages sent by other nodes at the same time due to arbitration mechanism of CAN protocol and against messages waiting to be transmitted in the same node i e inner pri ority inversion The FCAN system scans the message buffer section at the beginning of each message transmit to analyse that no other message with a higher priority is waiting to be transmitted on the same CAN b...

Page 444: ... user must allocate the 5 higher prior transmit messages to message buffers with a lower address There is no sorting needed among the 5 higher prior message buffer Message Buffer Address OffsetNote1 Message Buffer Number Message Buffer Link Message Buffer TypeNote2 Waiting for Transmission Identifier 400H 31 300H 24 2E0H 23 2C0H 22 CAN 1 TRX 3 123H 2A0H 21 280H 20 260H 19 240H 18 220H 17 200H 16 1...

Page 445: ...higher prior transmit messages assigned to message buffers with lower address values Message Buffer Address Offset Note 1 Message Buffer Number Message Buffer Link Message Buffer TypeNote 2 Identifier 400H 31 300H 24 2E0H 23 2C0H 22 CAN1 TRX 005H 2A0H 21 280H 20 260H 19 CAN1 TRX 006H 240H 18 220H 17 200H 16 1E0H 15 CAN1 TRX 007H 1C0H 14 CAN1 TRX 001H Note 3 1A0H 13 180H 12 160H 11 140H 10 CAN1 TRX...

Page 446: ...r stored in the receive buffer linked to mask 2 but always into the non masked receive buffer Furthermore there is a fixed inner storage rule in case several buffers of the same priority class are linked to a CAN module For the inner priority class storage rule the data new flag DN in the M_STATm register is the first storage criteria m 00 to 31 Whenever the DN flag cannot provide an unambiguous c...

Page 447: ...ious message storage As soon the CPU reads one of the message buffer with DN flag set and then clears the DN flag the storing in ascending message buffer number order is interrupted Due to the storage priority for receive messages it is possible to design multiple buffer arrays for a CAN message while not all message buffers assigned to the same identifier contain new data DN flag set the FCAN sys...

Page 448: ...d by message sorting In the FCAN system each CAN module provides 4 different masks For a receive message buffer assigned to a CAN module one of the 4 masks can be selected when the BasicCAN concept is used When using a mask a certain identifier value must be written into the identifier register M_IDm equals 32 bit value build by M_IDHm and M_IDLm of the receive message buffer at initialisation The...

Page 449: ...when setting the transmit request bit TRQ of the M_STATm register for a message buffer defined as receive message buffer m 00 to 31 Same as for generating a data frame from a transmit message buffer the ready bit RDY of M_STATm register must be set 1 Remote frames can also be generated by means of a transmit message buffer by setting the RTR bit of the M_CTRLm register and using the same transmiss...

Page 450: ...automatic remote frame handling activities from the FCAN system The application software must handle the remote frame in the expected way 2 RMDE0 RMDE1 bits as well as ATS bit of M_CTRLm register are set to 0 M_DLCm message data length code register M_CTRLm message control register M_TIMEm message time stamp register 16 bit M_DATAm0 message data byte 0 M_DATAm1 message data byte 1 M_DATAm2 message...

Page 451: ...g the DN flag in the transmit message buffer No reaction at all Table 14 15 shows the detailed handling reaction upon the reception of a remote frame for a transmit message buffer depending on the settings of RMDE0 RMDE1 and RTR flags Table 14 15 Remote Frame Handling upon Reception into a Transmit Message Buffer Note Auto answer upon remote frame is suppressed because the transmit message buffer ...

Page 452: ... A and µPD703129 A1 Registers like above where bit access and direct write operations are prohibited are organized in such a way that all bits allowed for manipulation are located in the lower byte bits 7 to 0 while in the upper byte bits 15 to 8 either no or read only information is located The registers can be read in the usual way to get all 16 data bits in their actual setting ref to appropri ...

Page 453: ...ess for better vis ibility of the program code it is recommended to perform only 16 bit write accesses 2 n 0 to 7 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SE_7 SE_6 SE_5 SE_4 SE_3 SE_2 SE_1 SE_0 CL_7 CL_6 CL_5 CL_4 CL_3 CL_2 CL_1 CL_0 Bit Name Function SE_n Sets the register bit n 0 No change of register bit n 1 Register bit n is set 1 CL_n Clears the register bit n 0 No change of register bit n 1 Re...

Page 454: ...y for the complete FCAN system The CSTP flag can be used to reduce the power consumption when the FCAN system is set to SLEEP mode and STOP mode to a minimum 0 FCAN system is supplied with clock fMEM 1 Clock supply of the FCAN system is stopped Remark When switching off the clock supply of the FCAN system during SLEEP mode wake up by CAN bus activity is possible But instead of CxINT4 interrupt i e...

Page 455: ...SC0 0 MCS MCP3 MCP2 MCP1 MCP0 1014H 7F05H Bit Position Bit Name Function 15 to 8 CGTS7 to CGTS0 Specifies the 8 bit prescaler compare value for the global time system clock fGTS ref to Fig 9 11 Remark The global time system clock is the source clock for the 16 bit timer used for the time stamp functionality This clock is common for all CAN modules 7 6 GTCS1 GTCS0 Selects the global time system bas...

Page 456: ...e System Clock Bit Position Bit Name Function 3 to 0 MCP3 to MCP0 Specifies the prescaler for the memory access clock fMEM ref to Fig 9 10 MCP3 MCP2 MCP1 MCP0 Prescaler m 1 Memory Clock fMEM fMEM1 m 1 0 0 0 0 1 fMEM fMEM1 0 0 0 1 2 fMEM fMEM1 2 0 0 1 0 3 fMEM fMEM1 3 1 1 1 1 16 fMEM fMEM1 16 Selector f MCS Prescaler MCP0 to MCP3 Clock for Memory Access Controller PCLK fMEM MEM 8 bit counter 8 bit ...

Page 457: ...ead 1 2 Bit Position Bit Name Function 7 MERR Indicates the error status of the memory access controller MAC 0 No error occurrence 1 At least one error occurred since the flag was cleared last A MAC error occurs under the following conditions An attempt to clear the GOM flag was performed although not all CAN modules are set to initialization state Access to an illegal address or access is prohibi...

Page 458: ...ffers Note 1 1 Operation of all CAN modules are enabled Temporary buffers can be read only Note 1 Caution To ensure that resetting the CAN modules do not cause any unex pected behaviour on the CAN bus the GOM flag can only be cleared if all CAN modules are set into initialisation state exception forced shut down see EFSD flag If the software clears the flag while at least one CAN module is still n...

Page 459: ... EVM bit 8 0 ST_GOM CL_GOM Sets clears the GOM bit 7 CL_MERR Clears the MERR bit 0 No change of MERR bit 1 MERR bit is cleared 0 ST_EFSD CL_EFSD Status of EFSD Bit 0 1 EFSD bit is cleared 0 1 0 EFSD bit is set 1 Others No change in EFSD bit value ST_TSM CL_TSM Status of TSM Bit 0 1 TSM bit is cleared 0 1 0 TSM bit is set 1 Others No change in TSM bit value ST_EVM CL_EVM Status of EVM Bit 0 1 EVM b...

Page 460: ... Enables interrupt by CAN bridge 0 Interrupt disabled 1 Interrupt enabled Remark Due to the reason that no CAN bridge is implemented in the V850E CA2 device this bit must not be set at any time 2 G_IE2 Enables illegal address interrupt 0 Interrupt disabled 1 Interrupt enabled Remarks 1 Interrupt signals any access to CAN module register while GOM bit of the CGST register is reset 0 2 Interrupt sig...

Page 461: ...E2 Sets clears the G_IE2 bit 9 1 ST_G_IE1 CL_G_IE1 Sets clears the G_IE1 bit ST_G_IE7 CL_G_IE7 Status of G_IE7 Bit 0 1 G_IE7 bit is cleared 0 1 0 G_IE7 bit is set 1 Others No change in G_IE7 bit value ST_G_IE2 CL_G_IE2 Status of G_IE2 Bit 0 1 G_IE2 bit is cleared 0 1 0 G_IE2 bit is set 1 Others No change in G_IE2 bit value ST_G_IE1 CL_G_IE1 Status of G_IE1 Bit 0 1 G_IE1 bit is cleared 0 1 0 G_IE1 ...

Page 462: ...llows timer event 0 fGTS 210 timer event 1 fGTS 212 timer event 2 fGTS 214 timer event 3 fGTS 216 Figure 14 15 CAN Global Time System Counter and event generation 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address OffsetNote1 Initial value CGTEN 0 0 0 0 0 0 0 0 0 0 0 0 CTEN3 CTEN2 CTEN1 CTEN0 1016H 0000H Read Bit Position Bit Name Function 3 CTEN3 Enables CAN timer event 3 0 Timer event disabled 1 Time...

Page 463: ...ter can be read and writtenNote 1 in 16 bit units only Figure 14 16 CAN Global Time System Counter CGTSC Notes 1 When writing is performed to CGTSC register the counter is cleared to 0 2 The register address is calculated according to the following formula effective address PP_BASE address offset Remark The CGTSC register can be read at any time 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Offset...

Page 464: ...ag RDY of the M_STATm registers 0 Do not check status of TRQ flag and RDY flag 1 TRQ flag and RDY flag must be set 12 CMSK Search criteria for the mask link bits MT2 to MT0 of the M_CONFm registers 0 Do not check mask link bits 1 Check only message buffers not linked with a mask 11 CDN Search criteria for data new flag DN of the M_STATm registers 0 Do not check status of the DN flag 1 DN flag must...

Page 465: ... function 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address OffsetNote1 Initial value CGMSR 0 0 0 0 0 0 MM AM 0Note3 0Note3 MFND5 MFND4 MFND3 MFND2 MFND1 MFND0 101AH 0000H Bit Position Bit Name Function 9 8 MM AM Indicates the match result of the preceding message search 5 to 0 MFND5 to MFND0 Indicates the number of the message buffer which was found by the message search 0 to 31 Note 2 Remarks 1 Any ...

Page 466: ...ansceiver bus harness etc 3 x 1 to 4 Note CAN module 3 and CAN module 4 are available in the derivatives µPD703129 A and µPD703129 A1 only Caution The internal test bus must only be used when none of the CAN modules are con nected to a CAN bus 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address OffsetNote Initial value CTBR 0 0 0 0 0 0 0 0 0 0 0 0 0 RXEN TXPRE TEN 101CH 0000H Bit Position Bit Name Funct...

Page 467: ...the dedicated interrupt pending registers CGINTP C1INTP C2INTP and C3INTP 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address OffsetNote 1 Initial value CCINTPH 0 0 0 0 0 0 0 0 0 0 0 0 0 CAN4ERR CAN4REC CAN4TRX 1006H 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address OffsetNote 1 Initial value CCINTPL INTACT INTMAC 0 0 0 0 0 CAN3ERR CAN3REC CAN3TRX CAN2ERR CAN2REC CAN2TRX CAN1ERR CAN1REC CAN1TRX 1004H ...

Page 468: ...0 0 0 0 0 CL_ GINT7 0 0 0 CL_ GINT3 CL_ GINT2 CL_ GINT1 0 1020H Read Bit Position Bit Name Function 7 GINT7 Indicates an interrupt of the CAN bridge ELISA GINT7 bit of CGINTP register 0 No Interrupt pending 1 Interrupt pending 3 GINT3 Indicates a wake up interrupt from CAN sleep mode while clock supply to the FCAN system was stopped ref to CSTOP register 0 No Interrupt pending 1 Interrupt pending ...

Page 469: ...eared by software in the interrupt service routine Caution In case the interrupt pending bit is not cleared by software in the interrupt service routine no subsequent interrupt is generated anymore Write Bit Position Bit Name Function 7 CL_GINT7 Clears the interrupt pending bit GINT7 0 No change of GINT7 bit 1 GINT7 bit is cleared 0 3 CL_GINT3 Clears the interrupt pending bit GINT3 0 No change of ...

Page 470: ...0 C2INT6 C2INT5 C2INT4 C2INT3 C2INT2 C2INT1 C2INT0 1024H 0000H C3INTP 0 0 0 0 0 0 0 0 0 C3INT6 C3INT5 C3INT4 C3INT3 C3INT2 C3INT1 C3INT0 1026H 0000H C4INTP 0 0 0 0 0 0 0 0 0 C3INT6 C3INT5 C3INT4 C3INT3 C3INT2 C3INT1 C3INT0 1028H 0000H Write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 C1INTP 0 0 0 0 0 0 0 0 0 CL_ C1INT6 CL_ C1INT5 CL_ C1INT4 CL_ C1INT3 CL_ C1INT2 CL_ C1INT1 CL_ C1INT0 1022H C2INTP 0 0 0 ...

Page 471: ...ing 1 CxINT1 Indicates a reception completion interrupt of CAN module x 0 No Interrupt pending 1 Interrupt pending 0 CxINT0 Indicates a transmission completion interrupt of CAN module x 0 No Interrupt pending 1 Interrupt pending Write Bit Position Bit Name Note 1 2 Function 6 CL_CxINT6 Clears the interrupt pending bit CxINT6 0 No change of CxINT6 bit 1 CxINT6 bit is cleared 0 5 CL_CxINT5 Clears th...

Page 472: ... D2 3 When received message in standard format mode IDE 0 has less than 18 data bits the values of the not received bits are undefined Remark m 00 to 31 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address OffsetNote 1 Initial value M_ID Hm IDE 0 0 ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21 ID20 ID19 ID18 ID17 ID16 812H m 20H undef 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 M_IDL m ID15 ID14 ID13 ID12 ID11 ID10 ...

Page 473: ... 31 M_CONF00 to M_CONF31 1 2 7 6 5 4 3 2 1 0 Address OffsetNote 1 Initial value M_CONFm 0 0 MT2 MT1 MT0 MA2 MA1 MA0 814H m 20H undef Bit Position Bit Name Function 5 to 3 MT2 to MT0 Specifies the message type and mask link MT2 MT1 MT0 Message type and mask link 0 0 0 Transmit message 0 0 1 Receive message no mask linked 0 1 0 Receive message mask 0 linked Note 2 0 1 1 Receive message mask 1 linked...

Page 474: ...ell Even the type of the identifier standard or extended and the type of the frame remote or data frame are not respected In normal operation mode the message buffer is not han dled 5 If the message buffer is not assigned to a CAN module it can be used as temporary buffer of the application or by the CAN bridge ELISA 6 CAN module 3 and CAN module 4 are available in the derivatives µPD703129 A and ...

Page 475: ...least one new message was received Remarks 1 If the DN flag is set for a transmit message buffer it indicates a remote frame reception In case auto answering RMDE0 bit of the M_CTRLm register is active the DN flag is cleared automatically after the answer ing data frame is sent 2 If the OVM bit of CxCTRL register is cleared 0 a message buffer assigned to the CAN module might be overwritten by new ...

Page 476: ...6 Table 14 16 CAN Message Processing by TRQ and RDY Bits Message Type TRQ RDY Message Processing Any 0 Message buffer is disabled for any processing by the assigned CAN module Receive message 0 1 Message buffer is ready for reception 1 1 Request for sending a remote frame Transmit message 0 1 No processing of the transmit message 1 1 Request for message transmission ...

Page 477: ...te Initial value SC_STAT m 0 0 0 0 ST_ ERQ ST_ DN ST_ TRQ ST_ RDY 0 0 0 0 CL_ ERQ CL_ DN CL_ TRQ CL_ RDY 816H m 20H Bit Position Bit Name Function 11 3 ST_ERQ CL_ERQ Sets clears the ERQ bit of the M_STATm register 10 2 ST_DN CL_DN Sets clears the DN bit of the M_STATm register 9 1 ST_TRQ CL_TRQ Sets clears the TRQ bit of the M_STATm register 8 0 ST_RDY CL_RDY Sets clears the RDY bit of the M_STATm...

Page 478: ...to 31 1 2 7 6 5 4 3 2 1 0 Address OffsetNote Initial value M_DATA m0 D0_7 D0_6 D0_5 D0_4 D0_3 D0_2 D0_1 D0_0 808H m 20H undef M_DATA m1 D1_7 D1_6 D1_5 D1_4 D1_3 D1_2 D1_1 D1_0 809H m 20H undef M_DATA m2 D2_7 D2_6 D2_5 D2_4 D2_3 D2_2 D2_1 D2_0 80AH m 20H undef M_DATA m3 D3_7 D3_6 D3_5 D3_4 D3_3 D3_2 D3_1 D3_0 80BH m 20H undef M_DATA m4 D4_7 D4_6 D4_5 D4_4 D4_3 D4_2 D4_1 D4_0 80CH m 20H undef M_DATA...

Page 479: ...time stamp value is sent x 1 to 2 for the derivative µPD703128 A x 1 to 4 for the derivatives µPD703129 A and µPD703129 A1 refer to chapter 14 2 5 Time stamp on page 441 3 When a new message is received all data bytes are updated even if the data length code DLC in the M_DLCm register is less than 8 The values of the data bytes that have not been received may be change undefined Bit Position Bit N...

Page 480: ...LCm register 3 If a DLC is specified to a value greater 8 for a transmit message 8 byte transfer is per formed regardless of the DLC value Remark m 00 to 31 Cautions 1 If a remote frame is received on a transmit buffer the DLC value leaves unchanged 2 If a remote frame is received on a receive buffer the DLC value is updated by the DLC value of the remote frame 7 6 5 4 3 2 1 0 Address OffsetNote 1...

Page 481: ...es and indicates how the DN flag is updated if a remote frame is received on that message buffer For details refer to chapter 14 2 8 Remote frame han dling on page 449 6 RMED0 Specifies the remote frame handling mode 0 0 Auto answering of remote frame is not active 1 Auto answering of remote frame is active Remark The remote frame handling mode 0 is only valid for transmit messages and indicates h...

Page 482: ...is CAN module might be overwritten by new messages although the DN flag is already set Checking the MOVR bit additionally indicates whether the message buffer has been overwritten 2 R1 Reserved bit value of CAN bus bit r0 for receive message buffer 1 R0 Reserved bit value of CAN bus bit r1 for receive message buffer 0 RTR Specifies remote or data frame type of the message buffer 0 Message received...

Page 483: ... calculated according to the following formula effective address PP_BASE address offset Remarks 1 m 00 to 31 2 x 1 to 4 for the derivatives µPD703129 A and µPD703129 A1 3 x 1 to 2 for the derivative µPD703128 A 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address OffsetNote Initial value M_TIM Em TS15 TS14 TS13 TS12 TS11 TS19 TS9 TS8 TS7 TS6 TS5 TS4 TS3 TS2 TS1 TS0 806H m 20H undef Bit Position Bit Name ...

Page 484: ...all Message Event Bytes with the value 0x00 at the first initialization and let that initialization unchanged always 7 6 5 4 3 2 1 0 Address OffsetNote Initial value M_EVTm0 PTR07 PTR06 PTR05 PTR04 PTR03 PTR02 PTR01 PTR00 800H m 20H undef M_EVTm1 PTR17 PTR16 PTR15 PTR14 PTR13 PTR12 PTR11 PTR10 801H m 20H undef M_EVTm2 PTR27 PTR26 PTR25 PTR24 PTR23 PTR22 PTR21 PTR20 802H m 20H undef M_EVTm3 PTR37 P...

Page 485: ...KHn CMIDE Sets the CAN module mask option for the identifier type of the receive message 0 Check identifier type of a received message 1 Do not check identifier type Remark When CMIDE is cleared 0 the specified identifier type standard or extended of the message buffer linked to this CAN mask register must match the identifier type of the received message in order to accept it for that message buf...

Page 486: ...erivative µPD703128 A 3 The register address is calculated according to the following formula effective address PP_BASE address offset SymbolNote1 2 Address OffsetNote 3 x 1 x 2 x 3Note 1 2 x 4Note 1 2 CxMASKL0 1040H 1080H 10C0H 1100H CxMASKH0 1042H 1082H 10C2H 1102H CxMASKL1 1044H 1084H 10C4H 1104H CxMASKH1 1046H 1086H 10C6H 1106H CxMASKL2 1048H 1088H 10C8H 1108H CxMASKH2 104AH 108AH 10CAH 110AH ...

Page 487: ...T 1050H 0101H C2CTRL TECS1 TECS0 RECS1 RECS0 BOFF TSTAT RSTAT ISTAT TPE DLEVR DLEVT OVM TMR STOP SLEEP INIT 1090H 0101H C3CTRL TECS1 TECS0 RECS1 RECS0 BOFF TSTAT RSTAT ISTAT TPE DLEVR DLEVT OVM TMR STOP SLEEP INIT 10D0H 0101H C4CTRL TECS1 TECS0 RECS1 RECS0 BOFF TSTAT RSTAT ISTAT TPE DLEVR DLEVT OVM TMR STOP SLEEP INIT 1110H 0101H Write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 C1CTRL ST_ TPE ST_ DLEVR...

Page 488: ...t is recessive logical high 3 Data manipulation of the CxSYNC and CxBRP registers is only possi ble during INIT state 4 In INIT state the transmission and reception error counters are cleared and any error status is reset 7 TPE Indicates the transmit pin status 0 CAN transmit pin is disabled tri state 1 CAN transmit pin is enabled 6 DLEVR Specifies the dominant level of the CAN receive input pin 0...

Page 489: ...vities stopped and set in suspend mode and wake up of the CAN module is only possible by CPU CPU clears STOP bit 1 SLEEP Selects the CAN sleep mode 0 Normal operation mode 1 CAN module sleep mode selected Remarks 1 Entering the CAN sleep mode from normal operating mode is just pos sible when the CAN bus is idle 2 In CAN sleep mode the CAN module does not process any transmit request submitted by t...

Page 490: ...of TPE bit 0 1 TPE bit is cleared 0 1 0 TPE bit is set 1 Others No change in TPE bit value ST_DLEVR CL_DLEVR Status of DLEVR bit 0 1 DLEVR bit is cleared 0 1 0 DLEVR bit is set 1 Others No change in DLEVR bit value ST_DLEVT CL_DLEVT Status of DLEVT bit 0 1 DLEVT bit is cleared 0 1 0 DLEVT bit is set 1 Others No change in DLEVT bit value ST_OVM CL_OVM Status of OVM bit 0 1 OVM bit is cleared 0 1 0 ...

Page 491: ...a effective address PP_BASE address offset Write 2 2 Bit Position Bit Name Function 9 1 ST_SLEEP CL_SLEEP Sets clears the SLEEP bit 8 0 ST_INIT CL_INIT Sets clears the INIT bit ST_SLEEP CL_SLEEP Status of SLEEP bit 0 1 SLEEP bit is cleared 0 1 0 SLEEP bit is set 1 Others No change in SLEEP bit value ST_INIT CL_INIT Status of INIT bit 0 1 INIT bit is cleared 0 1 0 INIT bit is set 1 Others No change...

Page 492: ...1 10 9 8 7 6 5 4 3 2 1 0 Address OffsetNote Initial value C1DEF 0 0 0 0 0 0 0 0 DGM MOM SSHT PBB BERR VALID WAKE OVR 1052H 0000H C2DEF 0 0 0 0 0 0 0 0 DGM MOM SSHT PBB BERR VALID WAKE OVR 1092H 0000H C3DEF 0 0 0 0 0 0 0 0 DGM MOM SSHT PBB BERR VALID WAKE OVR 10D2H 0000H C4DEF 0 0 0 0 0 0 0 0 DGM MOM SSHT PBB BERR VALID WAKE OVR 1112H 0000H Write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 C1DEF ST_ DGM ...

Page 493: ... be used for baud rate detection and diagnos tic purposes Caution When the diagnostic mode MOM 1 is defined for a CAN module the CxBRP register is only accessible in the initialisation state ISTAT 1 While ISTAT is cleared 0 write access to the CxBRP is prohib ited and reading the address of the CxBRP register returns the status of the CxDINF register 5 SSHT Defines the single shot mode for a CAN m...

Page 494: ...eared last Remark For single shot mode SSHT bit 1 this flag indicates a loss of the arbitra tion 2 VALID Indicates valid protocol activity 0 No valid message was detected by the CAN protocol layer 1 At least one valid message was received on the CAN bus since the flag has been cleared last 1 WAKE Indicates the wake up condition from CAN sleep mode 0 No wake up or sleep mode has been terminated by ...

Page 495: ...ID bit 0 No change of VALID bit 1 VALID bit is cleared 0 1 CL_WAKE Clears the WAKE bit 0 No change of WAKE bit 1 WAKE bit is cleared 0 0 CL_OVR Clears the OVR bit 0 No change of OVR bit 1 OVR bit is cleared 0 ST_DGM CL_DGM Status of DGM bit 0 1 DGM bit is cleared 0 1 0 DGM bit is set 1 Others No change in DGM bit value ST_MOM CL_MOM Status of MOM bit 0 1 MOM bit is cleared 0 1 0 MOM bit is set 1 O...

Page 496: ...RR3 LERR2 LERR1 LERR0 LREC7 LREC6 LREC5 LREC4 LREC3 LREC2 LREC1 LREC0 1094H 00FFH C3LAST 0 0 0 0 LERR3 LERR2 LERR1 LERR0 LREC7 LREC6 LREC5 LREC4 LREC3 LREC2 LREC1 LREC0 10D4H 00FFH C4LAST 0 0 0 0 LERR3 LERR2 LERR1 LERR0 LREC7 LREC6 LREC5 LREC4 LREC3 LREC2 LREC1 LREC0 1114H 00FFH Bit Position Bit Name Function 11 to 8 LERR3 to LERR0 Holds the code of the last CAN protocol error Remark The LERR3 to ...

Page 497: ...offset 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address OffsetNote Initial value C1ERC REC7 REC6 REC5 REC4 REC3 REC2 REC1 REC0 TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 TEC0 1056H 0000H C2ERC REC7 REC6 REC5 REC4 REC3 REC2 REC1 REC0 TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 TEC0 1096H 0000H C3ERC REC7 REC6 REC5 REC4 REC3 REC2 REC1 REC0 TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 TEC0 10D6H 0000H C4ERC REC7 REC6 REC5 REC4 RE...

Page 498: ...0 0 0 E_INT6 E_INT5 E_INT4 E_INT3 E_INT2 E_INT1 E_INT0 1058H 0000H C2IE 0 0 0 0 0 0 0 0 0 E_INT6 E_INT5 E_INT4 E_INT3 E_INT2 E_INT1 E_INT0 1098H 0000H C3IE 0 0 0 0 0 0 0 0 0 E_INT6 E_INT5 E_INT4 E_INT3 E_INT2 E_INT1 E_INT0 10D8H 0000H C4IE 0 0 0 0 0 0 0 0 0 E_INT6 E_INT5 E_INT4 E_INT3 E_INT2 E_INT1 E_INT0 1118H 0000H Write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 C1IE 0 ST_ E_INT6 ST_ E_INT5 ST_ E_IN...

Page 499: ...1 Interrupt enabled 4 E_INT4 Enables wake up from CAN sleep mode interrupt INT4 0 Interrupt disabled 1 Interrupt enabled 3 E_INT3 Enables interrupt for error passive on reception INT3 0 Interrupt disabled 1 Interrupt enabled 2 E_INT2 Enables interrupt for error passive or bus off on transmission INT2 0 Interrupt disabled 1 Interrupt enabled 1 E_INT1 Enables reception successful completion interrup...

Page 500: ...bit is set 1 Others No change in E_INT6 bit value ST_E_INT5 CL_E_INT5 Status of E_INT5 bit 0 1 E_INT5 bit is cleared 0 1 0 E_INT5 bit is set 1 Others No change in E_INT5 bit value ST_E_INT4 CL_E_INT4 Status of E_INT4 bit 0 1 E_INT4 bit is cleared 0 1 0 E_INT4 bit is set 1 Others No change in E_INT4 bit value ST_E_INT3 CL_E_INT3 Status of E_INT3 bit 0 1 E_INT3 bit is cleared 0 1 0 E_INT3 bit is set...

Page 501: ...AH 00FFH C3BA 0 0 0 CACT4 CACT3 CACT2 CACT1 CACT0 TMNO7 TMNO6 TMNO5 TMNO4 TMNO3 TMNO2 TMNO1 TMNO0 10DAH 00FFH C4BA 0 0 0 CACT4 CACT3 CACT2 CACT1 CACT0 TMNO7 TMNO6 TMNO5 TMNO4 TMNO3 TMNO2 TMNO1 TMNO0 111AH 00FFH Bit Position Bit Name Function 12 to 8 CACT4 to CACT0 Indicates the CAN module activity Remark The CACT4 to CACT0 bits reflect the status of the CAN protocol layer CACT4 CACT3 CACT2 CACT1 C...

Page 502: ...nction 7 to 0 TMNO7 to TMNO0 Indicates the message buffer which is either waiting to be transmitted or in transmis sion progress TMNO7 to TMNO0 Number of Transmit Message Buffer 0 to 31 Current transmit message buffer waiting for transmission or in transmission progress 32 to 254 Reserved not possible 255 No message waiting for transmission or in transmission progress ...

Page 503: ...aution In diagnostic mode the CxBRP register is hidden and the CxDINF register appears instead of it at the same address TLM 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address OffsetNote Initial value C1BRP TLM 0 0 0 0 0 0 0 0 BTYPE BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 105CH 0000H C2BRP TLM 0 0 0 0 0 0 0 0 BTYPE BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 109CH 0000H C3BRP TLM 0 0 0 0 0 0 0 0 BTYPE BRP5 BRP4 BRP3 BRP2 BR...

Page 504: ...TLM 1 BRP5 to BRP0 TLM 0 Specifies the bit rate prescaler for the CAN protocol layer TLM 0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 Bit Rate Prescaler fBTL fMEM 2 k 1 k 0 0 0 0 0 0 fBTL fMEM 2 0 0 0 0 0 0 1 fBTL fMEM 4 1 0 0 0 0 1 0 fBTL fMEM 6 2 0 0 0 0 1 1 fBTL fMEM 8 3 0 0 0 1 0 0 fBTL fMEM 10 4 1 1 1 1 1 0 fBTL fMEM 126 62 1 1 1 1 1 1 fBTL fMEM 128 63 TLM 1 BRP7 BRP6 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 Bit Rat...

Page 505: ... for which the CAN module is permitted to lengthen or shorten the phase segments is called synchronisation jump width SJW The SJW value must be less or equal the difference of DBT and SPT which corresponds to PHASE_SEG2 and can be specified in the range of 1 TQ to 4 TQ For additional information on the CAN bus bit timing please refer to ISO 11898 The relation between CAN memory clock and CAN bus b...

Page 506: ...WR0 SPTR4 SPTR3 SPTR2 SPTR1 SPTR0 DBTR4 DBTR3 DBTR2 DBTR1 DBTR0 105EH 0218H C2SYNC 0 0 0 SAMP SJWR1 SJWR0 SPTR4 SPTR3 SPTR2 SPTR1 SPTR0 DBTR4 DBTR3 DBTR2 DBTR1 DBTR0 109EH 0218H C3SYNC 0 0 0 SAMP SJWR1 SJWR0 SPTR4 SPTR3 SPTR2 SPTR1 SPTR0 DBTR4 DBTR3 DBTR2 DBTR1 DBTR0 10DEH 0218H C4SYNC 0 0 0 SAMP SJWR1 SJWR0 SPTR4 SPTR3 SPTR2 SPTR1 SPTR0 DBTR4 DBTR3 DBTR2 DBTR1 DBTR0 111EH 0218H Bit Position Bit N...

Page 507: ...gister is only possible when the CAN module is set to INIT mode 3 For setting the DBTR and SPTR bits some rules must be observed otherwise the CAN module will malfunction for details refer to chapter 14 4 Operating Considerations on page 509 Bit Position Bit Name Function 4 to 0 DBTR4 to DBTR0 Specifies the number of TQ per bit DBTR4 DBTR3 DBTR2 DBTR1 DBTR0 Data Bit Time DBTR q 1 TQ q 0 0 0 0 0 Se...

Page 508: ...er It is automati cally reset whenever a SOF is detected on the CAN bus Caution In normal operating mode the CxDINF register is hidden and the corresponding CxBRP register appears instead of it at the same address 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address OffsetNote Initial value C1DINF DINF15 DINF14 DINF13 DINF12 DINF11 DINF10 DINF9 DINF8 DINF7 DINF6 DINF5 DINF4 DINF3 DINF2 DINF1 DINF0 105CH ...

Page 509: ...estricted to a range from 8 TQ to 25 TQ which corre sponds to the DBTR4 to DBTR0 bits of the CxSYNC register 3 Rule for synchronization jump width SJW setting The number of TQ allowed for soft synchronization must not exceed the number of TQ for PHASE_SEG2 The length of PHASE_SEG2 is given by the difference of data bit time DBTR and the sampling point position SPTR Converted to register values the...

Page 510: ... baud rate is calculated The register descriptions show that the prescaler must be an even number between 2 and 128 the data bit time must be a value in the range 8 to 25 As the synchronization jump width SJW is defined as 3 TQ the maximum setting for the sampling point SPT can be only 3 TQ less than the setting for the data bit time DBT and also less than 17 TQ Based on the restrictions and assum...

Page 511: ... 15 data bit time DBT 16 TQ SPTR4 to SPTR0 01100B 12 sampling point SPT 13 TQ or BRP5 to BRP0 000111B 7 prescaler BRP 16 TQ DBTR4 to DBTR0 01011B 11 data bit time DBT 12 TQ SPTR4 to SPTR0 01000B 8 sampling point SPT 9 TQ 2 TLM 1 BRP7 to BRP0 00001011B 11 prescaler BRP 12 DBTR4 to DBTR0 01111B 15 data bit time DBT 16 TQ SPTR4 to SPTR0 01100B 12 sampling point SPT 13 TQ or BRP7 to BRP0 00001111B 15 ...

Page 512: ...CPU by sequential accesses to the CAN message buffers the following sequence has to be observed Figure 14 44 Sequential CAN Data Read by CPU As the DN flag is only set by the CAN module and cleared by the CPU only it is ensured that the CPU can recognize that new data is stored in the message buffer during the read operation Remark If the CPU reads the data by only one read access the data consist...

Page 513: ...the message is automatically started whenever the data length code from the M_DLCm register is read by the CPU and the data is copied from the message buffer into the temporary buffer As long as the CPU reads 16 bit data from consecutive addresses that means 16 bit burst read sequence M_DLCm M_CTRLm M_TIMEm M_DATAm0 m1 M_DATAm2 m3 M_DATAm4 m5 M_DATAm6 m7 M_IDLm M_IDHm the data is read from the tem...

Page 514: ... and µPD703129 A1 x 1 to 2 for the deriva tive µPD703128 A PowerOn RESET or RESET CxCTRL ISTAT 1 INIT 0 CxCTRL ISTAT 0 INIT 1 and CAN bus busy CAN bus idle SLEEP 1and CANbusbusy CxCTRL ISTAT 0 CxCTRL SLEEP 1 CxCTRL STOP 0 SLEEP 0 CxCTRL ISTAT 0 CxCTRL SLEEP 1 CxCTRL STOP 1 STOP 1 PowerOffor RESET PowerOffor RESET STOP 0and SLEEP 0 Detectionofbus transition Power Off or RESET CANbusbusy PowerOffor ...

Page 515: ... CAN interface Before any operation on the CAN memory can be done it is essential that the common control register are initialised The general initialisation sequence is shown in Figure 14 46 Figure 14 46 General Initialisation Sequence for the CAN Interface Remark Enabling the global operation does not automatically enable any CAN module Each CAN module must be initialised and enabled separately ...

Page 516: ...able all CAN modules for i 0 i CAN_MODULES i CAN_ModuleStop i clear GOM flag CGST 0x0001 CGST 0x00FF clear all flags of CGST CGIE 0x00FF disable global interrupts CGCS 0x0000 define internal clock CGTSC 0x0000 clear CAN global time system counter CGTEN 0x0000 disable all timer events clear all message buffers for i 0 i CAN_MESSAGES i CAN_ClearMessage i set GOM bit CGST 0x0100 return 0 ...

Page 517: ...sed by the sequence according to Figure 14 47 Figure 14 47 Initialisation Sequence for a CAN module Remark x 1 to 4 for the derivatives µPD703129 A and µPD703129 A1 x 1 to 2 for the deriva tive µPD703128 A INIT CAN MODULE Init the module registers CxCTRL but do not clear the INIT flag CxDEF CxIE CxBRP CxSYNC Define Masks Clear INIT flag register CxCTRL END ...

Page 518: ...xCTRL 0x00FE clear CxCTRL except INIT can_mod_ptr CxDEF 0x00FF clear CxDEF can_mod_ptr CxIE 0x00FF clear CxIE can_mod_ptr CxBRP brp_value set CxBRP can_mod_ptr CxSYNC sync_value set CxSYNC can_mod_ptr mask0_low 0x0000 clear mask0 can_mod_ptr mask0_high 0x0000 can_mod_ptr mask1_low 0x0000 clear mask1 can_mod_ptr mask1_high 0x0000 can_mod_ptr mask2_low 0x0000 clear mask2 can_mod_ptr mask2_high 0x000...

Page 519: ... There fore the sequence is only required if the CAN module is already in normal operation Figure 14 48 Setting CAN Module into Initialisation State Note In case of permanent bus activity the program loops for a long time Therefore a time out mech anism should be provided in order to limit the runtime of the routine Remark x 1 to 4 for the derivatives µPD703129 A and µPD703129 A1 x 1 to 2 for the ...

Page 520: ... unsigned char module_no can_module_type can_mod_ptr define CAN module ptr can_mod_ptr can_module module_no load CAN module ptr if can_mod_ptr CxCTRL 0x0001 0 if INIT flag not yet set can_mod_ptr CxCTRL 0x0100 set INIT flag while can_mod_ptr CxCTRL 0x0100 0 wait until initialisation state is confirmed ISTAT bit 1 return 0 ...

Page 521: ... malfunction on the corresponding CAN bus 1 For each CAN module x x 1 to 4 for the derivatives µPD703129 A and µPD703129 A1 x 1 to 2 for the derivative µPD703128 A a Enter sleep mode Set SLEEP bit 1 CxCTRL register or b Enter initialisation mode Set INIT bit 1 CxCTRL register and wait for ISTAT bit 1 2 Disable event processing Clear EVM flag CGST register 3 Stop the CAN global time system counter ...

Page 522: ...522 Preliminary User s Manual U15839EE1V0UM00 MEMO ...

Page 523: ...s 10 bit resolution on chip A D converter Analog inputs 12 channels Standby function Current cut between AVDD AGND if A D conversion is stopped Current cut between AVREF AGND if A D conversion is stopped A D conversion trigger modes A D trigger mode Successive approximation technique ...

Page 524: ...tput voltage of the D A converter 4 D A converter The D A converter is used to generate a voltage that matches an analog input The output voltage of the D A converter is controlled by the successive approximation register SAR 5 Successive approximation register SAR The SAR is a 10 bit register that controls the output value of the D A converter for comparing with an analog input voltage value When...

Page 525: ...F pin The AVREF pin is used to input reference voltage to the A D converter A signal input to the ANIm pin is converted to a digital signal based on the voltage applied between AVREF and AVSS m 0 to 11 If not using the AVREF pin connect it to AVDD or AVSS Note 10 AVSS pin The AVSS pin is the ground voltage pin of the A D converter Even if not using A D converter always ensure that this pin has the...

Page 526: ...abnormal conversion results that are obtained If an A D conversion result from which it is judged that an abnormality occurred in the system is obtained do not perform abnormality processing at once but perform it upon reconfirming the occurrence of an abnormality 3 Be sure that voltages outside the range AVSS to AVREF are not applied to pins being used as A D converter and input pins ANI5 ANI6 AN...

Page 527: ...egister ADS 15 3 1 Register format of A D Converter Control Register Table 15 2 Register format of A D Converter Control Register SFR name Symbol R W Manipulable Bit Unit After Reset 1 bit 8 bits 16 bits A D converter mode register ADM R W 00H Analog input channel setting register ADS R W 00H A D conversion result register ADCR R undef A D conversion result register ADCRL R undef A D conversion re...

Page 528: ...ster ADM Notes 1 The bits FR0 FR1 FR2 and FR3 must not be changed while ADCS bit is set 1 2 Conversion time actual A D conversion time Always set the time to 5 µs Conversion time 12 µs Caution Be sure not to change the setting of bits 0 1 and 6 from their reset value 0 If these bits are set 1 the operation is not guaranteed 7 6 5 4 3 2 1 0 Address Initial value ADM ADCS 0 FR3 FR2 FR1 FR0 0 0 FFFFF...

Page 529: ...djusted By the selection bits FR3 to FR0 in the ADM register the number of the conversion clocks can be set in the range of 84 to 216 However the settings modifying the conversion time TCONV must keep the following relation Example Provided that fPCLK 16 MHz A setting of bits FR3 to FR0 0101B will be chosen The conversion time is By this the conversion time results in 5 µs TCONV 12 µs TCONV Conver...

Page 530: ...st The conversion operation restarts from the beginning Figure 15 3 A D Converter Register ADS 7 6 5 4 3 2 1 0 Address Initial value ADS 0 0 0 0 ADS3 ADS2 ADS1 ADS0 FFFFF201H 0000H Bit Position Bit Name Function 3 to 0 ADS3 to ADS0 The bits ADS3 to ADS0 specify the analog input channel for which the A D conversion is performed ADS3 ADS2 ADS1 ADS0 Analog input channel 0 0 0 0 AIN0 0 0 0 1 AIN1 0 0 ...

Page 531: ... ADCRL register is the same as the lower byte of the ADCR register When reading all 8 bits of data of an A D conversion result from the ADCRL register only the higher 2 bits are valid and the lower 6 bits are always read 0 This register can be read in 1 bit or 8 bit units Figure 15 5 A D Conversion Result Register ADCRL 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value ADCR ADCR9 ADCR8 A...

Page 532: ...onversion The ADCRH register is the same as the higher byte of the ADCR register This register can be read in 1 bit or 8 bit units Figure 15 6 A D Conversion Result Register ADCRH 7 6 5 4 3 2 1 0 Address Initial value ADCRH ADCR9 ADCR8 ADCR7 ADCR6 ADCR5 ADCR4 ADCR3 ADCR2 FFFFF203H undef H Bit Position Bit Name Function 7 to 0 ADCR9 to ADCR2 The bits ADCR9 to ADCR2 hold the upper 8 bits result of t...

Page 533: ...lue of the analog input channel ANIx is disabled during A D conversion operation Remark x 0 to 11 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value Port7 Port8 0 0 0 0 P83 ANI11 P82 ANI10 P81 ANI9 P80 ANI8 P77 ANI7 P76 ANI6 P75 ANI5 P74 ANI4 P73 ANI3 P72 ANI2 P71 ANI1 P70 ANI0 FFFFF40CH undef Bit Position Bit Name Function 11 to 8 P83 to P80 The bits P83 to P80 holds the digital input va...

Page 534: ...t units Figure 15 8 Port Function Register 7 PORT7 Note Reading the digital value of the analog input channel ANIx is disabled during A D conversion operation Remark x 0 to 11 7 6 5 4 3 2 1 0 Address Initial value Port7 P77 ANI7 P76 ANI6 P75 ANI5 P74 ANI4 P73 ANI3 P72 ANI2 P71 ANI1 P70 ANI0 FFFFF40CH undef H Bit Position Bit Name Function 7 to 0 P77 to P70 The bits P77 to P70 holds the digital inp...

Page 535: ...the following expression or the following expression where INT Function which returns integer part of value in parentheses VIN Analog input voltage AVDD AVDD pin voltage and A D converter power supply ADCRL A D conversion result register ADCRL value Figure 15 9 Relation between Analog Input Voltage and A D Conversion Result on page 536 shows the relation between the analog input voltage and the A ...

Page 536: ... interrupt A D conversion termination interrupt INTAD 1 A D conversion termination interrupt INTAD In A D conversion enabled status an A D conversion termination interrupt is generated when the specified input channel A D conversion has terminated 1023 1022 1021 3 2 1 0 A D conversion result ADCR 1 2048 1 1024 3 2048 2 1024 5 2048 3 1024 2045 2048 1022 1024 2046 2048 1023 1024 2047 2048 1 Input vo...

Page 537: ...put is compared with the voltage generated by the D A converter 3 When the 10 bit comparison is completed the conversion result is stored in the ADCR ADCRL and ADCRH registers and a new conversion operation is started 4 An interrupt request signal INTAD is generated after completion of each conversion Notes 1 If a write operation is carried out to the ADM or the ADS register during conversion oper...

Page 538: ...D converter converts one analog input specified in the ADS register The conversion result is stored in the ADCR ADCRL ADCRH register Figure 15 10 No write operation is made to ADM or ADS register during A D conversion operation ANI0 Input A D conversion ADCR ADCRL ADCRH registers INTAD interrupt Conversion start ADCS bit of ADM register is set 1 ADS3 to ADS0 bits of ADS register are cleared 0 Data...

Page 539: ...Input A D conversion ADCR ADCRL ADCRH registers INTAD interrupt Conversion start ADCS bit of ADM register is set 1 ADS3 to ADS0 bits of ADS register are cleared 0 Data 1 Data 2 Data 3 Data 1 Data 2 ANI0 ANI0 Data 1 Data 2 ANI0 ANI0 Conversion stop ADCS bit of ADM register is cleared 0 A D conversion stops ADCS bit of ADM register is cleared 0 ...

Page 540: ...registers INTAD interrupt Conversion start ADCS bit of ADM register is set 1 ADS3 to ADS0 bits of ADS register are cleared 0 Data 1 Data 2 Data 1 Data 2 Data 3 Data 4 ANI0 ANI0 ANI1 ANI1 Data 1 Data 3 Data 4 ANI0 ANI1 ANI1 ANI0 Input Data 3 Data 4 Data 5 Data 5 ANI1 Conversion operation stopped conversion operation started with new setting of ADS register Write operation to ADS register ADS0 bit i...

Page 541: ...t increases in proportion to the output impedance of the analog input source it is recommended that a capacitor be connected externally as shown in Figure 15 13 Analog Input Pin Handling on page 541 to reduce noise Figure 15 13 Analog Input Pin Handling 4 ANI0 to ANI11 The analog input pins ANI0 to ANI11 also function as input port pins P80 to P83 P70 to P77 When A D conversion is performed with a...

Page 542: ...o the full scale is expressed by FSR Full Scale Range When the resolution is 10 bits 1LSB 1 210 1 1024 0 098 FSR Accuracy has no relation to resolution but is determined by the overall error 2 Overall Error This shows the maximum error value between the actual measured value and the theoretical value Zero scale error full scale error non linearity error and errors which are combinations of these e...

Page 543: ... 15 15 Quantization Error 4 Zero scale error This shows the difference between the actual measurement value of the analog input voltage and the theoretical value 1 2 LSB when the digital output changes from 0 000 to 0 001 If the actual measurement value is greater than the theoretical value it shows the difference between the actual measurement value of the analog input voltage and the theoretical...

Page 544: ... Error This shows the degree to which the conversion characteristics deviate from the ideal linear rela tionship It expresses the maximum value of the difference between the actual measurement value and the ideal straight line when the zero scale error and full scale error are 0 Figure 15 18 Nonlinearity Error 111 110 101 000 0 AVREF AVREF 1 AVREF 2 AVREF 3 Digital output Lower order 3 bits Analog...

Page 545: ...9EE1V0UM00 Chapter 16 Port Functions 16 1 Features Input Output ports 5 V 51 Input ports 5 V 12 Input Output ports 3 3 V 15 Ports alternate as input output pins of other peripheral functions Input or output can be specified in bit units ...

Page 546: ... ports have 3 3 V power The ports are named ports P1 through P9 and PAH PCM PCT and PCS The configuration is shown below Figure 16 1 Port Configuration Port 2 P20 to P27 Port 3 P30 to P35 Port 4 to P45 P40 Port 5 P50 to P56 Port 6 P60 to P67 Port 8 Port 9 P80 to P83 P90 P97 Port PAH Port PCS Port PCT PAH0 to PAH7 PCS0 PCS4 PCT0 PCT4 Port 1 P10 to P17 Port 7 P70 to P77 to PCS3 PCT1 PCM0 Port PCM ...

Page 547: ...input output CSI0 CSI1 UART0 A Port 3 P30 to P35 6 bit input output Real time pulse unit RPU input output External interrupt input A Port 4 P40 to P45 6 bit input output Real time pulse unit RPU input output External interrupt input A Port 5 P50 to P56 7 bit input output Real time pulse unit RPU input output Serial interface input output FCAN4Note External interrupt input A Port 6 P60 to P67 8 bit...

Page 548: ...4 Input mode P25 SCKO1 SCKI1 P25 Input mode P26 RXD0 P26 Input mode P27 TXD0 P27 Input mode Port 3 P30 TIG00 INTP00 P30 Input mode PMC3 P31 TOG01 TIG01 P31 Input mode P32 TOG02 TIG02 P32 Input mode P33 TOG03 TIG03 P33 Input mode P34 TOG04 TIG04 P34 Input mode P35 TIG05 INTP05 P35 Input mode Port 4 P40 TIG10 INTP10 P40 Input mode PMC4 P41 TOG11 TIG11 P41 Input mode P42 TOG12 TIG12 P42 Input mode P4...

Page 549: ...8 P80 Input ANI8 P81 ANI9 P81 Input ANI9 P82 ANI10 P82 Input ANI10 P83 ANI11 P83 Input ANI11 Port 9 P90 P90 Input mode P91 P91 Input mode P92 P92 Input mode P93 P93 Input mode P94 P94 Input mode P95 P95 Input mode P96 P96 Input mode P97 P97 Input mode Port AH PAH0 A16 A16 Address output mode PMCAH PAH1 A17 A17 Address output mode PAH2 A18 A18 Address output mode PAH3 A19 A19 Address output mode PA...

Page 550: ...00 Port Name Pin Name Pin Function after Reset Mode Setting Register Port CT PCT0 LWR PCT0 Input mode PMCCT PCT1 UWR PCT1 Input mode PCT4 RD RD Read strobe signal output mode Port CM PCM0 WAIT WAIT Wait insertion signal input mode PMCCM Table 16 2 Port Pin Functions 3 3 ...

Page 551: ...pe A Block Diagram Remark N 1 to 6 9 Port number n 0 to 7 Port pin for port number 1 2 6 9 n 0 to 6 Port pin for port number 5 n 0 to 3 Port pin for port number 3 4 Peripheral Bus WRPMC Nn PMC Nn WRPM Nn PM Nn WRP Nn P Nn RDP Nn Selector Selector Address Selector Peripheral Function P Nn Peripheral Function ...

Page 552: ...ort Functions Preliminary User s Manual U15839EE1V0UM00 Figure 16 3 Type B Block Diagram Remark n 0 to 7 Peripheral Bus WRPMCAHn PMCAHn WRPMAHn PMAHn WRPAHn PAHn RDPAHn Selector Selector Address Selector A23 A16 PAHn 0 ...

Page 553: ...rt Functions Preliminary User s Manual U15839EE1V0UM00 Figure 16 4 Type C Block Diagram Remark n 0 3 4 Peripheral Bus WRPMCCSn PMCCSn WRPMCSn PMCSn WRPCSn PCSn RDPCSn Selector Selector Address Selector CS0 CS3 CS4 PCSn ...

Page 554: ...ort Functions Preliminary User s Manual U15839EE1V0UM00 Figure 16 5 Type D Block Diagram Remark n 0 1 4 Peripheral Bus WRPMCCTn PMCCTn WRPMCTn PMCTn WRPCTn PCTn RDPCTn Selector Selector Address Selector WR0 WR1 RD PCTn ...

Page 555: ...apter 16 Port Functions Preliminary User s Manual U15839EE1V0UM00 Figure 16 6 Type E Block Diagram Peripheral Bus WRPMCCMn PMCCMn WRPMCMn PMCMn WRPCMn PCMn RDPCMn Selector Selector Address Selector WAIT PCMn ...

Page 556: ...ctioning as a port in control mode it also can operate as the serial interface UART1 FCAN1 FCAN2 FCAN3Note 3 input output 1 Operation in control mode Notes 1 If using peripheral functions the direction setting for the respective port bit is not forced automatically Port bit direction has to be programmed according to the peripheral function requirement by setting the port mode register 2 The reset...

Page 557: ...et using the port 1 mode control register PMC1 a Port 1 mode register PM1 This register can be read or written in 8 bit or 1 bit units Figure 16 8 Port 1 Mode Register PM1 7 6 5 4 3 2 1 0 Address At Reset PM1 PM17 PM16 PM15 PM14 PM13 PM12 PM11 PM10 FFFFF420H FFH Bit Position Bit Name Function 7 to 0 PM1n n 7 to 0 Specifies input output mode of P1n pin 0 Output mode Output buffer on 1 Input mode Ou...

Page 558: ...put mode 6 PMC16 Specifies operation mode of P16 pin 0 Input output port mode 1 RXD1 input mode 5 PMC15 Specifies operation mode of P15 pin 0 Input output port mode 1 CTXD3 output mode 4 PMC14 Specifies operation mode of P14 pin 0 Input output port mode 1 CRXD3 input mode 3 PMC13 Specifies operation mode of P13 pin 0 Input output port mode 1 CTXD2 output mode 2 PMC12 Specifies operation mode of P1...

Page 559: ...nd those values are immediately output Besides functioning as a port in control mode it also can operate as the serial interface UART0 CSI0 CS1 input output Notes 1 If using peripheral functions the direction setting for the respective port bit is not forced automatically Port bit direction has to be programmed according to the peripheral function requirement by setting the port mode register 2 Th...

Page 560: ...t using the port 2 mode control register PMC2 a Port 2 mode register PM2 This register can be read or written in 8 bit or 1 bit units Figure 16 11 Port 2 Mode Register PM2 7 6 5 4 3 2 1 0 Address At Reset PM2 PM27 PM26 PM25 PM24 PM23 PM22 PM21 PM20 FFFFF422H FFH Bit Position Bit Name Function 7 to 0 PM2n n 7 to 0 Specifies input output mode of P2n pin 0 Output mode Output buffer on 1 Input mode Ou...

Page 561: ...ut mode 6 PMC26 Specifies operation mode of P26 pin 0 Input output port mode 1 RXD0 input mode 5 PMC25 Specifies operation mode of P25 pin 0 Input output port mode 1 SCK1 input output mode 4 PMC24 Specifies operation mode of P24 pin 0 Input output port mode 1 SO1 output mode 3 PMC23 Specifies operation mode of P23 pin 0 Input output port mode 1 SI1 input mode 2 PMC22 Specifies operation mode of P2...

Page 562: ... Besides functioning as a port in control mode it also can operate as the real time pulse unit RPU input output and external interrupt request input Notes 1 If using peripheral functions the direction setting for the respective port bit is not forced automatically Port bit direction has to be programmed according to the peripheral function requirement by setting the port mode register 2 The reset ...

Page 563: ... output mode of P2n pin 0 Output mode Output buffer on 1 Input mode Output buffer off 7 6 5 4 3 2 1 0 Address At Reset PMC3 0 0 PMC35 PMC34 PMC33 PMC32 PMC31 PMC30 FFFFF444H 00H Bit Position Bit Name Function 5 PMC35 Specifies operation mode of P35 pin 0 Input output port mode 1 TIG05 input mode or external interrupt request INTP05 input mode 4 PMC34 Specifies operation mode of P34 pin 0 Input out...

Page 564: ... Besides functioning as a port in control mode it also can operate as the real time pulse unit RPU input output and external interrupt request input Notes 1 If using peripheral functions the direction setting for the respective port bit is not forced automatically Port bit direction has to be programmed according to the peripheral function requirement by setting the port mode register 2 The reset ...

Page 565: ... output mode of P4n pin 0 Output mode Output buffer on 1 Input mode Output buffer off 7 6 5 4 3 2 1 0 Address At Reset PMC4 0 0 PMC45 PMC44 PMC43 PMC42 PMC41 PMC40 FFFFF446H 00H Bit Position Bit Name Function 5 PMC45 Specifies operation mode of P45 pin 0 Input output port mode 1 TIG15 input mode or external interrupt request INTP15 input mode 4 PMC44 Specifies operation mode of P44 pin 0 Input out...

Page 566: ...al time pulse unit RPU input output as the serial interface FCAN4Note 3 and as external interrupt request input 1 Operation in control mode Notes 1 If using peripheral functions the direction setting for the respective port bit is not forced automatically Port bit direction has to be programmed according to the peripheral function requirement by setting the port mode register 2 The reset value of ...

Page 567: ...set using the port 5 mode control register PMC5 a Port 5 mode register PM5 This register can be read or written in 8 bit or 1 bit units Figure 16 20 Port 5 Mode Register PM5 7 6 5 4 3 2 1 0 Address At Reset PM5 0 PM56 PM55 PM54 PM53 PM52 PM51 PM50 FFFFF428H 7FH Bit Position Bit Name Function 7 to 0 PM5n n 7 to 0 Specifies input output mode of P5n pin 0 Output mode Output buffer on 1 Input mode Out...

Page 568: ... TO0 output mode 5 PMC55 Specifies operation mode of P55 pin 0 Input output port mode 1 TI1 input mode or external interrupt request INTP21 input mode 4 PMC54 Specifies operation mode of P54 pin 0 Input output port mode 1 TI0 input mode or external interrupt request INTP20 input mode 3 PMC53 Specifies operation mode of P53 pin 0 Input output port mode 1 External interrupt request INTP5 input mode ...

Page 569: ...mediately output Besides functioning as a port in control mode it also can operate as the serial interface CSI2 or as external interrupt request input Notes 1 If using peripheral functions the direction setting for the respective port bit is not forced automatically Port bit direction has to be programmed according to the peripheral function requirement by setting the port mode register 2 The rese...

Page 570: ...t using the port 6 mode control register PMC6 a Port 6 mode register PM6 This register can be read or written in 8 bit or 1 bit units Figure 16 23 Port 6 Mode Register PM6 7 6 5 4 3 2 1 0 Address At Reset PM6 PM66 PM66 PM65 PM64 PM63 PM62 PM61 PM60 FFFFF42AH FFH Bit Position Bit Name Function 7 to 0 PM6n n 7 to 0 Specifies input output mode of P6n pin 0 Output mode Output buffer on 1 Input mode Ou...

Page 571: ...P65 pin 0 Input output port mode 1 SCK2 input output mode 6 PMC66 Specifies operation mode of P65 pin 0 Input output port mode 1 SO2 output mode 5 PMC65 Specifies operation mode of P65 pin 0 Input output port mode 1 SI2 input mode 4 PMC64 Specifies operation mode of P64 pin 0 Input output port mode 1 External interrupt request INTP3 input mode 3 PMC63 Specifies operation mode of P63 pin 0 Input ou...

Page 572: ...vailable for port 7 This register can be read in 1 bit or 8 bit units Figure 16 25 Port Function Register 7 P7 Note Reading the digital value of the analog input channel ANIx is disabled during A D conversion operation Remark x 0 to 7 7 6 5 4 3 2 1 0 Address Initial value P7 P77 ANI7 P76 ANI6 P75 ANI5 P74 ANI4 P73 ANI3 P72 ANI2 P71 ANI1 P70 ANI0 FFFFF40CH undef H Bit Position Bit Name Function 7 t...

Page 573: ...ort Function Register 7 8 P7 P8 Note Reading the digital value of the analog input channel ANIx is disabled during A D conversion operation Remark x 0 to 11 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value P7 P8 0 0 0 0 P83 ANI11 P82 ANI10 P81 ANI9 P80 ANI8 P77 ANI7 P76 ANI6 P75 ANI5 P74 ANI4 P73 ANI3 P72 ANI2 P71 ANI1 P70 ANI0 FFFFF40CH undef Bit Position Bit Name Function 11 to 8 P83 ...

Page 574: ...at register and those values are immediately output Note The reset value of register P9 is 00H Due to the input mode of the port after reset the read input value is determined by the port pins 1 Setting in input output mode Port 9 is set in input output mode using the port 9 mode register PM9 a Port 9 mode register PM9 This register can be read or written in 8 bit or 1 bit units Figure 16 28 Port ...

Page 575: ...ister is read the values of PAH are read Writing to the PAH register writes the values to that register and those values are immediately output Besides functioning as a port in control mode it also can operate as an address bus Notes 1 If using peripheral functions the direction setting for the respective port bit is not forced automatically Port bit direction has to be programmed according to the...

Page 576: ...r PMCAH This register can be read or written in 8 bit or 1 bit units Figure 16 31 Port AH Mode Control Register PMCAH 7 6 5 4 3 2 1 0 Address At Reset PMAH PMAH7 PMAH6 PMAH5 PMAH4 PMAH3 PMAH2 PMAH1 PMAH0 FFFF022FH 00H Bit Position Bit Name Function 7 to 0 PMAHn n 7 to 0 Specifies input output mode of PAHn pin 0 Output mode Output buffer on 1 Input mode Output buffer off 7 6 5 4 3 2 1 0 Address At ...

Page 577: ...re immediately output Besides functioning as a port in control mode it also can operate as the chip select signal output when memory is accesses externally Notes 1 If using peripheral functions the direction setting for the respective port bit is not forced automatically Port bit direction has to be programmed according to the peripheral function requirement by setting the port mode register 2 The...

Page 578: ...S3 0 0 PMCS0 FFFFF028H 18H Bit Position Bit Name Function 4 PMCS4 Specifies input output mode of PCS4 pin 0 Output mode Output buffer on 1 Input mode Output buffer off 3 PMCS3 Specifies input output mode of PCS3 pin 0 Output mode Output buffer on 1 Input mode Output buffer off 0 PMCS0 Specifies input output mode of PCS0 pin 0 Output mode Output buffer on 1 Input mode Output buffer off 7 6 5 4 3 2 ...

Page 579: ... in control mode PCT0 and PCT1 can operate as the write strobe signal outputs when memory is accessed externally PCT4 can also operate as the read strobe signal input Notes 1 If using peripheral functions the direction setting for the respective port bit is not forced automatically Port bit direction has to be programmed according to the peripheral function requirement by setting the port mode reg...

Page 580: ...02AH 03H Bit Position Bit Name Function 4 PMCT4 Specifies input output mode of PCT4 pin 0 Output mode Output buffer on 1 Input mode Output buffer off 1 PMCT1 Specifies input output mode of PCT1 pin 0 Output mode Output buffer on 1 Input mode Output buffer off 0 PMCT0 Specifies input output mode of PCT0 pin 0 Output mode Output buffer on 1 Input mode Output buffer off 7 6 5 4 3 2 1 0 Address At Res...

Page 581: ...ely output Besides functioning as a port in control mode PCM0 can operate as the wait insertion signal input when external slow memory peripherals are connected Notes 1 If using peripheral functions the direction setting for the respective port bit is not forced automatically Port bit direction has to be programmed according to the peripheral function requirement by setting the port mode register ...

Page 582: ...e Register PMCM b Port mode control register PMCCM This register can be read or written in 8 bit or 1 bit units Figure 16 40 Port CM Mode Control Register PMCCM 7 6 5 4 3 2 1 0 Address At Reset PMCM 0 0 0 0 0 0 0 PMCM0 FFFFF02CH 01H Bit Position Bit Name Function 0 PMCM0 Specifies input output mode of PCM0 pin 0 Output mode Output buffer on 1 Input mode Output buffer off 7 6 5 4 3 2 1 0 Address At...

Page 583: ...us is released and the CPU starts program execution The user has to initialize the contents of various registers as needed within the pro gram 17 2 Features Noise elimination of RESET pin using analog delay 17 3 Pin Functions During a system reset most pins all but the RESOUT VDDn VSSn CVDD CVSS AVDD AVREF pins enter the high impedance state Therefore when memory is connected externally a pull up ...

Page 584: ...4 to FCRXD3 only for µPD703129 Pin Function RESET D 15 0 Hi Z A 23 0 Hi Z CS 4 3 0 Hi Z WR 1 0 Hi Z RD Hi Z WAIT RESOUT LOW TIG05 to TIG00 TIG15 to TIG10 TIC01 to TIC00 N A INTP05 INTP00 INTP15 INTP10 INTP21 INTP20 INTP5 to INTP0 NMI N A TOG04 to TOG01 TOG14 to TOG11 TOC0 N A SO02 SO01 SO00 N A SI02 SI01 SI00 N A SCK02 SCK01 SCK00 N A RXD51 RXD50 N A TXD51 TXD50 N A FCRXD3 to FCRXD0Note N A FCTXD3...

Page 585: ...ecution is started All register will be initialized The RESET pin incorporates a noise eliminator which uses analogue delay to prevent malfunction due to noise 1 Reset signal acknowledgment Figure 17 1 Reset signal acknowledgment Note The internal system reset signal keeps its active level for at least four system clock cycles after a RESET pin is released RESET Internal system reset signal Elimin...

Page 586: ...e has to be applied to the RESET pin This is to secure the clock stabilization time that is necessary after the power is turned on and before a reset signal can be acknowledged Please refer to the Electrical Data Sheet for Jupiter Figure 17 2 Reset at power on RESET pin DD Reset release Analog delay Oscillation stabilization time V ...

Page 587: ... into the Reset circuit Oscillation stabilization time is not required after this reset Except WDT reset was triggered in sub watch mode or stop mode This case is handled by the clock controller 17 6 Reset Output Jupiter has an output RESOUT pin to indicate an internal system reset caused by RESET pin or Watch dog timer This reset output is used to terminate any ongoing internal erasing or program...

Page 588: ...ing are synchronized On a RESET other than this data is maintained in its previous status On Chip Hardware Register Name Initial Value After Reset CPU Program registers General purpose register r0 00000000H General purpose registers r1 to r31 Undefined Program counter PC 00000000H System registers Status save registers during interrupt EIPC EIPSW Undefined Status save registers during NMI FEPC FEP...

Page 589: ... Instructions are divided into each instruciton group and described This column shows instruction mnemonics This column shows instruction operands refer to Table B 1 This column shows instruction operations refer to Table B 3 This column shows flag statuses refer to Table B 4 This column shows instruction codes opcode in binary format 32 bit instructions are displayed in 2 lines refer to Table B 2...

Page 590: ...Element pointer r30 bit 3 3 bit data for bit number specification imm bit immediate data disp bit displacement regID System register number vector 5 bit data that specifies trap vector number 00H to 1FH cccc 4 bit data that indicates condition code Symbol Description R 1 bit data of code that specifies reg1 or regID r 1 bit data of code that specifies reg2 d 1 bit data of displacement i 1 bit data...

Page 591: ...c to bit b of address a saturated n Performs saturated processing of n n is 2ís complements Result of calculation of n If n is n 7FFFFFFFH as result of calculation 7FFFFFFFH If n is n 80000000H as result of calculation 80000000H result Reflects result to a flag Byte Byte 8 bits Halfword Half word 16 bits Word Word 32 bits Add Subtract Bit concatenation Multiply Divide AND Logical product OR Logica...

Page 592: ...C NL 1001 CY 0 No carry No lower Greater than or equal Z E 0010 Z 1 Zero Equal NZ NE 1010 Z 0 Not zero Not equal NH 0011 CY OR Z 1 Not higher Less than or equal H 1011 CY OR Z 0 Higher Greater than N 0100 S 1 Negative P 1100 S 0 Positive T 0101 Always unconditional SA 1101 SAT 1 Saturated LT 0110 S XOR OV 1 Less than signed GE 1110 S XOR OV 0 Greater than or equal signed LE 0111 S XOR OV OR Z 1 Le...

Page 593: ...3 adr GR reg1 sign extend disp16 GR reg2 Load memory adr Word SST B reg2 disp7 ep rrrrr0111 ddddddd adr ep zero extend disp7 Store memory adr GR reg2 Byte SST H reg2 disp8 ep rrrrr1001 ddddddd Note 1 adr ep zero extend disp8 Store memory adr GR reg2 Halfword SST W reg2 disp8 ep rrrrr1010 dddddd1 Note 2 adr ep zero extend disp8 Store memory adr GR reg2 Word ST B reg2 disp16 reg1 rrrrr1110 10RRRRR d...

Page 594: ...g1 reg2 rrrrr1110 01RRRRR ddddddddd dddddd1 Note 3 adr GR reg1 sign extend disp16 GR reg2 Load memory adr Word SST B reg2 disp7 ep rrrrr0111 ddddddd adr ep zero extend disp7 Store memory adr GR reg2 Byte ADD reg1 reg2 rrrrr001110 RRRRR GR reg2 GR reg2 GR reg1 ADD imm5 reg2 rrrrr010010i iiii GR reg2 GR reg2 sign extend imm5 Table A 6 Instruction Set List 2 7 Instruction Group Mne monic Operand Opco...

Page 595: ...11 1110cccc 00000000 00000000 if conditions are satisfied then GR reg2 00000001H else GR reg2 00000000H Saturated operation SAT ADD reg1 reg2 rrrrr000 110RRRRR GR reg2 saturated GR reg2 GR reg1 SAT ADD imm5 reg2 rrrrr010 001iiiii GR reg2 saturated GR reg2 sign extend imm5 SAT SUB reg1 reg2 rrrrr000 101RRRRR GR reg2 saturated GR reg2 GR reg1 Table A 6 Instruction Set List 3 7 Instruction Group Mne ...

Page 596: ... iiiiiiii GR reg2 GR reg1 XOR zero extend imm16 0 NOT reg1 reg2 rrrrr0000 01RRRRR GR reg2 NOT GR reg1 0 SHL reg1 reg2 rrrrr1111 11RRRRR 000000001 1000000 GR reg2 GR reg2 logically shift left by GR reg1 0 SHL imm5 reg2 rrrrr0101 10iiiii GR reg2 GR reg2 logically shift left by zero extend imm5 0 Table A 6 Instruction Set List 4 7 Instruction Group Mne monic Operand Opcode Operation Flag CY OV S Z SA...

Page 597: ...Bit manip ulate SET1 bit 3 disp16 reg1 00bbb1111 10RRRRR ddddddddd ddddddd adr GR reg1 sign extend disp16 Z flag Not Load memory bit adr bit 3 Store memory bit adr bit 3 1 CLR1 bit 3 disp16 reg1 10bbb1111 10RRRRR ddddddddd ddddddd adr GR reg1 sign extend disp16 Z flag Not Load memory bit adr bit 3 Store memory bit adr bit 3 0 Table A 6 Instruction Set List 5 7 Instruction Group Mne monic Operand O...

Page 598: ... to 0FH 00000050H vector 10H to 1FH RETI 000001111 1100000 000000010 1000000 if PSW EP 1 then PC EIPC PSW EIPSW else if PSW NP 1 then PC FEPC PSW FEPSW else PC EIPC PSW EIPSW R R R R R HALT 000001111 1100000 000000010 0100000 Stops Table A 6 Instruction Set List 6 7 Instruction Group Mne monic Operand Opcode Operation Flag CY OV S Z SAT Notes 1 ddddddd is the higher 7 bits of disp8 2 dddddd is the...

Page 599: ... CY OV S Z SAT Notes 1 ddddddd is the higher 7 bits of disp8 2 dddddd is the higher 6 bits of disp8 3 ddddddddddddddd is the higher 15 bits of disp16 4 Only the lower half word data is valid 5 ddddddddddddddddddddd is the higher 21 bits of dip22 6 dddddddd is the higher 8 bits of disp9 7 The op code of this instruction uses the field of reg1 through the source register is shown as reg2 in the abov...

Page 600: ...600 Preliminary User s Manual U15839EE1V0UM00 MEMO ...

Page 601: ...I00 to ANI11 49 ASC 132 ASIF0 ASIF1 371 ASIM0 367 ASIM1 367 ASIS0 to ASIS2 370 Asynchronous reset 275 Asynchronous serial interface mode registers 367 Asynchronous serial interface status registers 370 Asynchronous serial interface transmission status registers 371 Autofill Function 165 autofill function 155 AVDD 50 525 AVREF 50 525 AVSS 50 525 B Baud rate generator control registers 386 BCC 134 B...

Page 602: ...cked serial interface mode registers 395 Clocked serial interface read only reception buffer registers 400 Clocked serial interface read only reception buffer registers Low 401 Clocked serial interface reception buffer registers 398 Clocked serial interface reception buffer registers Low 399 Clocked serial interface transmission buffer registers 402 Clocked serial interface transmission buffer reg...

Page 603: ...p transfer mode 189 Transfer end 197 Transfer mode 187 Transfer object 193 Transfer start factors 194 Transfer types 193 Two cycle transfer 193 DMA destination address registers 172 173 DMA disable status register 178 DMA restart register 178 DMA source address registers 170 171 DMA transfer count registers 174 DMA trigger factor registers 0 to 3 179 180 181 182 DMAC 169 DN 446 447 451 464 475 477...

Page 604: ...f each port 547 Functions of each port pin on reset and registers that set port or control mode 548 G GCCn0 311 GCCn5 311 GCCnm 312 General registers 56 57 general registers 55 57 Global pointer 57 H Halfword access 16 bits 121 HALT mode 253 256 handler addresses 70 high impedance state 583 I iCache 55 ID 220 IDLE Mode 258 IDLE mode 253 idle states 137 Illegal opcode definition 230 images 66 IMR0 ...

Page 605: ... INTSER1 374 INTSR0 374 INTSR1 374 INTST0 374 INTST1 374 ISPR 220 L Least Recently Used 155 Link pointer 57 Load store instructions with long short format 24 LOCK0 165 low power systems 251 LRU algorithm 155 M malfunction 583 Maskable interrupt status flag 220 Maskable interrupts 209 Priorities 212 Match and clear mode 335 match and clear mode 322 MODE 62 159 MODE0 to MODE3 49 Multiple interrupt p...

Page 606: ...l area selection control register BPC 114 Peripheral I O 76 peripheral I O 74 Peripheral Status 106 PHCMD 105 PHS 106 Pin functions 33 40 Pin I O circuits 54 Pin Identification 28 pipeline 55 PLL synthesizer 239 PM1 557 560 563 565 567 570 574 576 578 580 582 PMC1 558 561 563 565 568 571 576 578 580 582 PMW 340 Port 1 40 556 559 562 564 566 569 572 573 574 575 577 579 Port 2 41 Port 3 42 43 Port 5...

Page 607: ...ounter 306 Pulse width measurement 335 PWM 271 291 306 331 Q Quantization Error 543 R RAM 30 Reception buffer registers 372 Reception completion interrupt 374 Reception error interrupt 374 re initialize 583 RESET 49 RESET mode 357 Reset signal acknowledgment 585 ROM 30 ROMC 145 ROM less 62 RXB0 RXB1 372 S Sample and hold circuit 524 SAR 524 Saturated operation instructions 24 Saturation 61 Serial ...

Page 608: ...271 Timer C control register 0 278 Timer C control register 1 280 Timer D counter Register 298 Timer Dn compare register 299 Timer Dn control register 301 Timer G capture compare registers with external PWW output function 312 Timer Gn 16 bit counter registers 310 Timer Gn capture compare registers of the 2 counters 311 Timer Gn Channel Mode Register 316 Timer Gn Mode Register 313 315 Timer Gn out...

Page 609: ...clock frequency 355 Watch timer mode control register 350 watchdog timer 587 Watchdog timer clock selection register 359 Watchdog timer command register 361 Watchdog timer command status register 361 Watchdog Timer Control Register 359 Watchdog timer mode register 360 WCMD 361 WDCS 359 WDTM 360 Word access 32 bits 123 WPHS 361 Wrap around 67 WTM 350 X X1 49 X2 49 Z Zero register 57 Zero scale erro...

Page 610: ...610 Preliminary User s Manual U15839EE1V0UM00 ...

Page 611: ... 02 2719 5951 Address North America NEC Electronics Inc Corporate Communications Dept Fax 1 800 729 9288 1 408 588 6130 Europe NEC Electronics Europe GmbH Market Communication Dept Fax 49 211 6503 274 South America NEC do Brasil S A Fax 55 11 6465 6829 Asian Nations except Philippines NEC Electronics Singapore Pte Ltd Fax 65 6250 3583 Japan NEC Semiconductor Technical Hotline I would like to repor...

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