NEC mPD703128, Preliminary User'S Manual

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Chapter 10 Timer
Preliminary User’s Manual U15839EE1V0UM00
Calculation:
The cycle of signals input to the INTCCC00 pin is calculated by obtaining the difference between
the TMC0 register’s count value (Dx) that was captured in the CCC00 register according to the
x-th valid edge input of the TIC00 pin and the TMC0 register’s count value (D(x+1)) that was
captured in the CCC00 register according to the (x+1)-th valid edge input of the TIC00 pin and
multiplying the value of this difference by the cycle of the clock control signal.
(Similarly the cycle of signals input to the INTCCC01 pin is calculated by obtaining the difference
between the TMC0 register’s count value (Dx) that was captured in the CCC01 register according
to the x-th valid edge input of the TIC01 pin and the TMC0 register’s count value (D(x+1)) that was
captured in the CCC01 register according to the (x+1)-th valid edge input of the TIC01 pin and
multiplying the value of this difference by the cycle of the clock control signal.)
Figure 10-12: Timing of cycle measurement operation
Caution: An overflow must not be generated more than once between the 1st and 2nd
INTCCC00 interrupts.
Remarks: 1. D0 to D3: TMC0 register’s count values
2. t: Count clock cycle
3. In this example, the valid edge of TIC00 input has been set to both edges (rising and
falling).
t
0001H 0000H 0001H 0000H FFFFH D0 D1 D2 D3
D3 D2 D1 D0
(D1 – D0) t (D3 – D2) t {(10000H – D1) + D2} t
TMC0
TIC00
(input)
CCC00
register
INTCCC00
interrupt
INTTMC0
interrupt
No overflow Overflow occurs No overflow
Clear Count start
x
x
x
f
COUNT