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Chapter 10
Timer
Preliminary User’s Manual U15839EE1V0UM00
(a) Example: Pulse width or period measurement of the TIGny input signal (free run)
Capture setting method:
(1)
When using one of the TOGn1 to TOGn4 pins, select the corresponding counter with the TBGm
bit. When TIGn0 is used, the corresponding counter is TMGn0. When TIGn5 is used, the
corresponding counter is TMGn1.
(2)
Select a count clock cycle with the CSE12 to CSE10 bits (TMGn1) or CSE02 to CSE02 bits
(TMGn0).
(3)
Select a valid TIGny edge with the IEGy1 and IEGy0 bits. A rising edge, falling edge, or both
edges can be selected.
(4)
Start timer operation by setting POWER bit and TMG0E bit for TMGn0 or TMG1E bit for TMGn1.
Capture Operation
(1)
When a specified edge is detected, the value of the counter is stored in GCCny and an edge
detection interrupt (INTCCGny) is output.
(2)
When the counter overflows, an overflow interrupt (INTTMGn0 or INTTMGn1) is generated.
(3)
If an overflow has occurred between capture operations, the CCFGy flag is set when GCCny is
read. Correct capture data by checking the value of CCFGy.
Using CCFGy:
When using GCCny as a capture register, use the procedure below.
<1> After INTCCGny (edge detection interrupt) generation, read the corresponding GCCny register.
<2> Check if the corresponding CCFGy bit of the TMGSTn register is set.
<3> If the CCFGy bit is set, the counter was cleared from the previous captured value.
CCFGy is set when GCCny is read. So, after GCCny is read, the value of CCFGy should be read.
Using the procedure above, the value of CCFGy corresponding to GCCny can be read normally.
Caution:
If two or more overflows occur between captures, a software-based measure needs
to be taken to count overflow interrupts (INTTMGn0, INTTMGn1).
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