User’s Manual U13850EJ4V0UM
417
CHAPTER 16 REGULATOR
16.1 Outline
The V850/SB1 and V850/SB2 incorporate a regulator to realize a 5 V single power supply, low power
consumption, and to reduce noise.
This regulator supplies a voltage obtained by stepping down V
DD
power supply voltage to oscillation blocks and
on-chip logic circuits (excluding the A/D converter and output buffers). The regulator output voltage is set to 3.3 V
(V850/SB1) or 3.0 V (V850/SB2).
Refer to
2.4 I/O Circuit Types, I/O Buffer Power Supply and Connection of Unused Pins
for the power supply
corresponding to each pin.
Figure 16-1. Regulator
A/D converter
4.5 V
to
5.5 V
AV
DD
Main/Sub
oscillators
On-chip digital circuit
3.3 V: V850/SB1
3.0 V: V850/SB2
Regulator
V
DD
BV
DD
EV
DD
Flash memory
3.0 V
to
5.5 V
3.0 V to
5.5 V
Bi-directional
level shifter
EV
DD-
system I/O buffer
BV
DD-
system I/O
buffer
V
PP
RE
GC
16.2 Operation
The regulators of the V850/SB1 and V850/SB2 operate in every mode (STOP, IDLE, HALT).
For stabilization of regulator outputs, connect an electrolytic capacitor of about 1
µ
F to the REGC pin.