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NEC MPD703030A, User Manual

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CHAPTER  10    SERIAL  INTERFACE  FUNCTION

User’s Manual  U13850EJ4V0UM

274

(6)

Wait signal (WAIT)

The wait signal (WAIT) is used to notify the communication partner that a device (master or slave) is preparing
to transmit or receive data (i.e., is in a wait state).
Setting the SCLn pin to low level notifies the communication partner of the wait status.  When wait status has
been canceled for both the master and slave devices, the next data transfer can begin (n = 0, 1).

Figure 10-23.  Wait Signal (1/2)

(a)  When master device has a nine-clock wait and slave device has an eight-clock wait

(master:  transmission, slave: reception, and ACKEn = 1)

SCL

6

SDA

7

8

9

1

2

3

SCL

IIC0

6

H

7

8

1

2

3

D2

D1

D0

ACK

D7

D6

D5

9

IIC0

SCL

ACKE

Master

Master returns to high
impedance but slave
is in wait state (low level).

Wait after output
of ninth clock.

IIC0 data write (cancel wait)

Slave

Wait after output
of eighth clock.

 FFH is written to IIC0 or WREL is set to 1.

Transfer lines

Remark

n = 0, 1

Summary of Contents for MPD703030A

Page 1: ... µ µPD703035AY µ µ µ µPD703032A µ µ µ µPD703036A µ µ µ µPD703032AY µ µ µ µPD703036AY µ µ µ µPD703033A µ µ µ µPD703037A µ µ µ µPD703033AY µ µ µ µPD703037AY µ µ µ µPD70F3032A µ µ µ µPD70F3035A µ µ µ µPD70F3032AY µ µ µ µPD70F3035AY µ µ µ µPD70F3033A µ µ µ µPD70F3037A µ µ µ µPD70F3033AY µ µ µ µPD70F3037AY Printed in Japan Document No U13850EJ4V0UM00 4th edition Date Published April 2001 N CP K 1998 19...

Page 2: ...User s Manual U13850EJ4V0UM 2 MEMO ...

Page 3: ...ed to VDD or GND with a resistor if it is considered to have a possibility of being an output pin All handling related to the unused pins must be judged device by device and related specifications governing the devices 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note Power on does not necessarily define initial status of MOS device Production process of MOS does not define the initial operation ...

Page 4: ...ce the quality reliability and safety of NEC semiconductor products customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely To minimize risks of damage to property or injury including death to persons arising from defects in NEC semiconductor products customers must incorporate sufficient safety measures in their design such as redundancy fire containm...

Page 5: ...C Electronics Germany GmbH Duesseldorf Germany Tel 0211 65 03 02 Fax 0211 65 03 490 NEC Electronics UK Ltd Milton Keynes UK Tel 01908 691 133 Fax 01908 670 290 NEC Electronics Italiana s r l Milano Italy Tel 02 66 75 41 Fax 02 66 75 42 99 NEC Electronics Germany GmbH Benelux Office Eindhoven The Netherlands Tel 040 2445845 Fax 040 2444580 NEC Electronics France S A Velizy Villacoublay France Tel 0...

Page 6: ...Addition of Caution in CHAPTER 18 FLASH MEMORY p 444 Addition of Table 19 5 Acknowledge Signal Output Condition of Control Field p 452 Addition of description 19 1 8 Bit format p 457 Modification of Caution in 19 3 2 1 a Communication enable flag ENIEBUS p 463 Addition of Note in Figure 19 18 Timing of INTIE2 Interrupt Generation in Locked State for 4 and 5 p 464 Addition of Remark in 19 3 2 6 IEB...

Page 7: ...only Data type Register set Instruction format and instruction set Interrupt and exception Pipeline operation How to Read This Manual It is assumed that the reader of this manual has general knowledge in the fields of electrical engineering logic circuits and microcontrollers To find out the details of a register whose name is known Refer to APPENDIX A REGISTER INDEX To find out the details of a f...

Page 8: ...r of 2 address space memory capacity K kilo 2 10 1024 M mega 2 20 1024 2 G giga 2 30 1024 3 Related Documents The related documents indicated in this publication may include preliminary versions However preliminary versions are not marked as such Related documents for V850 SB1 and V850 SB2 Document Name Document No V850 Family User s Manual Architecture U10243E V850 SB1 V850 SB2 User s Manual Hard...

Page 9: ... Debugger Operation Windows TM Based U14580E SM850 Ver 2 20 or Later System Simulator Operation Windows Based U14782E SM850 Ver 2 00 or Later System Simulator External Part User Open Interface Specifications U14873E Basics U13430E Installation U13410E RX850 Ver 3 13 or Later Real Time OS Technical U13431E Fundamental U13773E Installation U13774E RX850 Pro Ver 3 13 Real Time OS Technical U13772E RD...

Page 10: ...unctions 51 2 2 Pin States 58 2 3 Description of Pin Functions 59 2 4 I O Circuit Types I O Buffer Power Supply and Connection of Unused Pins 69 2 5 I O Circuit of Pins 71 CHAPTER 3 CPU FUNCTIONS 73 3 1 Features 73 3 2 CPU Register Set 74 3 2 1 Program register set 75 3 2 2 System register set 76 3 3 Operation Modes 78 3 4 Address Space 79 3 4 1 CPU address space 79 3 4 2 Image 80 3 4 3 Wrap aroun...

Page 11: ... Data space 123 CHAPTER 5 INTERRUPT EXCEPTION PROCESSING FUNCTION 124 5 1 Outline 124 5 1 1 Features 124 5 2 Non Maskable Interrupt 127 5 2 1 Operation 128 5 2 2 Restore 130 5 2 3 NP flag 131 5 2 4 Noise eliminator of NMI pin 131 5 2 5 Edge detection function of NMI pin 132 5 3 Maskable Interrupts 133 5 3 1 Operation 133 5 3 2 Restore 135 5 3 3 Priorities of maskable interrupts 136 5 3 4 Interrupt...

Page 12: ...1 16 Bit Timer TM0 TM1 174 7 1 1 Outline 174 7 1 2 Function 174 7 1 3 Configuration 176 7 1 4 Timer 0 1 control registers 179 7 2 16 Bit Timer Operation 187 7 2 1 Operation as interval timer 16 bits 187 7 2 2 PPG output operation 189 7 2 3 Pulse width measurement 190 7 2 4 Operation as external event counter 197 7 2 5 Operation to output square wave 198 7 2 6 Operation to output one shot pulse 200...

Page 13: ...gisters 246 10 2 3 Operations 249 10 3 I 2 C Bus 252 10 3 1 Configuration 255 10 3 2 I 2 C control register 257 10 3 3 I 2 C bus mode functions 268 10 3 4 I 2 C bus definitions and control methods 269 10 3 5 I 2 C interrupt requests INTIICn 276 10 3 6 Interrupt request INTIICn generation timing and wait control 294 10 3 7 Address match detection method 295 10 3 8 Error detection 295 10 3 9 Extensi...

Page 14: ...OA5 360 12 3 2 DMA internal RAM address registers 0 to 5 DRA0 to DRA5 361 12 3 3 DMA byte count registers 0 to 5 DBC0 to DBC5 366 12 3 4 DMA start factor expansion register DMAS 366 12 3 5 DMA channel control registers 0 to 5 DCHC0 to DCHC5 367 CHAPTER 13 REAL TIME OUTPUT FUNCTION RTO 369 13 1 Function 369 13 2 Configuration 370 13 3 RTO Control Registers 371 13 4 Operation 373 13 5 Usage 374 13 6...

Page 15: ...nment 425 18 4 Communication System 425 18 5 Pin Connection 428 18 5 1 VPP pin 428 18 5 2 Serial interface pin 428 18 5 3 RESET pin 431 18 5 4 Port pin including NMI 431 18 5 5 Other signal pins 431 18 5 6 Power supply 431 18 6 Programming Method 432 18 6 1 Flash memory control 432 18 6 2 Flash memory programming mode 433 18 6 3 Selection of communication mode 434 18 6 4 Communication command 434 ...

Page 16: ...nterrupt control block 478 19 4 2 Interrupt source list 479 19 4 3 Communication error source processing list 480 19 5 Interrupt Generation Timing and Main CPU Processing 482 19 5 1 Master transmission 482 19 5 2 Master reception 484 19 5 3 Slave transmission 486 19 5 4 Slave reception 488 19 5 5 Interval of occurrence of interrupt for IEBus control 490 APPENDIX A REGISTER INDEX 494 APPENDIX B INS...

Page 17: ... 18 Internal Peripheral I O Area 88 3 19 External Memory Area When Expanded to 64 K 256 K or 1 MB 89 3 20 External Memory Area When Expanded to 4 MB 90 3 21 Memory Expansion Mode Register MM Format 91 3 22 Memory Address Output Mode Register MAM Format 92 3 23 Application of Wrap Around 93 3 24 Recommended Memory Map Flash Memory Version 94 3 25 Command Register PRCMD 105 3 26 System Status Regist...

Page 18: ...cessing 146 5 17 RETI Instruction Processing 147 5 18 EP Flag EP 148 5 19 Illegal Op Code 148 5 20 Exception Trap Processing 149 5 21 RETI Instruction Processing 150 5 22 Pipeline Operation at Interrupt Request Acknowledgement 154 5 23 Key Return Mode Register KRM 156 5 24 Key Return Block Diagram 157 6 1 Clock Generator 159 6 2 Format of Processor Clock Control Register PCC 160 6 3 Format of Powe...

Page 19: ... Counter Mode 197 7 24 Configuration of External Event Counter 198 7 25 Timing of External Event Counter Operation with Rising Edge Specified 198 7 26 Control Register Settings in Square Wave Output Mode 199 7 27 Timing of Square Wave Output Operation 200 7 28 Control Register Settings for One Shot Pulse Output with Software Trigger 201 7 29 Timing of One Shot Pulse Output Operation with Software ...

Page 20: ...10 1 Block Diagram of 3 Wire Serial I O 245 10 2 Serial Operation Mode Registers 0 to 3 CSIM0 to CSIM3 247 10 3 Serial Clock Selection Registers 0 to 3 CSIS0 to CSIS3 248 10 4 CSIMn Setting Operation Stop Mode 249 10 5 CSIMn Setting 3 Wire Serial I O Mode 250 10 6 Timing of 3 Wire Serial I O Mode 251 10 7 Block Diagram of I 2 C 253 10 8 Serial Bus Configuration Example Using I 2 C Bus 254 10 9 IIC...

Page 21: ...s Serial Interface Mode 323 10 42 Error Tolerance When k 16 Including Sampling Errors 325 10 43 Format of Transmit Receive Data in Asynchronous Serial Interface 326 10 44 Timing of Asynchronous Serial Interface Transmit Completion Interrupt 328 10 45 Timing of Asynchronous Serial Interface Receive Completion Interrupt 329 10 46 Receive Error Timing 330 10 47 Block Diagram of CSI4 333 10 48 Variabl...

Page 22: ... 5 DBC0 to DBC5 366 12 8 DMA Start Factor Expansion Register DMAS 366 12 9 Format of DMA Channel Control Registers 0 to 5 DCHC0 to DCHC5 367 13 1 Block Diagram of RTO 369 13 2 Configuration of Real Time Output Buffer Registers 370 13 3 Format of Real Time Output Port Mode Register RTPM 371 13 4 Format of Real Time Output Port Control Register RTPC 372 13 5 Example of Operation Timing of RTO When E...

Page 23: ...32 Block Diagram of P70 to P77 and P80 to P83 400 14 33 Port 9 P9 401 14 34 Port 9 Mode Register PM9 402 14 35 Block Diagram of P90 to P96 403 14 36 Port 10 P10 404 14 37 Port 10 Mode Register PM10 405 14 38 Pull Up Resistor Option Register 10 PU10 406 14 39 Port 10 Function Register PF10 406 14 40 Block Diagram of P100 to P107 407 14 41 Port 11 P11 408 14 42 Port 11 Mode Register PM11 409 14 43 P...

Page 24: ...figuration of Lock Address 451 19 9 Bit Format of IEBus 452 19 10 IEBus Controller Block Diagram 453 19 11 IEBus Control Register BCR 456 19 12 IEBus Unit Address Register UAR Format 459 19 13 IEBus Slave Address Register SAR Format 459 19 14 IEBus Partner Address Register PAR Format 460 19 15 IEBus Control Data Register CDR Format 461 19 16 Interrupt Generation Timing for 1 3 and 4 462 19 17 Inte...

Page 25: ...ansmission 482 19 31 Master Reception 484 19 32 Slave Transmission 486 19 33 Slave Reception 488 19 34 Master Transmission Interval of Interrupt Occurrence 490 19 35 Master Reception Interval of Interrupt Occurrence 491 19 36 Slave Transmission Interval of Interrupt Occurrence 492 19 37 Slave Reception Interval of Interrupt Occurrence 493 ...

Page 26: ...ions 151 5 4 Description of Key Return Detection Pin 156 6 1 Operating Statuses in HALT Mode 166 6 2 Operating Statuses in IDLE Mode 168 6 3 Operating Statuses in Software STOP Mode 170 7 1 Configuration of Timers 0 and 1 176 7 2 Valid Edge of TIn0 Pin and Capture Trigger of CRn0 177 7 3 Valid Edge of TIn1 Pin and Capture Trigger of CRn0 177 7 4 TIn0 Pin Valid Edge and CRn1 Capture Trigger 178 7 5...

Page 27: ...me Output Buffer Registers Are Manipulated 371 13 3 Operation Mode and Output Trigger of Real Time Output Port 372 14 1 Pin I O Buffer Power Supplies 375 14 2 Port 0 Alternate Function Pins 376 14 3 Port 1 Alternate Function Pins 380 14 4 Port 2 Alternate Function Pins 384 14 5 Port 3 Alternate Function Pins 389 14 6 Alternate Function Pins of Ports 4 and 5 393 14 7 Port 6 Alternate Function Pins ...

Page 28: ...t 443 19 5 Acknowledge Signal Output Condition of Control Field 444 19 6 Contents of Telegraph Length Bit 445 19 7 Internal Registers of IEBus Controller 455 19 8 Reset Conditions of Flags in ISR Register 470 19 9 Interrupt Source List 479 19 10 Communication Error Source Processing List 480 B 1 Symbols in Operand Description 501 B 2 Symbols Used for Op Code 502 B 3 Symbols Used for Operation Desc...

Page 29: ... 5 V I O interface support and ROM correction For V850 SB2 based on the V850 SB1 the peripheral functions of automobile LAN IEBus Inter Equipment Bus are added In addition to high real time response characteristics and 1 clock pitch basic instructions the V850 SB1 and V850 SB2 have multiply saturation operation and bit manipulation instructions realized with a hardware multiplier for digital servo...

Page 30: ...Mask ROM 128 KB 12 KB 100 pin QFP 14 20 100 pin LQFP 14 14 µPD703035A Mask ROM µPD70F3035A None Flash memory µPD703035AY Mask ROM µPD70F3035AY Available Flash memory 256 KB 16 KB 100 pin QFP 14 20 100 pin LQFP 14 14 µPD703036A None µPD703036AY Available Mask ROM 384 KB 20 KB 100 pin QFP 14 20 µPD703037A Mask ROM µPD70F3037A None Flash memory µPD703037AY Mask ROM V850 SB2 µPD70F3037AY Available Fla...

Page 31: ... address data multiplex Address bus separate output enabled 3 V to 5 V interface enabled Bus hold function External wait function Internal memory µPD703031A 703031AY mask ROM 128 KB RAM 12 KB µPD703033A 703033AY mask ROM 256 KB RAM 16 KB µPD703030A 703030AY mask ROM 384 KB RAM 20 KB µPD703032A 703032AY mask ROM 512 KB RAM 24 KB µPD70F3033A 70F3033AY flash memory 256 KB RAM 16 KB µPD70F3032A 70F303...

Page 32: ...MA controller Internal RAM internal peripheral I O 6 channels Real time output port RTP 8 bits 1 channel or 4 bits 2 channels ROM correction Modifiable 4 points Regulator 4 0 V to 5 5 V input internal 3 3 V Key return function 4 to 8 selecting enabled falling edge fixed Clock generator During main system clock or subsystem clock operation 5 level CPU clock including slew rate and sub operations Po...

Page 33: ...QFP 14 20 100 pin plastic LQFP fine pitch 14 14 100 pin plastic QFP 14 20 100 pin plastic LQFP fine pitch 14 14 100 pin plastic QFP 14 20 100 pin plastic QFP 14 20 100 pin plastic LQFP 14 20 100 pin plastic QFP 14 20 100 pin plastic QFP 14 20 100 pin plastic LQFP fine pitch 14 14 100 pin plastic QFP 14 20 100 pin plastic LQFP fine pitch 14 14 100 pin plastic QFP 14 20 100 pin plastic QFP 14 20 100...

Page 34: ... 14 15 16 17 18 19 20 21 22 23 24 25 1 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 75 P21 SO2 P23 RXD1 SI3 P24 TXD1 SO3 EVDD EVSS P26 TI2 TO2 P27 TI3 TO3 P30 TI00 P31 TI01 P33 TI11 SO4 P34 TO0 A13 SCK4 P35 TO1 A14 P36 TI4 TO4 A15 P37 TI5 TO5 IC VPP Note 1 P100 RTP0 KR0 A5 P101 RTP1 KR1 A6 P102 RTP2 KR2 A7 P103 RTP3 KR3 A8 P104 RTP4 KR4 A9 P105 RTP5 KR5 A10 P106 RTP6 KR6...

Page 35: ...3 RXD1 SI3 P24 TXD1 SO3 EVDD EVSS P26 TI2 TO2 P27 TI3 TO3 P30 TI00 P31 TI01 P33 TI11 SO4 P34 TO0 A13 SCK4 P35 TO1 A14 P36 TI4 TO4 A15 P37 TI5 TO5 IC VPP Note 1 P100 RTP0 KR0 A5 P101 RTP1 KR1 A6 P102 RTP2 KR2 A7 P103 RTP3 KR3 A8 P104 RTP4 KR4 A9 P105 RTP5 KR5 A10 P106 RTP6 KR6 A11 P71 ANI1 P70 ANI0 AVSS AVREF AVDD P65 A21 P64 A20 P63 A19 P62 A18 P61 A17 P60 A16 P57 AD15 P56 AD14 P55 AD13 P54 AD12 P...

Page 36: ...data DSTB Data strobe SCK0 to SCK4 Serial clock EVDD Power supply for port SCL0 SCL1 Serial clock EVSS Ground for port SDA0 SDA1 Serial data HLDAK Hold acknowledge SI0 to SI4 Serial input HLDRQ Hold request SO0 to SO4 Serial output IC Internally connected TI00 TI01 TI10 INTP0 to INTP6 Interrupt request from peripherals TI11 TI2 to TI5 Timer input KR0 to KR7 Key return TO0 to TO5 Timer output LBEN ...

Page 37: ...bit timer TM2 to TM7 TO0 TO1 DMAC 6 ch Watch timer P80 to P83 P90 to P96 EVSS DSTB RD P93 R W WRH P92 LBEN WRL P90 RTPTRG A13 to A15 P34 to P36 A1 to A12 P100 to P107 P110 to P113 SO2 SI2 SDA1 Note 3 CSI2 I2 C1 Note 4 SCK2 SCL1 Note 3 SO3 TXD1 SI3 RXD1 CSI3 UART1 SCK3 ASCK1 Key return KR0 to KR7 ROM correction VPP Note 5 Regulator REGC IC Note 6 3 3 V Notes 1 µPD703031A 703031AY 128 KB mask ROM µP...

Page 38: ...ask ROM µPD70F3033A 70F3033AY 256 KB flash memory µPD703030A 703030AY 384 KB mask ROM µPD703032A 703032AY 512 KB mask ROM µPD70F3032A 70F3032AY 512 KB flash memory ROM can be accessed by the CPU in one clock cycle during instruction fetch d RAM The RAM capacity and mapping addresses vary depending on the product The RAM capacity of each product is shown below µPD703031A 703031AY 12 KB mapping star...

Page 39: ...erial interfaces UART0 UART1 clocked serial interfaces CSI0 to CSI3 and an 8 16 bit variable length serial interface CSI4 These plus the I 2 C bus interfaces I 2 C0 I 2 C1 comprise five channels Two of these channels are switchable between the UART and CSI and another two switchable between CSI and I 2 C For UART0 and UART1 data is transferred via the TXD0 TXD1 RXD0 and RXD1 pins For CSI0 to CSI3 ...

Page 40: ...ial interface Port 2 8 bit I O Serial interface timer I O Port 3 8 bit I O Timer I O external address bus serial interface Port 4 8 bit I O External address data bus Port 5 8 bit I O Port 6 6 bit I O External address bus Port 7 8 bit input A D converter analog input Port 8 4 bit input Port 9 7 bit I O External bus interface control signal I O Port 10 8 bit I O Real time output port external addres...

Page 41: ...ate output enabled 3 V to 5 V interface enabled Bus hold function External wait function Internal memory µPD703034A 703034AY mask ROM 128 KB RAM 12 KB µPD703035A 703035AY mask ROM 256 KB RAM 16 KB µPD703036A 703036AY mask ROM 384 KB RAM 20 KB µPD703037A 703037AY mask ROM 512 KB RAM 24 KB µPD70F3035A 70F3035AY flash memory 256 KB RAM 16 KB µPD70F3037A 70F3037AY flash memory 512 KB RAM 24 KB Interru...

Page 42: ...hannels Real time output port RTP 8 bits 1 channel or 4 bits 2 channels ROM correction Modifiable 4 points Regulator 4 0 V to 5 5 V input internal 3 0 V Key return function 4 to 8 selecting enabled falling edge fixed Clock generator During main system clock or subsystem clock operation 5 level CPU clock including slew rate and sub operations Power saving functions HALT IDLE STOP modes IEBus contro...

Page 43: ...3035AYGF xxx 3BA 100 pin plastic QFP 14 20 Mask ROM 256 KB µPD703036AGF xxx 3BA Note 100 pin plastic QFP 14 20 Mask ROM 384 KB µPD703036AYGF xxx 3BA Note 100 pin plastic QFP 14 20 Mask ROM 384 KB µPD703037AGF xxx 3BA 100 pin plastic QFP 14 20 Mask ROM 512 KB µPD703037AYGF xxx 3BA 100 pin plastic QFP 14 20 Mask ROM 512 KB µPD70F3035AGC 8EU 100 pin plastic LQFP fine pitch 14 14 Flash memory 256 KB µ...

Page 44: ...5 16 17 18 19 20 21 22 23 24 25 1 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 75 P21 SO2 P23 RXD1 SI3 P24 TXD1 SO3 EVDD EVSS P26 TI2 TO2 P27 TI3 TO3 P30 TI00 P31 TI01 P33 TI11 SO4 P34 TO0 A13 SCK4 P35 TO1 A14 P36 TI4 TO4 A15 P37 TI5 TO5 IC VPP Note 1 P100 RTP0 KR0 A5 P101 RTP1 KR1 A6 P102 RTP2 KR2 A7 P103 RTP3 KR3 A8 P104 RTP4 KR4 A9 IERX P105 RTP5 KR5 A10 IETX P106 RTP...

Page 45: ...1 SI3 P24 TXD1 SO3 EVDD EVSS P26 TI2 TO2 P27 TI3 TO3 P30 TI00 P31 TI01 P33 TI11 SO4 P34 TO0 A13 SCK4 P35 TO1 A14 P36 TI4 TO4 A15 P37 TI5 TO5 IC VPP Note 1 P100 RTP0 KR0 A5 P101 RTP1 KR1 A6 P102 RTP2 KR2 A7 P103 RTP3 KR3 A8 P104 RTP4 KR4 A9 IERX P105 RTP5 KR5 A10 IETX P106 RTP6 KR6 A11 P71 ANI1 P70 ANI0 AVSS AVREF AVDD P65 A21 P64 A20 P63 A19 P62 A18 P61 A17 P60 A16 P57 AD15 P56 AD14 P55 AD13 P54 A...

Page 46: ...K0 to SCK4 Serial clock EVDD Power supply for port SCL0 SCL1 Serial clock EVSS Ground for port SDA0 SDA1 Serial data HLDAK Hold acknowledge SI0 to SI4 Serial input HLDRQ Hold request SO0 to SO4 Serial output IC Internally connected TI00 TI01 TI10 IERX IEBus receive data TI11 TI2 to TI5 Timer input IETX IEBus transmit data TO0 to TO5 Timer output INTP0 to INTP6 Interrupt request from peripherals TX...

Page 47: ...r TM2 to TM7 TO0 TO1 DMAC 6 ch Watch timer P80 to P83 P90 to P96 EVSS DSTB RD P93 R W WRH P92 LBEN WRL P90 RTPTRG A13 to A15 P34 to P36 A1 to A12 P100 to P107 P110 to P113 SO2 SI2 SDA1 Note 3 CSI2 I2 C1 Note 4 SCK2 SCL1 Note 3 SO3 TXD1 SI3 RXD1 CSI3 UART1 SCK3 ASCK1 Key return KR0 to KR7 ROM correction VPP Note 6 Regulator REGC IC Note 6 3 0 V IEBus IETX IERX Notes 1 µPD703034A 703034AY 128 KB mas...

Page 48: ...ask ROM µPD70F3035A 70F3035AY 256 KB flash memory µPD703036A 703036AY 384 KB mask ROM µPD703037A 703037AY 512 KB mask ROM µPD70F3037A 70F3037AY 512 KB flash memory ROM can be accessed by the CPU in one clock cycle during instruction fetch d RAM The RAM capacity and mapping addresses vary depending on the product The RAM capacity of each product is shown below µPD703034A 703034AY 12 KB mapping star...

Page 49: ... serial interfaces UART0 UART1 clocked serial interfaces CSI0 to CSI3 and an 8 16 bit variable length serial interface CSI4 These plus the I 2 C bus interfaces I 2 C0 I 2 C1 comprise five channels Two of these channels are switchable between the UART and CSI and another two switchable between CSI and I 2 C For UART0 and UART1 data is transferred via the TXD0 TXD1 RXD0 and RXD1 pins For CSI0 to CSI...

Page 50: ...address bus serial interface Port 4 8 bit I O External address data bus Port 5 8 bit I O Port 6 6 bit I O External address bus Port 7 8 bit input A D converter analog input Port 8 4 bit input Port 9 7 bit I O External bus interface control signal I O Port 10 8 bit I O Real time output port external address bus key return input IEBus data I O Port 11 4 bit I O General purpose port Wait control exte...

Page 51: ... EVDD 5 5 V Caution The electrical specifications in the case of 3 0 V to up to 4 0 V are different from those for 4 0 V to 5 5 V Differences of pins between the V850 SB1 and V850 SB2 are shown below Table 2 2 Differences of Pins Between V850 SB1 and V850 SB2 V850 SB1 V850 SB2 Pin µPD703030A µPD703031A µPD703032A µPD703033A µPD70F3032A µPD70F3033A µPD703030AY µPD703031AY µPD703032AY µPD703033AY µP...

Page 52: ...rt Input output mode can be specified in 1 bit units INTP6 P10 SI0 SDA0 P11 SO0 P12 SCK0 SCL0 P13 SI1 RXD0 P14 SO1 TXD0 P15 I O Yes Port 1 6 bit I O port Input output mode can be specified in 1 bit units SCK1 ASCK0 P20 SI2 SDA1 P21 SO2 P22 SCK2 SCL1 P23 SI3 RXD1 P24 SO3 TXD1 P25 SCK3 ASCK1 P26 TI2 TO2 P27 I O Yes Port 2 8 bit I O port Input output mode can be specified in 1 bit units TI3 TO3 Remar...

Page 53: ...t units TI5 TO5 P40 AD0 P41 AD1 P42 AD2 P43 AD3 P44 AD4 P45 AD5 P46 AD6 P47 I O No Port 4 8 bit I O port Input output mode can be specified in 1 bit units AD7 P50 AD8 P51 AD9 P52 AD10 P53 AD11 P54 AD12 P55 AD13 P56 AD14 P57 I O No Port 5 8 bit I O port Input output mode can be specified in 1 bit units AD15 P60 A16 P61 A17 P62 A18 P63 A19 P64 A20 P65 I O No Port 6 6 bit I O port Input output mode c...

Page 54: ...W WRH P93 DSTB RD P94 ASTB P95 HLDAK P96 I O No Port 9 7 bit I O port Input output mode can be specified in 1 bit units HLDRQ P100 RTP0 A5 KR0 P101 RTP1 A6 KR1 P102 RTP2 A7 KR2 P103 RTP3 A8 KR3 P104 RTP4 A9 KR4 IERX P105 RTP5 A10 KR5 IETX P106 RTP6 A11 KR6 P107 I O Yes Port 10 8 bit I O port Input output mode can be specified in 1 bit units RTP7 A12 KR7 P110 A1 WAIT P111 A2 P112 A3 P113 I O Yes Po...

Page 55: ... strobe signal output P94 AVDD Positive power supply for A D converter and alternate function port AVREF Input Reference voltage input for A D converter AVSS Ground potential for A D converter and alternate function port BVDD Positive power supply for bus interface and alternate function port BVSS Ground potential for bus interface and alternate function port CLKOUT Output Internal system clock ou...

Page 56: ...utput Yes Real time output port P106 A11 KR6 P107 A12 KR7 RTPTRG Input Yes RTP external trigger input P06 INTP5 R W Output No External read write status output P92 WRH RXD0 P13 SI1 RXD1 Input Yes Serial receive data input for UART0 and UART1 P23 SI3 SCK0 P12 SCL0 SCK1 P15 ASCK0 SCK2 P22 SCL1 SCK3 Serial clock I O 3 wire type for CSI0 to CSI3 P25 ASCK1 SCK4 I O Yes Serial clock I O for variable len...

Page 57: ...rnal count clock input for TM5 P37 TO5 TO0 TO1 Pulse signal output for TM0 TM1 P34 A13 SCK4 P35 A14 TO2 Pulse signal output for TM2 P26 TI2 TO3 Pulse signal output for TM3 P27 TI3 TO4 Pulse signal output for TM4 P36 TI4 A15 TO5 Output Yes Pulse signal output for TM5 P37 TI5 TXD0 P14 SO1 TXD1 Output Yes Serial transmit data output for UART0 and UART1 P24 SO3 UBEN Output No Higher byte enable signal...

Page 58: ... Z Held Held Held Held Held A16 to A21 Hi Z Hi Z Hi Z Held Hi Z Held LBEN UBEN Hi Z Hi Z Hi Z Held Hi Z Held R W Hi Z Hi Z Hi Z H Hi Z H DSTB WRL WRH RD Hi Z Hi Z Hi Z H Hi Z H ASTB Hi Z Hi Z Hi Z H Hi Z H HLDRQ Operating Operating Operating HLDAK Hi Z Hi Z Hi Z Operating L Operating WAIT CLKOUT Hi Z L L Operating Note Operating Note Operating Note Note L when in clock output inhibit mode Remark H...

Page 59: ...e EGP0 and EGN0 registers a Port mode P00 to P07 can be set in 1 bit units as input or output pins according to the contents of the port 0 mode register PM0 b Control mode i NMI Non maskable Interrupt Request input This is a non maskable interrupt request signal input pin ii INTP0 to INTP6 Interrupt Request from Peripherals input These are external interrupt request input pins iii ADTRG AD Trigger...

Page 60: ... SI0 SI1 Serial Input 0 1 input These are the serial receive data input pins of CSI0 and CSI1 ii SO0 SO1 Serial Output 0 1 output These are the serial transmit data output pins of CSI0 and CSI1 iii SCK0 SCK1 Serial Clock 0 1 3 state I O These are the serial clock I O pins for CSI0 and CSI1 iv SDA0 Serial Data 0 I O This is the serial transmit receive data I O pin for I 2 C0 µPD70303xAY and 70F303w...

Page 61: ...al Output 2 3 output These are the serial transmit data output pins of CSI2 and CSI3 iii SCK2 SCK3 Serial Clock 2 3 3 state I O These are the serial clock I O pins of CSI2 and CSI3 iv SDA1 Serial Data 1 I O This is the serial transmit receive data I O pin for I 2 C1 µPD70303xAY and 70F303wAY only v SCL1 Serial Clock 1 I O This is the serial clock I O pin for I 2 C1 µPD70303xAY and 70F303wAY only v...

Page 62: ...3 to A15 Address 13 to 15 output These comprise the address bus that is used for external access These pins operate as the A13 to A15 bit address output pins within a 22 bit address The output changes in synchronization with the rising edge of the clock in the T1 state of the bus cycle When the timing sets the bus cycle as inactive the previous bus cycle s address is retained iv SI4 Serial Input 4...

Page 63: ...al expansion mode P50 to P57 can be set as AD8 to AD15 according to the contents of the memory expansion register MM i AD8 to AD15 Address Data 8 to 15 3 state I O These comprise the multiplexed address data bus that is used for external access At the address timing T1 state these pins operate as AD8 to AD15 22 bit address output pins At the data timing T2 TW T3 they operate as the higher 8 bit I ...

Page 64: ...tion faults Also do not apply voltage that is outside the range for AVSS and AVREF to pins that are being used as inputs for the A D converter If it is possible for noise above the AVREF range or below the AVSS to enter clamp these pins using a diode that has a small VF value 9 P90 to P96 Port 9 3 state I O Port 9 is a 7 bit I O port in which input and output can be specified in 1 bit units P90 to...

Page 65: ...s inactive v ASTB Address Strobe output This is an output pin for the external address bus s latch strobe signal Output becomes active low level in synchronization with the falling edge of the clock during the T1 state of the bus cycle and becomes inactive high level in synchronization with the falling edge of the clock during the T3 state of the bus cycle Output becomes inactive when the timing s...

Page 66: ...omprise a real time output port ii A5 to A12 Address 5 to 12 output These comprise the address bus that is used for external access These pins operate as A5 to A12 bit address output pins within a 22 bit address The output changes in synchronization with the rising edge of the clock in the T1 state of the bus cycle When the timing sets the bus cycle as inactive the previous bus cycle s address is ...

Page 67: ...nput is asynchronous input for a signal that has a constant low level width regardless of the operating clock s status When this signal is input a system reset is executed as the first priority ahead of all other operations In addition to being used for ordinary initialization start operations this pin can also be used to cancel a standby mode HALT IDLE or STOP mode 13 REGC Regulator Control input...

Page 68: ...ept for the alternate function ports of the bus interface 24 VDD Power Supply These are the positive power supply pins All VDD pins should be connected to a positive power source 25 VSS Ground These are the ground pins All VSS pins should be grounded 26 VPP Programming Power Supply This is the positive power supply pin used for flash memory programming mode This pin is used in the µPD70F303wA and ...

Page 69: ...SCK1 ASCK0 EVDD 10 A P20 SI2 SDA1 10 A P21 SO2 26 P22 SCK2 SCL1 P23 SI3 RXD1 10 A P24 SO3 TXD1 26 P25 SCK3 ASCK1 10 A P26 P27 TI2 TO2 TI3 TO3 EVDD 8 A P30 P31 TI00 TI01 P32 P33 TI10 SI4 TI11 SO4 P34 TO0 A13 SCK4 8 A P35 TO1 A14 5 A P36 TI4 TO4 A15 P37 TI5 TO5 EVDD 8 A Input Individually connect to EVDD or EVSS via a resistor Output Leave open P40 to P47 AD0 to AD7 P50 to P57 AD8 to AD15 P60 to P65...

Page 70: ...03 RTP0 A5 KR0 to RTP3 A8 KR3 P104 RTP4 A9 KR4 IERX P105 RTP5 A10 KR5 IETX P106 P107 RTP6 A11 KR6 RTP7 A12 KR7 EVDD 10 A P110 A1 WAIT P111 to P113 A2 to A4 EVDD 5 A Input Individually connect to EVDD or EVSS via a resistor Output Leave open AVREF Connect to AVSS via a resistor CLKOUT BVDD 4 Leave open RESET EVDD 2 X1 X2 XT1 16 Connect to VSS via a resistor XT2 16 Leave open VPP Note 1 Connect to V...

Page 71: ...that can be set for high impedance output both P ch and N ch off Type 8 A Type 5 Type 9 Pullup enable Input enable IN OUT Data Output disable N ch P ch P ch VDD VDD IN OUT Output disable N ch Data P ch VDD Pullup enable IN OUT Data Output disable N ch P ch P ch VDD VDD Output disable Input enable IN OUT Data N ch P ch VDD N ch P ch Input enable VREF threshold voltage Comparator ...

Page 72: ...Manual U13850EJ4V0UM 72 2 2 Type 10 A Type 26 Type 16 Pullup enable IN OUT Data Open drain Output disable N ch P ch P ch VDD VDD Pullup enable IN OUT Data Open drain Output disable N ch P ch P ch VDD VDD P ch XT1 XT2 Feedback cut off ...

Page 73: ...ution time V850 SB1 50 ns 20 MHz internal operation V850 SB2 79 ns 12 58 MHz internal operation Address space 16 MB linear Thirty two 32 bit general purpose registers Internal 32 bit architecture Five stage pipeline control Multiplication division instructions Saturated operation instructions One clock 32 bit shift instruction Load store instruction with long short format Four types of bit manipul...

Page 74: ...ecture Figure 3 1 CPU Register Set r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 r20 r21 r22 r23 r24 r25 r26 r27 r28 r29 r30 r31 Zero Register Reserved for Address Register Stack Pointer SP Global Pointer GP Text Pointer TP Element Pointer EP Link Pointer LP PC Program Counter PSW Program Status Word ECR Exception Cause Register FEPC FEPSW Fatal Error PC Fatal Error PSW EIP...

Page 75: ... r0 Zero register Always holds 0 r1 Assembler reserved register Working register for generating 32 bit immediate r2 Address data variable register when r2 is not used by the real time OS r3 Stack pointer Used to generate stack frame when function is called r4 Global pointer Used to access global variable in data area r5 Text pointer Register to indicate the start of the text area Note r6 to r29 Ad...

Page 76: ...interrupt or NMI occurs this register will contain information referencing the interrupt source The higher 16 bits of this register are called FECC to which exception code of NMI is set The lower 16 bits are called EICC to which exception code of exception interrupt is set 5 PSW Program status word A program status word is a collection of flags that indicate program status instruction execution re...

Page 77: ...ests can be accepted when this bit is sets ID Indicates that accepting external interrupt request is disabled SAT This flag is set if the result of executing saturated operation instruction overflows If overflow does not occur value of previous operation is held CY This flag is set if carry or borrow occurs as result of operation If carry or borrow does not occur it is reset OV This flag is set if...

Page 78: ...ruction processing written in the internal ROM is started However external expansion mode that connects external device to external memory area is enabled by setting in the memory expansion mode register MM by instruction 2 Flash memory programming mode This mode is provided only in the µPD70F3032A 70F3032AY 70F3033A 70F3033AY 70F3035A 70F3035AY 70F3037A 70F3037AY The internal flash memory is prog...

Page 79: ... support up to 4 GB of linear address space data space during operand addressing data access When referencing instruction addresses linear address space program space of up to 16 MB is supported The CPU address space is shown below Figure 3 5 CPU Address Space FFFFFFFFH CPU address space Program area 16 MB linear Data area 4 GB linear 01000000H 00FFFFFFH 00000000H ...

Page 80: ...use the higher 8 bits of a 32 bit CPU address are ignored and the CPU address is only seen as a 24 bit external physical address the physical location xx000000H is equally referenced by multiple address values 00000000H 01000000H 02000000H FE000000H FF000000H Figure 3 6 Image on Address Space FFFFFFFFH FF000000H FEFFFFFFH Image CPU address space Image Image Image Image FE000000H FDFFFFFFH 02000000...

Page 81: ...sses Caution No instruction can be fetched from the 4 KB area of 00FFF000H to 00FFFFFFH because this area is defined as peripheral I O area Therefore do not execute any branch operation instructions in which the destination address will reside in any part of this area Figure 3 7 Program Space 00FFFFFEH 00FFFFFFH 00000000H 00000001H Program space Program space direction direction 2 Data space The r...

Page 82: ...Map xxFFFFFFH Internal peripheral I O area Internal RAM area Reserved On chip flash memory ROM area Internal peripheral I O area Internal RAM area External memory area On chip flash memory ROM area Single chip mode Single chip mode external expansion mode 16 MB 1 MB 4 KB xxFFF000H xxFFEFFFH xx100000H xx0FFFFFH xx000000H xxFF8000H xxFF7FFFH 28 KB ...

Page 83: ...bited area Figure 3 10 Internal ROM Area 128 KB x x 0 F F F F F H x x 0 2 0 0 0 0 H x x 0 1 F F F F H x x 0 0 0 0 0 0 H Access prohibited area Internal ROM b V850 SB1 µ µ µ µPD703033A 703033AY 70F3033A 70F3033AY V850 SB2 µ µ µ µPD703035A 703035AY 70F3035A 70F3035AY 256 KB are available for the addresses xx000000H to xx03FFFFH Addresses xx040000H to xx0FFFFFH are an access prohibited area Figure 3 ...

Page 84: ... F F H x x 0 6 0 0 0 0 H x x 0 5 F F F F H x x 0 0 0 0 0 0 H Access prohibited area Internal ROM b V850 SB1 µ µ µ µPD703032A 703032AY 70F3032A 70F3032AY V850 SB2 µ µ µ µPD703037A 703037AY 70F3037A 70F3037AY 512 KB are available for the addresses xx000000H to xx07FFFFH Addresses xx080000H to xx0FFFFFH are an access prohibited area Figure 3 13 Internal ROM Flash Memory Area 512 KB x x 0 F F F F F H ...

Page 85: ...ption Source 00000000H RESET 000001D0H INTTM6 00000010H NMI 000001E0H INTTM7 00000020H INTWDT 000001F0H INTIIC0 Note INTCSI0 00000040H TRAP0n n 0 to F 00000200H INTSER0 00000050H TRAP1n n 0 to F 00000210H INTSR0 INTCSI1 00000060H ILGOP 00000220H INTST0 00000080H INTWDTM 00000230H INTCSI2 00000090H INTP0 00000240H INTIIC1 Note 000000A0H INTP1 00000250H INTSER1 000000B0H INTP2 00000260H INTSR1 INTCS...

Page 86: ...d area Figure 3 14 Internal RAM Area 12 KB x x F F E F F F H x x F F C 0 0 0 H x x F F B F F F H x x F F 8 0 0 0 H Access prohibited area Internal RAM b V850 SB1 µ µ µ µPD703033A 703033AY 70F3033A 70F3033AY V850 SB2 µ µ µ µPD703035A 703035AY 70F3035A 70F3035AY 16 KB are available for the addresses xxFFB000H to xxFFEFFFH Addresses xxFF8000H to xxFFAFFFH are an access prohibited area Figure 3 15 Int...

Page 87: ...B x x F F E F F F H x x F F A 0 0 0 H x x F F 9 F F F H x x F F 8 0 0 0 H Access prohibited area Internal RAM b V850 SB1 µ µ µ µPD703032A 703032AY 70F3032A 70F3032AY V850 SB2 µ µ µ µPD703037A 703037AY 70F3037A 70F3037AY 24 KB are available for the addresses xxFF9000H to xxFFEFFFH Addresses xxFF8000H to xxFF8FFFH are an access prohibited area Figure 3 17 Internal RAM Area 24 KB x x F F E F F F H x ...

Page 88: ...n the peripheral I O area is referenced accessed in byte units the register at the next lowest even address 2n will be accessed 2 If a register that can be accessed in byte units is accessed in half word units the higher 8 bits become undefined if the access is a read operation If a write access is made only the data in the lower 8 bits is written to the register 3 If a register with n address tha...

Page 89: ...ted when the external expansion mode is specified In the area of other than the physical external memory the image of the physical external memory can be seen The internal RAM area and internal peripheral I O area are not subject to external memory access Figure 3 19 External Memory Area When Expanded to 64 K 256 K or 1 MB xxFFFFFFH xx000000H Physical external memory xFFFFH 00000H Internal periphe...

Page 90: ... register MM The address bus A1 to A15 is set to multiplexed output with data bus D1 to D15 though separate output is also available by setting the memory address output mode register MAM see the User s Manual of relevant in circuit emulator about debugging when using the separate bus Caution Because the A1 pin and WAIT pin are alternate function pins the wait function by the WAIT pin cannot be us...

Page 91: ...er bits 4 to 7 are fixed to 0 Figure 3 21 Memory Expansion Mode Register MM Format After reset 00H R W Address FFFFF04CH Symbol 7 6 5 4 3 2 1 0 MM 0 0 0 0 MM3 MM2 MM1 MM0 MM3 P95 and P96 operation modes 0 Port mode 1 External expansion mode HLDAK P95 HLDRQ P96 Note MM2 MM1 MM0 Address space Port 4 Port 5 Port 6 Port 9 0 0 0 Port mode 0 1 1 64 KB AD0 to AD8 to LBEN expansion mode AD7 AD15 UBEN 1 0 ...

Page 92: ...s output mode register MAM an in circuit emulator is not available Also setting the MAM register by software cannot switch to the separate bus For details refer to the relevant User s Manual of in circuit emulator Remark For details of the operation of each port see 2 3 Description of Pin Functions The separate path outputs are output from P34 to P36 P100 to P107 and P110 to P113 The procedure for...

Page 93: ...s are valid Therefore a continuous 16 MB space starting from address 00000000H unconditionally corresponds to the memory map of the program space 2 Data space For the efficient use of resources to be performed through the wrap around feature of the data space the continuous 8 MB address spaces 00000000H to 007FFFFFH and FF800000H to FFFFFFFFH of the 4 GB CPU are used as the data space With the V85...

Page 94: ... External memory External memory Internal ROM xxFFFFFFH xxFFF400H xxFFF3FFH xxFFF000H xxFFEFFFH xxFFB000H xxFFAFFFH xxFF8000H xxFF7FFFH xx100000H xx0FFFFFH xx040000H xx03FFFFH xx800000H xx7FFFFFH xx000000H FFFFF000H FFFFEFFFH FFFF8000H FFFF7FFFH FF800000H FF7FFFFFH 01000000H 00FFFFFFH 00FFF000H 00FFEFFFH 00FF8000H 00FF7FFFH 00800000H 007FFFFFH 00100000H 000FFFFFH 00040000H 0003FFFFH Note This area...

Page 95: ...ction registers 0 1 IICCL0 IICCL1 None Available None Available Slave address registers 0 1 SVA0 SVA1 None Available None Available IIC shift registers 0 1 IIC0 IIC1 None Available None Available IIC function expansion registers 0 1 IICX0 IICX1 None Available None Available IIC clock expansion registers 0 1 IICCE0 IICCE1 None Available None Available Interrupt control register IEBIC1 IEBIC2 None A...

Page 96: ...er PM6 3FH FFFFF032H Port 9 mode register PM9 7FH FFFFF034H Port 10 mode register PM10 FFH FFFFF036H Port 11 mode register PM11 1FH FFFFF040H Port alternate function control register PAC FFFFF04CH Memory expansion mode register MM 00H FFFFF060H Data wait control register DWC FFFFH FFFFF062H Bus cycle control register BCC AAAAH FFFFF064H System control register SYC R W FFFFF068H Memory address outp...

Page 97: ...IC5 FFFFF10EH Interrupt control register PIC6 FFFFF118H Interrupt control register WTNIIC FFFFF11AH Interrupt control register TMIC00 FFFFF11CH Interrupt control register TMIC01 FFFFF11EH Interrupt control register TMIC10 FFFFF120H Interrupt control register TMIC11 FFFFF122H Interrupt control register TMIC2 FFFFF124H Interrupt control register TMIC3 FFFFF126H Interrupt control register TMIC4 FFFFF...

Page 98: ...ss register 0 DRA0 FFFFF184H DMA byte count register 0 DBC0 Undefined FFFFF186H DMA channel control register 0 DCHC0 00H FFFFF190H DMA peripheral I O address register 1 DIOA1 FFFFF192H DMA internal RAM address register 1 DRA1 FFFFF194H DMA byte count register 1 DBC1 Undefined FFFFF196H DMA channel control register 1 DCHC1 00H FFFFF1A0H DMA peripheral I O address register 2 DIOA2 FFFFF1A2H DMA inte...

Page 99: ...ster 10 PRM10 FFFFF218H 16 bit timer mode control register 1 TMC1 FFFFF21AH Capture compare control register 1 CRC1 FFFFF21CH Timer output control register 1 TOC1 FFFFF21EH Prescaler mode register 11 PRM11 R W 00H FFFFF240H 8 bit counter 2 TM2 R FFFFF242H 8 bit compare register 2 CR20 FFFFF244H Timer clock selection register 20 TCL20 00H FFFFF246H 8 bit timer mode control register 2 TMC2 R W 04H F...

Page 100: ...de connection only TM67 R FFFFF28CH 16 bit compare register 67 during cascade connection only CR67 0000H FFFFF28EH Timer clock selection register 61 TCL61 R W FFFFF290H 8 bit counter 7 TM7 R FFFFF292H 8 bit compare register 7 CR70 FFFFF294H Timer clock selection register 70 TCL70 00H FFFFF296H 8 bit timer mode control register 7 TMC7 04H FFFFF29EH Timer clock selection register 71 TCL71 FFFFF2A0H ...

Page 101: ... control register 1 BRGC1 R W 00H FFFFF316H Transmission shift register 1 TXS1 W FFFFF318H Reception buffer register 1 RXB1 R FFH FFFFF31EH Baud rate generator mode control register 10 BRGMC10 FFFFF320H Baud rate generator mode control register 01 BRGMC01 FFFFF322H Baud rate generator mode control register 11 BRGMC11 FFFFF340H IIC control register 0 Note IICC0 R W FFFFF342H IIC state register 0 No...

Page 102: ... FFFFF3C0H A D converter mode register 1 ADM1 FFFFF3C2H Analog input channel specification register ADS R W FFFFF3C4H A D conversion result register ADCR 0000H FFFFF3C6H A D conversion result register H higher 8 bits ADCRH R FFFFF3C8H A D converter mode register 2 ADM2 FFFFF3D0H Key return mode register KRM FFFFF3D4H Noise elimination control register NCC FFFFF3E0H IEBus control register V850 SB2 ...

Page 103: ...T SST instruction Bit manipulation instruction SET1 CLR1 NOT1 instruction 5 Return the PSW NP bit to 0 interrupt disable canceled 6 Insert the NOP instructions 2 or 5 instructions 7 If necessary enable DMA operation No special sequence is required when reading the specific registers Cautions 1 If an interrupt request or a DMA request is accepted between the time PRCMD is generated 3 and the specif...

Page 104: ...ollowing cancellation of STOP IDLE mode rX Value to be written to PSW rY Value to be written back to PSW rD Value to be set to PSC When saving the value of PSW the value of PSW prior to setting the NP bit must be transferred to the rY register Cautions 2 The instructions 5 interrupt disable cancel 6 NOP instruction following the store instruction for the PSC register for setting the software STOP ...

Page 105: ...llocated with status flags showing the operating state of the entire system This register can be read written in 8 or 1 bit units Figure 3 26 System Status Register SYS After reset 00H R W Address FFFFF078H Symbol 7 6 5 4 3 2 1 0 SYS 0 0 0 PRERR 0 0 0 0 PRERR Detection of protection error 0 Protection error does not occur 1 Protection error occurs Operation conditions of PRERR flag are shown as fo...

Page 106: ...ontrol Pins External Bus Interface Function Corresponding Port pins Address data bus AD0 to AD7 Port 4 P40 to P47 Address data bus AD8 to AD15 Port 5 P50 to P57 Address bus A1 to A4 Port 11 P110 to P113 Address bus A5 to A12 Port 10 P100 to P107 Address bus A13 to A15 Port 3 P34 to P36 Address bus A16 to A21 Port 6 P60 to P65 Read write control LBEN UBEN R W DSTB WRL WRH RD Port 9 P90 to P93 Addre...

Page 107: ...4 3 2 1 0 SYC 0 0 0 0 0 0 0 BIC BIC Bus interface control 0 DSTB R W LBEN UBEN signal outputs 1 RD WRL WRH UBEN signal outputs 4 3 Bus Access 4 3 1 Number of access clocks The number of basic clocks necessary for accessing each resource is as follows Table 4 2 Number of Access Clocks Peripheral I O bus width Bus Cycle Type Internal ROM 32 Bits Internal RAM 32 Bits Peripheral I O 16 Bits External M...

Page 108: ... data External data bus a Access to even address 0 7 0 7 8 15 Byte data External data bus b Access to odd address 2 Halfword access 16 bits In halfword access to external memory data is dealt with as it is because the data bus is fixed to 16 bits Figure 4 3 Halfword Access 16 Bits 0 0 15 15 Halfword data External data bus 3 Word access 32 bits In word access to external memory lower halfword is ac...

Page 109: ...Memory Block Block 15 Block 14 Block 13 Block 12 Block 11 Block 10 Block 9 Block 8 Block 7 Block 6 Block 5 Block 4 Block 3 Block 2 Block 1 Block 0 Internal peripheral I O area Internal RAM area External memory area FFFFFFH F00000H EFFFFFH E00000H DFFFFFH D00000H CFFFFFH C00000H BFFFFFH B00000H AFFFFFH A00000H 9FFFFFH 900000H 8FFFFFH 800000H 7FFFFFH 700000H 6FFFFFH 600000H 5FFFFFH 500000H 4FFFFFH 4...

Page 110: ...ess FFFFF060H Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DWC Number of wait states to be inserted 0 0 0 0 1 1 1 0 2 1 1 3 n Blocks into which wait states are inserted 0 Blocks 0 1 1 Blocks 2 3 2 Blocks 4 5 3 Blocks 6 7 4 Blocks 8 9 5 Blocks 10 11 6 Blocks 12 13 7 Blocks 14 15 Block 0 is reserved for the internal ROM area It is not subject to programmable wait control regardless of the setting of...

Page 111: ...d WAIT pin are alternate function pins the wait function by the WAIT pin cannot be used when using a separate bus programmable wait can be used however Similarly a separate bus cannot be used when the wait function by the WAIT pin is being used 4 5 3 Relationship between programmable wait and external wait A wait cycle is inserted as a result of an OR operation between the wait cycle specified by ...

Page 112: ... blocks 1 Bus cycle control register BCC This register can be read written in 16 bit units Figure 4 9 Bus Cycle Control Register BCC After reset AAAAH R W Address FFFFF062H Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BCC Idle state insert specification 0 Not inserted 1 Inserted n Blocks into which idle state is inserted 0 Blocks 0 1 1 Blocks 2 3 2 Blocks 4 5 3 Blocks 6 7 4 Blocks 8 9 5 Blocks 10 ...

Page 113: ... inactive high indicating that the request for the bus is cleared these pins are driven again During bus hold period the internal operation continues until the next external memory access The bus hold status can be recognized by that the HLDAK pin becomes active low This feature can be used to design a system where two or more bus masters exist such as when multi processor configuration is used an...

Page 114: ...LDAK 1 8 Clears bus cycle start request pending 9 Start of bus cycle Nomal status Bus hold status Normal status 4 7 3 Operation in power save mode In the STOP or IDLE mode the system clock is stopped Consequently the bus hold status is not set even if the HLDRQ pin becomes active In the HALT mode the HLDAK pin immediately becomes active when the HLDRQ pin becomes active and the bus hold status is ...

Page 115: ...signals Set these modes by using the BIC bit of the system control register SYC see Figure 4 1 Figure 4 11 Memory Read 1 4 a 0 wait T1 T2 T3 CLKOUT output A16 to A21 output AD0 to AD15 input output Address Data Address ASTB output R W output DSTB RD output UBEN LBEN output WAIT input WRH WRL output H A1 to A15 output Address Remarks 1 indicates the sampling timing when the number of programmable w...

Page 116: ...put A16 to A21 output AD0 to AD15 input output Address Address ASTB output R W output DSTB RD output UBEN LBEN output WAIT input WRH WRL output T3 Data H A1 to A15 output Address Remarks 1 indicates the sampling timing when the number of programmable waits is set to 0 2 The broken line indicates the high impedance state ...

Page 117: ...T output A1 to A15 output AD0 to AD15 input output Address Address ASTB output R W output DSTB RD output UBEN LBEN output WAIT input WRH WRL output H TI Data A16 to A21 output Address Remarks 1 indicates the sampling timing when the number of programmable waits is set to 0 2 The broken line indicates the high impedance state ...

Page 118: ... output A1 to A15 output AD0 to AD15 input output Address Address ASTB output R W output DSTB RD output UBEN LBEN output WAIT input WRH WRL output T3 Data TI H A16 to A21 output Address Remarks 1 indicates the sampling timing when the number of programmable waits is set to 0 2 The broken line indicates the high impedance state ...

Page 119: ...output R W output DSTB output UBEN LBEN output WAIT input RD output WRH WRL output H A1 to A15 output Address Note AD0 to AD7 output invalid data when odd address byte data is accessed AD8 to AD15 output invalid data when even address byte data is accessed Remarks 1 indicates the sampling timing when the number of programmable waits is set to 0 2 The broken line indicates the high impedance state ...

Page 120: ...STB output UBEN LBEN output WAIT input RD output WRH WRL output T3 DataNote Address H A1 to A15 output Address Note AD0 to AD7 output invalid data when odd address byte data is accessed AD8 to AD15 output invalid data when even address byte data is accessed Remarks 1 indicates the sampling timing when the number of programmable waits is set to 0 2 The broken line indicates the high impedance state...

Page 121: ...ss Address Data Address ASTB output Undefined Address Note 1 Note 2 Notes 1 If HLDRQ signal is inactive high level at this sampling timing bus hold state is not entered 2 If transferred to bus hold status after a write cycle high level may be output momentarily from the R W pin immediately before HLDAK signal changes from high level to low level Remarks 1 indicates the sampling timing when the num...

Page 122: ... access instruction fetch branch and instruction fetch continuous in that order The instruction fetch cycle may be inserted in between the read access and write access in read modify write access No instruction fetch cycle or bus hold is inserted between the lower half word access and higher half word access of word access operations Table 4 3 Bus Priority External Bus Cycle Priority Bus hold 1 Op...

Page 123: ...mory 2 A prefetch operation straddling over the on chip peripheral I O area invalid fetch does not take place if a branch instruction exists at the upper limit address of the internal RAM area 4 10 2 Data space Only the address aligned at the half word boundary when the least significant bit of the address is 0 word boundary when the lowest 2 bits of the address are 0 boundary is accessed by data ...

Page 124: ... exception or by generation of an exception event fetching of an illegal op code 5 1 1 Features Interrupts Non maskable interrupts 2 sources Maskable interrupts the number of maskable interrupt sources differs depending on the product V850 SB1 µPD703030A 703031A 703032A 703033A 70F3032A 70F3033A 37 sources µPD703030AY 703031AY 703032AY 703033AY 70F3032AY 70F3033AY 38 sources V850 SB2 µPD703034A 70...

Page 125: ...PIC4 6 INTP5 INTP5 pin Pin 00E0H 000000E0H nextPC PIC5 7 INTP6 INTP6 pin Pin 00F0H 000000F0H nextPC PIC6 8 INTWTNI Watch timer prescaler WT 0140H 00000140H nextPC WTNIIC 9 INTTM00 INTTM00 TM0 0150H 00000150H nextPC TMIC00 10 INTTM01 INTTM01 TM0 0160H 00000160H nextPC TMIC01 11 INTTM10 INTTM10 TM1 0170H 00000170H nextPC TMIC10 12 INTTM11 INTTM11 TM1 0180H 00000180H nextPC TMIC11 13 INTTM2 TM2 compa...

Page 126: ...MA2 transfer end DMA2 02E0H 000002E0H nextPC DMAIC2 35 INTDMA3 DMA3 transfer end DMA3 02F0H 000002F0H nextPC DMAIC3 36 INTDMA4 DMA4 transfer end DMA4 0300H 00000300H nextPC DMAIC4 37 INTDMA5 DMA5 transfer end DMA5 0310H 00000310H nextPC DMAIC5 38 INTWTN Watch timer OVF WT 0320H 00000320H nextPC WTNIC Maskable Interrupt 39 INTKR Key return interrupt KR 0330H 00000330H nextPC KRIC Notes 1 Available ...

Page 127: ...s the non maskable interrupt INTWDT only in the state that the WDTM4 bit of the watchdog timer mode register WDTM is set to 1 While the service routine of the non maskable interrupt is being executed PSW NP 1 the acknowledgement of another non maskable interrupt request is kept pending The pending NMI is acknowledged after the original service routine of the non maskable interrupt under execution ...

Page 128: ... exception code 0010H to the higher half word FECC of ECR 4 Sets the NP and ID bits of PSW and clears the EP bit 5 Loads the handler address 00000010H 00000020H of the non maskable interrupt routine to the PC and transfers control Figure 5 1 Non Maskable Interrupt Servicing NMI input Non maskable interrupt request Interrupt servicing Interrupt request pending FEPC FEPSW ECR FECC PSW NP PSW EP PSW ...

Page 129: ...equest NMI request PSW NP 1 NMI request pending because PSW NP 1 Pending NMI request processed b If a new NMI request is generated twice while an NMI service routine is executing Main routine NMI request NMI request Held pending because NMI service program is being processed Held pending because NMI service program is being processed NMI request Only one NMI request is acknowledged even though two...

Page 130: ... of PSW is 1 2 Transfers control back to the address of the restored PC and PSW How the RETI instruction is processed is shown below Figure 5 3 RETI Instruction Processing PSW EP RETI instruction PC PSW EIPC EIPSW PSW NP Original processing restored PC PSW FEPC FEPSW 1 1 0 0 Caution When the PSW EP bit and PSW NP bit are changed by the LDSR instruction during the non maskable interrupt service in ...

Page 131: ... 31 8 7 6 5 4 3 2 1 0 PSW 0 NP EP ID SAT CY OV S Z NP NMI servicing state 0 No NMI interrupt servicing 1 NMI interrupt currently servicing 5 2 4 Noise eliminator of NMI pin NMI pin noise is eliminated by the noise eliminator with analog delay Therefore a signal input to the NMI pin is not detected as an edge unless it maintains its input level for a certain period The edge is detected after a cert...

Page 132: ... is specified by using the EGP0 and EGN0 registers When using P00 as an output port set the NMI valid edge to detects neither rising nor falling edge Figure 5 5 Rising Edge Specification Register 0 EGP0 Format After reset 00H R W Address FFFFF0C0H Symbol 7 6 5 4 3 2 1 0 EGP0 EGP07 EGP06 EGP05 EGP04 EGP03 EGP02 EGP01 EGP00 EGP0n Rising edge valid control 0 No interrupt request signal occurs at the ...

Page 133: ...ty interrupts with the same priority level cannot be nested To use multiple interrupts it is necessary to save EIPC and EIPSW to memory or a register before executing the EI instruction and restore EIPC and EIPSW to the original values by executing the DI instruction before the RETI instruction When the WDTM4 bit of the watchdog timer mode register WDTM is set to 0 the watchdog timer overflow inte...

Page 134: ... accepted CPU processing Mask Yes No PSW ID 0 Priority higher than that of interrupt currently serviced Interrupt request pending PSW NP PSW ID Interrupt request pending No No No No 1 0 1 0 INT input Yes Yes Yes Yes Priority higher than that of other interrupt request Highest default priority of interrupt requests with the same priority Interrupt enable mode Restored PC PSW Exception code 0 1 Hand...

Page 135: ...SW is 0 2 Transfers control to the address of the restored PC and PSW The processing of the RETI instruction is shown below Figure 5 8 RETI Instruction Processing RETI instruction Restores original processing PC PSW EIPC EIPSW PSW EP 1 0 1 0 PC PSW FEPC FEPSW PSW NP Caution When the PSW EP bit and the PSW NP bit are changed by the LDSR instruction during the maskable interrupt service in order to ...

Page 136: ...ion bit xxPRn When two or more interrupts having the same priority level specified by xxPRn are generated at the same time interrupts are serviced in order depending on the priority level allocated to each interrupt request types default priority level be forehand For more information refer to Table 5 1 The programmable priority control customizes interrupt requests into eight levels by setting th...

Page 137: ...s held pending even if interrupts are enabled because its priority is the same as that of g Interrupt request f is held pending even if interrupts are enabled because its priority is lower than that of e Interrupt request b is acknowledged because the priority of b is higher than that of a and interrupts are enabled Although the priority of interrupt request d is higher than that of c d is held pe...

Page 138: ...Servicing of p Servicing of q Servicing of r EI If levels 3 to 0 are acknowledged Interrupt request j is held pending because its priority is lower than that of i k that occurs after j is acknowledged because it has the higher priority Interrupt requests m and n are held pending because servicing of l is performed in the interrupt disabled status Pending interrupt requests are acknowledged after s...

Page 139: ...pt control register can be read written in 8 or 1 bit units Caution If the following three conditions conflict interrupt servicing is executed twice However when DMA is not used interrupt servicing is not executed twice Execution of a bit manipulation instruction corresponding to the interrupt request flag xxIFn An interrupt via hardware of the same interrupt control register xxICn as the interrup...

Page 140: ...rupt mask flag 0 Enables interrupt servicing 1 Disables interrupt servicing pending xxPRn2 xxPRn1 xxPRn0 Interrupt priority specification bit 0 0 0 Specifies level 0 highest 0 0 1 Specifies level 1 0 1 0 Specifies level 2 0 1 1 Specifies level 3 1 0 0 Specifies level 4 1 0 1 Specifies level 5 1 1 0 Specifies level 6 1 1 1 Specifies level 7 lowest Note Automatically reset by hardware when interrupt...

Page 141: ...2 TMPR61 TMPR60 FFFFF12CH TMIC7 TMIF7 TMMK7 0 0 0 TMPR72 TMPR71 TMPR70 FFFFF12EH CSIC0 CSIF0 CSMK0 0 0 0 CSPR02 CSPR01 CSPR00 FFFFF130H SERIC0 SERIF0 SERMK0 0 0 0 SERPR02 SERPR01 SERPR00 FFFFF132H CSIC1 CSIF1 CSMK1 0 0 0 CSPR12 CSPR11 CSPR10 FFFFF134H STIC0 STIF0 STMK0 0 0 0 STPR02 STPR01 STPR00 FFFFF136H CSIC2 CSIF2 CSMK2 0 0 0 CSPR22 CSPR21 CSPR20 FFFFF138H IICIC1 Note 1 IICIF1 IICMK1 0 0 0 IICP...

Page 142: ...ty n not acknowledged 1 Interrupt request with priority n acknowledged Remark n 0 to 7 priority level 5 3 6 Maskable interrupt status flag The interrupt disable status flag ID of the PSW controls the enabling and disabling of maskable interrupt requests As a status flag it also displays the current maskable interrupt acknowledgment condition Figure 5 13 Interrupt Disable Flag ID After reset 000000...

Page 143: ... noise eliminator that functions via an analog delay Therefore a signal input to each pin is not detected as an edge unless it maintains its input level for a certain period An edge is detected after a certain period has elapsed 2 Noise elimination of INTP4 and INTP5 pins INTP4 and INTP5 pins incorporate the digital noise eliminator If an input level of the INTP pin is detected with the sampling c...

Page 144: ... within these 3 clocks an interrupt request may occur Therefore be careful of the following things when using the interrupt and DMA functions When using the interrupt function after the sampling clock 3 clocks have elapsed allow the interrupt after the interrupt request flag bit 7 of PIC6 has been cleared When using the DMA function after the sampling clock 3 clocks have elapsed allow DMA by setti...

Page 145: ...egister 0 EGP0 and the validity of the falling edge is controlled by falling edge specification register 0 EGN0 Refer to Figures 5 5 and 5 6 for details of EGP0 and EGN0 After reset the valid edge of the NMI pin is set to the detects neither rising nor falling edge state Therefore the NMI pin functions as a normal port and an interrupt request cannot be acknowledged unless a valid edge is specifie...

Page 146: ...processing and transfers control to the handler routine 1 Saves the restored PC to EIPC 2 Saves the current PSW to EIPSW 3 Writes an exception code to the lower 16 bits EICC of ECR interrupt source 4 Sets the EP and ID bits of PSW 5 Loads the handler address 00000040H or 00000050H of the software exception routine in the PC and transfers control How a software exception is processed is shown below...

Page 147: ...of PSW is 1 2 Transfers control to the address of the restored PC and PSW The processing of the RETI instruction is shown below Figure 5 17 RETI Instruction Processing PSW EP RETI instruction PC PSW EIPC EIPSW PSW NP Original processing restored PC PSW FEPC FEPSW 1 1 0 0 Caution When the PSW EP bit and the PSW NP bit are changed by the LDSR instruction during the software exception process in orde...

Page 148: ... is considered as an exception trap Illegal op code exception Occurs if the sub op code field of an instruction to be executed next is not a valid op code 5 5 1 Illegal op code definition An illegal op code is defined to be a 32 bit word with bits 5 to 10 being 111111B and bits 23 to 26 being 0011B to 1111B Figure 5 19 Illegal Op Code 15 16 17 23 22 x 21 x 20 x x x x x x x x x x x x x x x 1 1 1 1 ...

Page 149: ...Manual U13850EJ4V0UM 149 How the exception trap is processed is shown below Figure 5 20 Exception Trap Processing Exception trap ILGOP occurs EIPC EIPSW ECR EICC PSW EP PSW ID PC Restored PC PSW Exception code 1 1 00000060H CPU processing Exception processing ...

Page 150: ...bit of PSW is 1 2 Transfers control to the address of the restored PC and PSW The processing of the RETI instruction is shown below Figure 5 21 RETI Instruction Processing RETI instruction Jump to PC PC PSW EIPC EIPSW PSW EP 1 0 1 0 PC PSW FEPC FEPSW PSW NP Caution When the PSW EP bit and the PSW NP bit are changed by the LDSR instruction during the exception trap process in order to restore the P...

Page 151: ...that allows the nesting of interrupts If a higher priority interrupt is generated and acknowledged it will be allowed to stop a current interrupt service routine in progress Execution of the original routine will resume once the higher priority interrupt routine is completed If an interrupt with a lower or equal priority is generated and a service routine is currently in progress the later interru...

Page 152: ...egister EI instruction enables interrupt acknowledgement DI instruction disables interrupt acknowledgement Restores saved value to EIPSW Restores saved value to EIPC RETI instruction Saves EIPC to memory or register Saves EIPSW to memory or register EI instruction enables interrupt acknowledgement TRAP instruction Illegal op code Restores saved value to EIPSW Restores saved value to EIPC RETI inst...

Page 153: ...set to 7 by the xxPRn0 to xxPRn2 bits Priorities of maskable interrupts High Level 0 Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 Low Interrupt servicing that has been suspended as a result of multiple interrupt servicing is resumed after the interrupt servicing of the higher priority has been completed and the RETI instruction has been executed A pending interrupt request is acknowledg...

Page 154: ... necessary for external interrupts except when In IDLE STOP mode External bus is accessed Two or more interrupt request non sample instructions are executed in succession Access to interrupt control register 5 8 Periods Where Interrupt Is Not Acknowledged An interrupt is acknowledged while an instruction is being executed However no interrupt will be acknowledged between interrupt non sample instr...

Page 155: ...owever the following instructions are not included IDLE STOP mode setting instructions EI and DI instructions RETI instruction LDSR instruction vs PSW register Instruction that accesses interrupt control register xxICn Example When the EI instruction processing is not valid Program example DI MK flag 0 enables interrupt requests Interrupt request occurs IF flag 1 EI JR LP1 EI instruction 7 clocks ...

Page 156: ...re 5 23 Key Return Mode Register KRM After reset 00H R W Address FFFFF3D0H 7 6 5 4 3 2 1 0 KRM KRM7 KRM6 KRM5 KRM4 0 0 0 KRM0 KRMn Key return mode control 0 Does not detect key return signal 1 Detects key return signal Caution If the key return mode register KRM is changed an interrupt request flag may be set To avoid this flag to be set change the KRM register after disabling interrupts and then ...

Page 157: ... 5 INTERRUPT EXCEPTION PROCESSING FUNCTION User s Manual U13850EJ4V0UM 157 Figure 5 24 Key Return Block Diagram INTKR Key return mode register KRM KRM7 KRM6 KRM5 KRM4 0 0 0 KRM0 KR7 KR6 KR5 KR4 KR3 KR2 KR1 KR0 ...

Page 158: ...the main oscillator is stopped by inputting a reset or executing a STOP instruction the oscillation stabilization time is secured after the stop mode is canceled This oscillation stabilization time is set via the oscillation stabilization time selection register OSTS The watchdog timer is used as the timer that counts the oscillation stabilization time 2 If the main system clock halt is released b...

Page 159: ...ock Generator fXT fXT fXX 8 fXX STOP MCK FRC Prescaler Prescaler X2 X1 XT2 XT1 IDLE Main system clock oscillator Subsystem clock oscillator IDLE control IDLE control Selector Clock supplied to watch timer etc Clock supplied to peripheral hardware HALT HALT control CPU clock fCPU CLKOUT fXX 4 fXX 2 ...

Page 160: ...K0 bits of PCC register is disabled 6 3 1 Control registers 1 Processor clock control register PCC This is a specific register It can be written to only when a specified combination of sequences is used see 3 4 9 Specific registers This register can be read written in 8 or 1 bit units Figure 6 2 Format of Processor Clock Control Register PCC After reset 03H R W Address FFFFF074H 7 6 5 4 3 2 1 0 PC...

Page 161: ...mum number of the following instructions is required before sub clock operation after the CK2 bit is set CPU clock frequency before setting sub clock frequency 2 Therefore insert the wait described above using a program 3 MCK 1 Only when the main clock is stopped b Example of sub clock operation main clock operation setup 1 MCK 0 Main clock oscillation start 2 Insert wait using a program and wait ...

Page 162: ...After reset C0H R W Address FFFFF070H 7 6 5 4 3 2 1 0 PSC DCLK1 DCLK0 0 0 0 IDLE STP 0 DCLK1 DCLK0 Specification of CLKOUT pin s operation 0 0 Output enabled 0 1 Setting prohibited 1 0 Setting prohibited 1 1 Output disabled when reset IDLE IDLE mode setting 0 Normal mode 1 IDLE mode Note 1 STP STOP mode setting 0 Normal mode 1 STOP mode Note 2 Notes 1 When IDLE mode is canceled this bit is automat...

Page 163: ... Time Selection Register OSTS After reset 04H R W Address FFFFF380H 7 6 5 4 3 2 1 0 OSTS 0 0 0 0 0 OSTS2 OSTS1 OSTS0 Selection of oscillation stabilization time fXX OSTS2 OSTS1 OSTS0 Clock 20 MHz Note 12 58 MHz 0 0 0 2 14 fxx 819 2 µs 1 3 ms 0 0 1 2 16 fXX 3 3 ms 5 2 ms 0 1 0 2 17 fXX 6 6 ms 10 4 ms 0 1 1 2 18 fXX 13 1 ms 20 8 ms 1 0 0 2 19 fXX 26 2 ms 41 6 ms Other than above Setting prohibited N...

Page 164: ...anceled there is no need for the oscillator to wait for the oscillation stabilization time so normal operation can be resumed quickly When the power saving control register PSC s IDLE bit is set to 1 the system switches to IDLE mode 3 Software STOP mode This mode stops the entire system by stopping a clock oscillator that is not for a sub clock system The sub clock continues to be supplied to keep...

Page 165: ...ing via either the main clock or sub clock The operating statuses in the HALT mode are listed in Table 6 1 2 Cancellation of HALT mode HALT mode can be canceled by an NMI request an unmasked maskable interrupt request or a RESET input a Cancellation by interrupt request HALT mode is canceled regardless of the priority level when an NMI request or an unmasked maskable interrupt request occurs Howev...

Page 166: ...opped 8 bit timer TM4 Operating Operates when fXT is selected for count clock 8 bit timer TM5 Operating Operates when fXT is selected for count clock 8 bit timer TM6 Operating Stopped 8 bit timer TM7 Operating Stopped Watch timer Operates when main clock is selected for count clock Operating Operates when fXT is selected for count clock Watchdog timer Operating interval timer only CSI0 to CSI3 Ope...

Page 167: ...ing INTP0 to INTP3 Operating INTP4 and INTP5 Operating Stopped External interrupt request INTP6 Operating Operation when sampling clock fXT is selected Key return function Operating AD0 to AD15 High impedance Note A16 to A21 LBEN UBEN Held Note high impedance when HLDAK 0 R W High level output Note high impedance when HLDAK 0 DSTB WRL WRH RD ASTB In external expansion mode HLDAK Operating Note Eve...

Page 168: ...nterrupt request or a RESET input Table 6 2 Operating Statuses in IDLE Mode 1 2 IDLE Mode Settings When Sub Clock Exists When Sub Clock Does Not Exist CPU Stopped ROM correction Stopped Clock generator Both a main clock and sub clock oscillator Clock supply to CPU and on chip peripheral functions is stopped 16 bit timer TM0 Operates when INTWTNI is selected as count clock fXT is selected for watch...

Page 169: ...xists When Sub Clock Does Not Exist External bus interface Stopped NMI Operating INTP0 to INTP3 Operating INTP4 and INTP5 Stopped External interrupt request INTP6 Operates when fXT is selected for sampling clock Stopped Key return Operating AD0 to AD15 A16 to A21 LBEN UBEN R W DSTB WRL WRH RD ASTB In external expansion mode HLDAK High impedance Item ...

Page 170: ...e interrupt an unmasked interrupt request or a RESET input When the STOP mode is canceled an oscillation stabilization time is secured Table 6 3 Operating Statuses in Software STOP Mode 1 2 STOP Mode Settings Item When Sub Clock Exists When Sub Clock Does Not Exist CPU Stopped ROM correction Stopped Clock generator Oscillation for main clock is stopped and oscillation for sub clock continues Clock...

Page 171: ...utput Operates when INTTM4 or INTTM5 has been selected when TM4 or TM5 is operating Stopped Port function Held External bus interface Stopped NMI Operating INTP0 to INTP3 Operating INTP4 and INTP5 Stopped External interrupt request INTP6 Operates when fXT is selected for the noise eliminator Stopped Key return Operating AD0 to AD15 A16 to A21 LBEN UBEN R W DSTB WRL WRH RD ASTB In external expansio...

Page 172: ...upt is input the counter watchdog timer starts counting and the count time is the length of time that must elapse for stabilization of the oscillator s clock output Oscillation stabilization time WDT count time After the specified amount of time has elapsed system clock output starts and processing branches to the interrupt handler address Figure 6 5 Oscillation Stabilization Time STOP mode is set...

Page 173: ...register is 1 during interrupt request servicing DI instruction set by software If the power save mode is released by an interrupt request with a priority the same as or lower than the interrupt request being serviced even though interrupts are enabled EI status Therefore use the V850 SB1 and V850 SB2 under the following conditions Conditions i Do not use a power save mode IDLE or STOP mode while ...

Page 174: ...nator and support of edge specifications Timer output operated by match detection 1 each TOn When using the P34 TO0 and P35 TO1 pins as TO0 and TO1 timer outputs set the value of port 3 P3 to 0 port mode output and the port 3 mode register PM3 to 0 The ORed value of the output of a port and a timer is output Remark n 0 1 7 1 2 Function TM0 and TM1 have the following functions Interval timer PPG ou...

Page 175: ...atch Match Clear 16 bit timer mode control register n TMCn TOn INTTMn1 INTTMn0 3 Timer output control register n TOCn fXX 2 Selector Selector Selector Selector PRMn2 Prescaler mode register n1 PRMn1 Noise eliminator Noise eliminator Note Count clock is set by the PRMn0 PRMn1 registers Remark n 0 1 1 Interval timer Generates an interrupt at predetermined time intervals 2 PPG output Can output the s...

Page 176: ...ontrol registers 0 1 TOC0 TOC1 Prescaler mode registers n0 n1 PRMn0 PRMn1 1 16 bit timer registers 0 1 TM0 TM1 TMn is a 16 bit read only register that counts count pulses The counter is incremented in synchronization with the rising edge of an input clock If the count value is read during operation input of the count clock is temporarily stopped and the count value at that point is read The count ...

Page 177: ...le 7 2 When the valid edge for TIn1 pin is specified as the capture trigger refer to Table 7 3 Table 7 2 Valid Edge of TIn0 Pin and Capture Trigger of CRn0 ESn01 ESn00 Valid Edge of TIn0 Pin CRn0 Capture Trigger 0 0 Falling edge Rising edge 0 1 Rising edge Falling edge 1 0 Setting prohibited Setting prohibited 1 1 Both rising and falling edges No capture operation Remark n 0 1 Table 7 3 Valid Edge...

Page 178: ...ster When the capture trigger is specified as the valid edge of TIn0 the relationship between the TIn0 valid edge and the CRn1 capture trigger is as follows Table 7 4 TIn0 Pin Valid Edge and CRn1 Capture Trigger ESn01 ESn00 TIn0 Pin Valid Edge CRn1 Capture Trigger 0 0 Falling edge Falling edge 0 1 Rising Edge Rising Edge 1 0 Setting prohibited Setting prohibited 1 1 Both rising and falling edges B...

Page 179: ...ode registers n0 n1 PRMn0 PRMn1 1 16 bit timer mode control registers 0 1 TMC0 TMC1 TMCn specifies the operation mode of the 16 bit timer and the clear mode output timing and overflow detection of 16 bit timer register n TMCn is set by an 8 1 bit memory manipulation instruction RESET input clears TMC0 and TMC1 to 00H Caution 16 bit timer register n starts operating when a value other than 0 0 oper...

Page 180: ...Mn and CRn0 or match between TMn and CRn1 0 1 1 Match between TMn and CRn0 match between TMn and CRn1 or valid edge of TIn0 1 0 0 Clears and starts at valid edge of TIn0 Match between TMn and CRn0 or match between TMn and CRn1 1 0 1 Match between TMn and CRn0 match between TMn and CRn1 or valid edge of TIn0 1 1 0 Clears and starts on match between TMn and CRn0 Match between TMn and CRn0 or match b...

Page 181: ...ters 0 1 CRC0 CRC1 After reset 00H R W Address FFFFF20AH FFFFF21AH 7 6 5 4 3 2 1 0 CRCn 0 0 0 0 0 CRCn2 CRCn1 CRCn0 n 0 1 CRCn2 Selects operation mode of CRn1 0 Operates as compare register 1 Operates as capture register CRCn1 Selects capture trigger of CRn0 0 Captured at valid edge of TIn1 1 Captured in reverse phase of valid edge of TIn0 CRCn0 Selects operation mode of CRn0 0 Operates as compare...

Page 182: ...VRn TOCn1 TOEn n 0 1 OSPTn Controls output trigger of one shot pulse by software 0 No one shot pulse trigger 1 Uses one shot pulse trigger OSPEn Controls one shot pulse output operation 0 Successive pulse output 1 One shot pulse output Note TOCn4 Controls timer output F F on coincidence between CRn1 and TMn 0 Disables reverse timer output F F 1 Enables reverse timer output F F LVSn LVRn Sets statu...

Page 183: ...ister 00 PRM00 After reset 00H R W Address FFFFF206H 7 6 5 4 3 2 1 0 PRM00 ES011 ES010 ES001 ES000 0 0 PRM01 PRM00 ES011 ES010 Selects valid edge of TI01 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both rising and falling edges ES001 ES000 Selects valid edge of TI00 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both rising and falling edges Count clock selection fXX P...

Page 184: ...fy the valid edge of TI0n to clear and start the timer and as a capture trigger 2 Before setting data to PRM0n always stop the timer operation 3 If the 16 bit timer TM0 operation is enabled by specifying the rising edge or both edges for the valid edge of the TI0n pin while the TI0n pin is high level immediately after system reset the rising edge is detected immediately after the rising edge or bo...

Page 185: ... of TI11 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both rising and falling edges ES101 ES100 Selects valid edge of TI10 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both rising and falling edges Count clock selection fXX PRM12 Note1 PRM11 PRM10 Count clock 20 MHz Note 3 12 58 MHz 0 0 0 fXX 2 100 ns 158 ns 0 0 1 fXX 4 200 ns 318 ns 0 1 0 fXX 16 800 ns 1 3 µs 0 1 1 T...

Page 186: ...fy the valid edge of TI1n to clear and start the timer and as a capture trigger 2 Before setting data to PRM1n always stop the timer operation 3 If the 16 bit timer TM1 operation is enabled by specifying the rising edge or both edges for the valid edge of the TI1n pin while the TI1n pin is high level immediately after system reset the rising edge is detected immediately after the rising edge or bo...

Page 187: ...ounting At the same time an interrupt request signal INTTMn0 is generated The count clock of the 16 bit timer event counter can be selected by bits 0 and 1 PRMn0 and PRMn1 of prescaler mode register n0 PRMn0 and by bits 0 PRMn2 of prescaler mode register n1 PRMn1 Figure 7 9 Control Register Settings When TMn Operates as Interval Timer a 16 bit timer mode control registers 0 1 TMC0 TMC1 TMCn3 TMCn2...

Page 188: ... 11 Timing of Interval Timer Operation TMn count value CRn0 0000H 0001H N N N N N N N 0000H 0001H 0000H 0001H Count start Clear Clear Interrupt acknowledgement Interrupt acknowledgement INTTMn0 TOn Interval time Interval time Interval time Count clock t Remarks 1 Interval time N 1 t N 0001H to FFFFH 2 n 0 1 TIn0 Noise eliminator 16 bit capture compare register n0 CRn0 Count clock Note Selector 16 ...

Page 189: ...utput Operation a 16 bit timer mode control registers 0 1 TMC0 TMC1 TMCn3 TMCn2 TMCn1 OVFn TMCn 0 0 0 0 1 1 0 0 Clears and starts on match between TMn and CRn0 b Capture compare control registers 0 1 CRC0 CRC1 CRCn2 CRCn1 CRCn0 CRCn 0 0 0 0 0 0 0 CRn0 as compare register CRn1 as compare register c 16 bit timer output control registers 0 1 TOC0 TOC1 OSPTn OSPEn TOCn4 LVSn LVRn TOCn1 TOEn TOCn 0 0 0...

Page 190: ... using bits 6 and 7 ESn10 and ESn11 of prescaler mode register n0 PRMn0 The rising edge falling edge or both the rising and falling edges can be selected The valid edge is detected through sampling at a count clock cycle selected by prescaler mode register n0 n1 PRMn0 PRMn1 and the capture operation is not performed until the valid level is detected two times Therefore noise with a short pulse wid...

Page 191: ... connected to ports 2 n 0 1 Figure 7 15 Timing of Pulse Width Measurement with Free Running Counter and One Capture Register with Both Edges Specified t Value loaded to CRn1 TIn0 pin input TMn count value 0000H 0001H D0 FFFFH D1 0000H D2 D3 INTTMn1 D0 OVFn D1 D0 t 10000H D1 D2 t Count clock D1 D2 D3 D3 D2 t D0 1 D1 1 Remark n 0 1 16 bit capture compare register n1 CRn1 16 bit timer register n TMn ...

Page 192: ...re specified by bits 4 and 5 ESn00 and ESn01 and bits 6 and 7 ESn10 and ESn11 of PRMn0 respectively The rising falling or both rising and falling edges can be specified The valid edge is detected through sampling at a count clock cycle selected by prescaler mode register n0 n1 PRMn0 PRMn1 and the capture operation is not performed until the valid level is detected two times Therefore noise with a ...

Page 193: ...ge Specified Count clock TMn TIn0 CRn1 INTTMn1 n 1 n n 1 n 2 n 3 n Rising edge detection Remark n 0 1 Figure 7 18 Timing of Pulse Width Measurement with Free Running Counter with Both Edges Specified t Value loaded to CRn1 D1 D0 t 10000H D1 D2 t D3 D2 t 10000H D1 D2 1 t 0000H 0001H D0 Count clock TMn count value TIn0 pin input INTTMn1 TIn1 pin input INTTMn0 OVFn Value loaded to CRn0 D0 1 D1 D1 1 F...

Page 194: ...lid edge of TIn0 is detected through sampling at a count clock cycle selected by prescaler mode register n0 n1 PRMn0 PRMn1 and the capture operation is not performed until the valid level is detected two times Therefore noise with a short pulse width can be removed Caution If the valid edge of the TIn0 pin is specified to be both the rising and falling edges capture compare register n0 CRn0 cannot...

Page 195: ...be measured by clearing 16 bit timer register n TMn once and then resuming counting after loading the count value of TMn to 16 bit capture compare register n1 CRn1 See Figure 7 22 The edge is specified by bits 4 and 5 ESn00 and ESn01 of prescaler mode register n0 PRMn0 The rising or falling edge can be specified The valid edge is detected through sampling at a count clock cycle selected by prescal...

Page 196: ... 0 0 0 1 1 1 CRn0 as capture register Captures to CRn0 at edge reverse to valid edge of TIn0 CRn1 as capture register Remark 0 1 When these bits are reset to 0 or set to 1 other functions can be used along with the pulse width measurement function For details refer to 7 1 4 Timer 0 1 control registers Figure 7 22 Timing of Pulse Width Measurement by Restarting with Rising Edge Specified t D1 1 t D...

Page 197: ...ister n0 PRMn0 The rising falling or both the rising and falling edges can be specified The valid edge is detected through sampling at a count clock cycle of fXX 2 and the capture operation is not performed until the valid level is detected two times Therefore noise with a short pulse width can be removed Figure 7 23 Control Register Settings in External Event Counter Mode a 16 bit timer mode cont...

Page 198: ...nt Counter Operation with Rising Edge Specified TIn0 pin input TMn count value CRn0 INTTMn0 0001H 0000H N 1 N N 0003H 0002H 0005H 0004H 0001H 0000H 0003H 0002H Caution Read TMn when reading the count value of the external event counter Remark n 0 1 7 2 5 Operation to output square wave TMn can be used to output a square wave with any frequency at an interval specified by the count value set in adv...

Page 199: ...0 CRCn 0 0 0 0 0 0 1 0 1 1 CRn0 as compare register c 16 bit timer output control registers 0 1 TOC0 TOC1 OSPTn OSPEn TOCn4 LVSn LVRn TOCn1 TOEn TOCn 0 0 0 0 0 1 0 1 1 1 Enables TOn output Reverses output on match between TMn and CRn0 Specifies initial value of TOn output F F Does not reverse output on match between TMn and CRn1 Disables one shot pulse output Remark 0 1 When these bits are reset t...

Page 200: ...put control register n TOCn as shown in Figure 7 28 and by setting bit 6 OSPTn of TOCn by software By setting OSPTn to 1 the 16 bit timer event counter is cleared and started and its output is asserted active at the count value N set in advance to 16 bit capture compare register n1 CRn1 After that the output is deasserted inactive at the count value M set in advance to 16 bit capture compare regis...

Page 201: ...ster CRn1 as compare register c 16 bit timer output control registers 0 1 TOC0 TOC1 OSPTn OSPEn TOCn4 LVSn LVRn TOCn1 TOEn TOCn 0 0 1 1 0 1 0 1 1 1 Enables TOn output Reverses output on match between TMn and CRn0 Specifies initial value of TOn output F F Reverses output on match between TMn and CRn1 Sets one shot pulse output mode Set to 1 for output Caution Do not set CRn0 and CRn1 to 0000H Remar...

Page 202: ...6 bit timer output control register n TOCn as shown in Figure 7 30 and by using the valid edge of the TIn0 pin as an external trigger The valid edge of the TIn0 pin is specified by bits 4 and 5 ESn00 and ESn01 of prescaler mode register n0 PRMn0 The rising falling or both the rising and falling edges can be specified When the valid edge of the TIn0 pin is detected the 16 bit timer event counter is...

Page 203: ... 0 CRn0 as compare register CRn1 as compare register c 16 bit timer output control registers 0 1 TOC0 TOC1 OSPTn OSPEn TOCn4 LVSn LVRn TOCn1 TOEn TOCn 0 0 1 1 0 1 0 1 1 1 Enables TOn output Reverses output on match between TMn and CRn0 Specifies initial value of TOn output F F Reverses output on match between TMn and CRn1 Sets one shot pulse output mode Caution Do not set CRn0 and CRn1 to 0000H Re...

Page 204: ...ified Count clock TMn count value 0000H 0001H N 1 M 2 N 2 M 1 M 1 M Value to set CRn1 N Value to set CRn0 M TIn0 pin input INTTMn1 INTTMn0 TOn pin output Sets 08H to TMCn TMn count starts 0000H N M 2 N M N M N M Caution 16 bit timer register n starts operating as soon as values other than 0 0 operation stop mode have been set to TMCn2 and TMCn3 Remark n 0 1 N M ...

Page 205: ... pulse count operation is disabled when these registers are used as event counters 3 Setting compare register during timer count operation If the value to which the current value of 16 bit capture compare register n0 CRn0 has been changed is less than the value of 16 bit timer register n TMn TMn continues counting overflows and starts counting again from 0 If the new value of CRn0 M is less than t...

Page 206: ...MCn3 of 16 bit timer mode control register n to 0 0 Set the valid edge by using bits 4 and 5 ESn00 and ESn01 of prescaler mode register n0 PRMn0 6 Re triggering one shot pulse a One shot pulse output by software When a one shot pulse is being output do not set OSPTn to 1 To output a one shot pulse again wait until the interrupt INTTMn0 which occurs on a match with CRn0 or INTTMn1 which occurs on a...

Page 207: ...16 bit capture compare registers n0 and n1 CRn0 CRn1 are used as capture registers if the read period and capture trigger input conflict the capture trigger has priority The read data of CRn0 and CRn1 is undefined b If the match timings of the write period and TMn conflict When 16 bit capture compare registers n0 and n1 CRn0 CRn1 are used as capture registers because match detection cannot be perf...

Page 208: ...riting 16 bit timer capture compare registers n0 and n1 CRn0 CRn1 if the value is close to or larger than the timer value the match interrupt request generation or clear operation may not be performed correctly b When CRn0 and CRn1 are set to compare mode When CRn0 and CRn1 are set to compare mode they do not perform a capture operation even if a capture trigger is input 12 Edge detection a When t...

Page 209: ... Mode using timer alone individual mode The timer operates as an 8 bit timer event counter It can have the following functions Interval timer External event counter Square wave output PWM output 2 Mode using the cascade connection 16 bit resolution cascade connection mode The timer operates as a 16 bit timer event counter by connecting TM2 and TM3 or TM4 and TM5 in cascade It can have the followin...

Page 210: ...n connecting in cascade Registers 8 bit compare registers 2 to 7 CR20 to CR70 16 bit compare registers 23 45 67 CR23 CR45 CR67 Only when connecting in cascade Timer outputs TO2 to TO5 Control registers Timer clock selection registers 20 to 70 and 21 to 71 TCL20 to TCL70 and TCL21 to TCL71 8 bit timer mode control registers 2 to 7 TMC2 to TMC7 8 bit compare register n CRn0 8 bit counter n TMn Match...

Page 211: ...nd CRn0 match in the clear and start mode that occurs when TMn and CRn0 match Caution When connected in cascade these registers become 00H even when TCEn in the lower timers TM2 TM4 TM6 is cleared Remark n 2 to 7 m 2 4 6 2 8 bit compare registers 2 to 7 CR20 to CR70 The value set in CRn0 is always compared to the count in 8 bit counter n TMn If the two values match an interrupt request INTTMn is g...

Page 212: ...imer n Timer clock selection registers n0 n1 TCLn0 TCLn1 8 bit timer mode control register n TMCn 1 Timer clock selection registers 20 to 71 and 21 to 71 TCL20 to TCL70 and TCL21 to TCL71 These registers set the count clock of timer n TCLn0 and TCLn1 are set by an 8 bit memory manipulation instruction RESET input clears these registers to 00H ...

Page 213: ... 0 0 1 0 fXX 4 200 ns 318 ns 0 0 1 1 fXX 8 400 ns 636 ns 0 1 0 0 fXX 16 800 ns 1 3 µs 0 1 0 1 fXX 32 1 6 µs 2 5 µs 0 1 1 0 fXX 128 6 4 µs 10 2 µs 0 1 1 1 fXX 512 25 6 µs 40 7 µs 1 0 0 0 Setting prohibited 1 0 0 1 Setting prohibited 1 0 1 0 fXX 64 3 2 µs 5 1 µs 1 0 1 1 fXX 256 12 8 µs 20 3 µs 1 1 0 0 Setting prohibited 1 1 0 1 Setting prohibited 1 1 1 0 Setting prohibited 1 1 1 1 Setting prohibited...

Page 214: ...e 0 0 1 0 fXX 4 200 ns 318 ns 0 0 1 1 fXX 8 400 ns 636 ns 0 1 0 0 fXX 16 800 ns 1 3 µs 0 1 0 1 fXX 32 1 6 µs 2 5 µs 0 1 1 0 fXX 128 6 4 µs 10 2 µs 0 1 1 1 fXT Sub clock 30 5 µs 30 5 µs 1 0 0 0 Setting prohibited 1 0 0 1 Setting prohibited 1 0 1 0 fXX 64 3 2 µs 5 1 µs 1 0 1 1 fXX 256 12 8 µs 20 3 µs 1 1 0 0 Setting prohibited 1 1 0 1 Setting prohibited 1 1 1 0 Setting prohibited 1 1 1 1 Setting pro...

Page 215: ...ibited 0 0 1 0 fXX 4 200 ns 318 ns 0 0 1 1 fXX 8 400 ns 636 ns 0 1 0 0 fXX 16 800 ns 1 3 µs 0 1 0 1 fXX 32 1 6 µs 2 5 µs 0 1 1 0 fXX 64 3 2 µs 5 1 µs 0 1 1 1 fXX 128 6 4 µs 10 2 µs 1 0 0 0 Setting prohibited 1 0 0 1 Setting prohibited 1 0 1 0 fXX 256 12 8 µs 20 3 µs 1 0 1 1 fXX 512 25 6 µs 40 7 µs 1 1 0 0 Setting prohibited 1 1 0 1 Setting prohibited 1 1 1 0 Setting prohibited 1 1 1 1 TM0 overflow...

Page 216: ...he operating mode of 8 bit counter n TMn 3 Selects the individual mode or cascade connection mode 4 Sets the state of the timer output flip flop 5 Controls the timer flip flop or selects the active level in the PWM free running mode 6 Controls timer output TMCn is set by an 8 1 bit memory manipulation instruction RESET input sets these registers to 04H although the state of hardware is initialized...

Page 217: ...0 when n 2 4 6 1 Cascade connection mode connection to lower timer LVSm LVRm Setting state of timer output flip flop 0 0 Not change 0 1 Reset timer output flip flop to 0 1 0 Set timer output flip flop to 1 1 1 Setting prohibited Other than PWM free running mode TMCn6 0 PWM free running mode TMCn6 1 TMCm1 Controls timer F F Selects active level 0 Disable inversion operation Active high 1 Enable inv...

Page 218: ...nd by bit 0 TCLn3 in timer clock selection register n1 TCLn1 n 2 to 7 Setting method 1 Set each register TCLn0 TCLn1 Selects the count clock CRn0 Compare value TMCn Selects the clear and start mode when TMn and CRn0 match TMCn 0000xxx0B x is don t care 2 When TCEn 1 is set counting starts 3 When the values of TMn and CRn0 match INTTMn is generated TMn is cleared to 00H 4 Then INTTMn is repeatedly ...

Page 219: ...Timer Operation 2 3 When CRn0 00H Remark n 2 to 7 When CRn0 FFH 01H FEH FFH 00H FEH FFH 00H FFH FFH FFH Count clock TMn CRn0 TCEn INTTMn TOn Interrupt acknowledgement Interval time t Interrupt acknowledgement Remark n 2 to 7 Count clock CRn0 TCEn INTTMn TOn TMn 00H 00H 00H 00H 00H Interval time t ...

Page 220: ...r Operation 3 3 Operated by CRn0 transition M N Remark n 2 to 7 Operated by CRn0 transition M N Remark n 2 to 7 Count clock CRn0 TCEn INTTMn TOn TMn 00H FFH M M 00H 00H N N M CRn0 transition TMn overflows since M N CRn0 TCEn INTTMn TOn TMn N M CRn0 transition M 01H 00H M 1 N 01H 00H N N 1 Count clock ...

Page 221: ... is incremented The edge setting can be selected to be either a rising or falling edge If the total of TMn and the value of 8 bit compare register n CRn0 match TMn is cleared to 0 and the interrupt request signal INTTMn is generated INTTMn is generated each time the TMn value matches the CRn0 value Remark n 2 to 5 Figure 7 42 Timing of External Event Counter Operation When Rising Edge Is Set TIn T...

Page 222: ...ck CRn0 Compare value TMCn Clear and start mode when TMn and CRn0 match LVSn LVRn Setting State of Timer Output Flip Flop 1 0 High level output 0 1 Low level output Inversion of timer output flip flop enabled Timer output enabled TOEn 1 2 When TCEn 1 is set the counter starts operating 3 If the values of TMn and CRn0 match the timer output flip flop inverts Also INTTMn is generated and TMn is clea...

Page 223: ...are register n CRn0 are output from TOn Set the width of the active level of the PWM pulse in CRn0 The active level can be selected by bit 1 TMCn1 in TMCn The count clock can be selected by bits 0 to 2 TCLn0 to TCLn2 of timer clock selection register n0 TCLn0 and by bit 0 TCLn3 of timer clock selection register n1 TCLn1 The PWM output can be enabled and disabled by bit 0 TOEn of TMCn Caution CRn0 ...

Page 224: ...counting starts When counting stops set TCEn to 0 PWM output operation 1 When counting starts the PWM output output from TOn outputs the inactive level until an overflow occurs 2 When the overflow occurs the active level specified in step 1 in the setting method is output The active level is output until CRn0 and the count of 8 bit counter n TMn match 3 The PWM output after CRn0 and the count matc...

Page 225: ... Inactive level Active level 01H FFH 00H 01H 02H N N 1 FFH 00H 01H 02H M 00H N When CRn0 0 Count clock TMn CRn0 TCEn INTTMn TOn Inactive level Inactive level 00H 01H FFH 00H 01H 02H N N 1 N 2 FFH 00H 01H 02H M 00H 00H When CRn0 FFH Count clock TMn CRn0 TCEn INTTMn TOn Inactive level Inactive level Active level Active level Inactive level 00H 01H FFH 00H 01H 02H N N 1 N 2 FFH 00H 01H 02H M 00H FFH ...

Page 226: ...transition N M M 1 M N M H M 2 02H 01H 00H FFH M 1 M M 2 When the CRn0 value changes from N to M after TMn overflows INTTMn N 1 02H 01H 00H FFH N N 2 TMn CRn0 TCEn TOn Count clock CRn0 transition N M N 1 N N M H N 2 02H 01H 00H FFH M 1 M M 2 03H N When the CRn0 value changes from N to M within two clocks 00H 01H immediately after TMn overflows INTTMn N 1 02H 01H 00H FFH N N 2 TMn CRn0 TCEn TOn Cou...

Page 227: ...2 TM3 cascade connection 1 Setting registers TCL20 TCL21 Select the count clock for TM2 setting not necessary for TM3 because of cascade connection CR20 CR30 Compare value 00H to FFH can be set for compare values TMC2 Selects clear start mode on a match of TM2 and CR2 x don t care TM2 TMC2 0000xxx0B TM3 TMC3 0001xxx0B 2 Set the TCE3 bit of TMC3 to 1 After that set the TCE2 bit of TMC2 to 1 to star...

Page 228: ... below Figure 7 46 Cascade Connection Mode with 16 Bit Resolution N 1 N 00H 01H TMn Count clock Enable operation starting count 00H FFH FFH 01H 00H FFH 00H 00H N 01H 00H A 00H TMn 1 01H M M 1 02H 00H 00H B CRn0 N CR n 1 0 M TCEn TCEn 1 INTTMn TOn Interval time Operation stopped Interrupt generation level inverted Counter cleared Remark n 2 4 6 ...

Page 229: ...Mn counting continues overflows and counting starts again from 0 Consequently when the value M after CRn0 changes is less than the value N before the change the timer must restart after CRn0 changes n 2 to 5 Figure 7 48 Timing After Compare Register Changes During Timer Count Operation TMn count value N Count pulse CRn0 X 1 X FFH 00H 01H 02H M Remarks 1 N X M 2 n 2 to 5 Caution Except when the TIn...

Page 230: ...gram of Watch Timer fW 210 Selector 11 bit prescaler fW 28 fW 27 fW 26 fW 25 fW 24 5 bit counter INTWTN INTWTNI WTNM0 WTNM1 WTNM3 WTNM4 WTNM5 WTNM6 WTNM7 Watch timer mode control register WTNM fXX Internal bus Clear Clear WTNM2 fXT fW 29 fW 211 WTNCS1 WTNCS0 Selector Selector Selector Watch timer clock selection register WTNCS 3 fW Remark fXX Main system clock frequency fXT Subsystem clock frequen...

Page 231: ...ed in advance Table 8 1 Interval Time of Interval Timer Interval Time fXT 32 768 kHz 2 4 1 fW 488 µs 2 5 1 fW 977 µs 2 6 1 fW 1 95 ms 2 7 1 fW 3 91 ms 2 8 1 fW 7 81 ms 2 9 1 fW 15 6 ms 2 10 1 fW 31 2 ms 2 11 1 fW 62 4 ms Remark fW Watch timer clock frequency 8 2 Configuration The watch timer includes the following hardware Table 8 2 Configuration of Watch Timer Item Configuration Counter 5 bits 1 ...

Page 232: ...it memory manipulation instruction RESET input clears WTNM to 00H Figure 8 2 Watch Timer Mode Control Register WTNM After reset 00H R W Address FFFFF360H 7 6 5 4 3 2 1 0 WTNM WTNM7 WTNM6 WTNM5 WTNM4 WTNM3 WTNM2 WTNM1 WTNM0 WTNM6 WTNM5 WTNM4 Selects interval time of prescaler 0 0 0 2 4 fW 488 µs 0 0 1 2 5 fW 977 µs 0 1 0 2 6 fW 1 95 ms 0 1 1 2 7 fW 3 91 ms 1 0 0 2 8 fW 7 81 ms 1 0 1 2 9 fW 15 6 ms ...

Page 233: ... clears WTNCS to 00H Caution Do not change the count clock during a watch timer operation Figure 8 3 Watch Timer Clock Selection Register WTNCS After reset 00H R W Address FFFFF364H 7 6 5 4 3 2 1 0 WTNCS 0 0 0 0 0 0 WTNCS1 WTNCS0 WTNCS1 WTNCS0 WTNM7 Selection of count clock Main clock frequency 0 0 0 fXX 2 7 4 194 MHz 0 0 1 fXT sub clock 0 1 0 fXX 3 2 6 6 291 MHz 0 1 1 fXX 2 8 8 388 MHz 1 0 0 Sett...

Page 234: ...15 6 ms may occur at this time Setting the WTNM0 bit to 0 can clear the interval timer However an error up to 0 5 sec may occur after a watch timer overflow INTWTN because the 5 bit counter is also cleared 8 4 2 Operation as interval timer The watch timer can also be used as an interval timer that repeatedly generates an interrupt at intervals specified by a count value set in advance The interval...

Page 235: ...l timer interrupt INTWTNI nT nT Remark fW Watch timer clock frequency fW 32 768 kHz n Interval timer operation counts 8 4 3 Cautions It takes some time to generate the first watch timer interrupt request INTWTN after operation is enabled WRNM1 and WTNM0 bits of WTNM register 1 Figure 8 5 Watch Timer Interrupt Request INTWTN Generation Interrupt Period 0 5 s It takes 0 515625 s to generate the firs...

Page 236: ...er WDTM to select the watchdog timer mode or the interval timer mode Figure 9 1 Block Diagram of Watchdog Timer Internal bus OSTS0 OSTS1 OSTS2 OSTS WDTM4 RUN WDTM WDCS WDCS0 WDCS1 WDCS2 3 INTWDTNote 1 INTWDTMNote 2 3 Output controller Prescaler Selector fXX 222 fXX 210 fXX 220 fXX 219 fXX 218 fXX 217 fXX 216 fXX 215 fXX 214 RUN Clear OSC Selector Notes 1 In watchdog timer mode 2 In interval timer ...

Page 237: ...fXX 1 6 ms 2 6 ms 2 16 fXX 3 3 ms 5 2 ms 2 17 fXX 6 6 ms 10 4 ms 2 18 fXX 13 1 ms 20 8 ms 2 19 fXX 26 2 ms 41 6 ms 2 20 fXX 52 4 ms 83 3 ms 2 22 fXX 209 7 ms 333 4 ms Note Only for the V850 SB1 2 Interval timer mode Interrupts are generated at a preset time interval Table 9 2 Interval Time of Interval Timer Interval Time Clock fXX 20 MHz Note fXX 12 58 MHz 2 14 fXX 819 2 µs 1 3 ms 2 15 fXX 1 6 ms ...

Page 238: ...r WDTM 1 Oscillation stabilization time selection register OSTS This register selects the oscillation stabilization time after a reset is applied or the STOP mode is released until the oscillation is stable OSTS is set by an 8 bit memory manipulation instruction RESET input sets OSTS to 04H Figure 9 2 Oscillation Stabilization Time Selection Register OSTS After reset 04H R W Address FFFFF380H 7 6 ...

Page 239: ...hdog Timer Clock Selection Register WDCS After reset 00H R W Address FFFFF382H 7 6 5 4 3 2 1 0 WDCS 0 0 0 0 0 WDCS2 WDCS1 WDCS0 Watchdog timer interval timer overflow time fXX WDCS2 WDCS1 WDCS0 Clock 20 MHz Note 12 58 MHz 0 0 0 2 14 fXX 819 2 µs 1 3 ms 0 0 1 2 15 fXX 1 6 ms 2 6 ms 0 1 0 2 16 fXX 3 3 ms 5 2 ms 0 1 1 2 17 fXX 6 6 ms 10 4 ms 1 0 0 2 18 fXX 13 1 ms 20 8 ms 1 0 1 2 19 fXX 26 2 ms 41 6 ...

Page 240: ...er Note 1 0 Disable count 1 Clear count and start counting WDTM4 Operating mode selection for the watchdog timer Note 2 0 Interval timer mode If an overflow occurs a maskable interrupt INTWDTM is generated 1 Watchdog timer mode 1 If an overflow occurs a non maskable interrupt INTWDT is generated Notes 1 Once RUN is set 1 the register cannot be cleared 0 by software Therefore when the count starts ...

Page 241: ...stops running in the STOP mode and IDLE mode Consequently set RUN to 1 and clear the watchdog timer before entering the STOP mode or IDLE mode Do not set the watchdog timer when operating the HALT mode since the watchdog timer running in HALT mode Cautions 1 The actual inadvertent program loop detection time may be up to 2 10 fXX seconds less than the set time 2 When the sub clock is selected for ...

Page 242: ...OP mode and IDLE mode Therefore after the RUN bit of WDTM register is set to 1 and the interval timer is cleared before entering the STOP mode IDLE mode execute the STOP instruction Cautions 1 Once bit 4 WDTM4 of WDTM is set to 1 selecting the watchdog timer mode the interval timer mode is not entered as long as RESET is not input 2 The interval time immediately after being set by WDTM may be up t...

Page 243: ...80H 7 6 5 4 3 2 1 0 OSTS 0 0 0 0 0 OSTS2 OSTS1 OSTS0 Oscillation stabilization time selection fXX OSTS2 OSTS1 OSTS0 Clock 20 MHz Note 12 58 MHz 0 0 0 2 14 fXX 819 2 µs 1 3 ms 0 0 1 2 16 fXX 3 3 ms 5 2 ms 0 1 0 2 17 fXX 6 6 ms 10 4 ms 0 1 1 2 18 fXX 13 1 ms 20 8 ms 1 0 0 2 19 fXX after reset 26 2 ms 41 6 ms Other than above Setting prohibited Note Only for the V850 SB1 Caution The wait time at the ...

Page 244: ...erial I O or I 2 C can be used as a serial interface 10 2 3 Wire Serial I O CSI0 to CSI3 CSIn n 0 to 3 has the following two modes 1 Operation stop mode This mode is used when serial transfers are not performed 2 3 wire serial I O mode fixed as MSB first This is an 8 bit data transfer mode using three lines a serial clock line SCKn serial output line SOn and serial input line SIn Since simultaneou...

Page 245: ...ollows When n 0 or 3 TM2 When n 1 or 2 TM3 1 Serial I O shift registers 0 to 3 SIO0 to SIO3 SIOn is an 8 bit register that performs parallel serial conversion and serial transmit receive shift operations synchronized with the serial clock SIOn is set by an 8 bit memory manipulation instruction When 1 is set to bit 7 CSIEn of serial operation mode register n CSIMn a serial operation can be started ...

Page 246: ...rial operation mode register n CSIMn Serial clock selection register n CSISn 1 Serial operation mode registers 0 to 3 CSIM0 to CSIM3 CSIMn is used to enable or disable serial interface channel n s serial clock operation modes and specific operations CSIMn can be set by an 8 1 bit memory manipulation instruction RESET input clears these registers to 00H ...

Page 247: ...IOn write Normal output 1 Receive only mode SIOn read Port function SCLn2 SCLn1 SCLn0 Clock selection 0 0 0 External clock input SCKn 0 0 1 at n 0 3 Output of TO2 at n 1 2 Output of TO3 0 1 0 fXX 8 0 1 1 fXX 16 1 0 0 Setting prohibited 1 0 1 Setting prohibited 1 1 0 fXX 32 1 1 1 fXX 64 Notes 1 The SIn SOn and SCKn pins are used as port function pins when CSIEn 0 SIOn operation stop status 2 When C...

Page 248: ...al clock CSISn can be set by an 8 bit memory manipulation instruction RESET input clears these registers to 00H Figure 10 3 Serial Clock Selection Registers 0 to 3 CSIS0 to CSIS3 After reset 00H R W Address CSIS0 FFFFF2A4H CSIS1 FFFFF2B4H CSIS2 FFFFF2C4H CSIS3 FFFFF2D4H 7 6 5 4 3 2 1 0 CSISn 0 0 0 0 0 0 0 SCLn2 n 0 to 3 Remark Refer to Figure 10 2 for the setting of the SCLn2 bit ...

Page 249: ... SCKn pin are also used as I O ports they can be used as normal I O ports as well a Register settings Operation stop mode are set via the CSIEn bit of serial operation mode register n CSIMn Figure 10 4 CSIMn Setting Operation Stop Mode After reset 00H R W Address CSIM0 FFFFF2A2H CSIM1 FFFFF2B2H CSIM2 FFFFF2C2H CSIM3 FFFFF2D2H 7 6 5 4 3 2 1 0 CSIMn CSIEn 0 0 0 0 MODEn SCLn1 SCLn0 n 0 to 3 SIOn oper...

Page 250: ...s CSIM0 FFFFF2A2H CSIM1 FFFFF2B2H CSIM2 FFFFF2C2H CSIM3 FFFFF2D2H 7 6 5 4 3 2 1 0 CSIMn CSIEn 0 0 0 0 MODEn SCLn1 SCLn0 n 0 to 3 SIOn operation enable disable specification CSIEn Shift register operation Serial counter Port 1 Operation enable Count operation enable Serial function port function Transfer operation mode flag MODEn Operation mode Transfer start trigger SOn output 0 Transmit receive m...

Page 251: ...DI3 DI2 DI1 DI0 INTCSIn Serial clock 1 SO0 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 2 3 4 5 6 7 8 Transfer completion Transfer starts in synchronization with the serial clock s falling edge c Transfer start A serial transfer starts when the following two conditions have been satisfied and transfer data has been set to serial I O shift register n SIOn The SIOn operation control bit CSIEn 1 After an 8 bit se...

Page 252: ...d when serial transfers are not performed It can therefore be used to reduce power consumption 2 I 2 C bus mode multimaster support This mode is used for 8 bit data transfers with several devices via two lines a serial clock SCLn line and a serial data bus SDAn line This mode complies with the I 2 C bus format and the master device can output start condition data and stop condition data to the sla...

Page 253: ...time correction circuit ACK detector Wake up controller ACK detector Stop condition detector Serial clock counter Interrupt request signal generator Serial clock controller Serial clock wait controller Prescaler INTIICn fXX TMx output LRELn WRELn SPIEn WTIMn ACKEn STTn SPTn MSTSn ALDn EXCn COIn TRCn ACKDn STDn SPDn Start condition detector Internal bus CLDn DADn SMCn DFCn CLn1 CLn0 CLXn IICCEn1 II...

Page 254: ...ation example is shown below Figure 10 8 Serial Bus Configuration Example Using I 2 C Bus SDA SCL SDA VDD VDD SCL SDA SCL Slave CPU3 Address 3 SDA SCL Slave IC Address 4 SDA SCL Slave IC Address N Master CPU1 Slave CPU1 Address 1 Serial data bus Serial clock Master CPU2 Slave CPU2 Address 2 ...

Page 255: ...on n 0 1 Write and read operations to IICn are used to control the actual transmit and receive operations IICn is set by an 8 bit memory manipulation instruction RESET input clears IIC0 and IIC1 to 00H 2 Slave address registers 0 and 1 SVA0 SVA1 SVAn sets local addresses when in slave mode SVAn is set by an 8 bit memory manipulation instruction n 0 1 RESET input clears SVA0 and SVA1 to 00H 3 SO la...

Page 256: ... WTIMn bit Bit 3 of IIC control register n IICCn SPIEn bit Bit 4 of IIC control register n IICCn Remark n 0 1 8 Serial clock controller In master mode this circuit generates the clock output via the SCLn pin from a sampling clock n 0 1 9 Serial clock wait controller This circuit controls the wait timing 10 ACK output circuit stop condition detector start condition detector and ACK detector These c...

Page 257: ...e also used IIC shift registers 0 1 IIC0 IIC1 Slave address registers 0 1 SVA0 SVA1 1 IIC control registers 0 1 IICC0 IICC1 IICCn is used to enable disable I 2 C operations set wait timing and set other I 2 C operations IICCn can be set by an 8 1 bit memory manipulation instruction n 0 1 RESET input clears IICCn to 00H Caution In I 2 C0 I 2 C1 bus mode set the port 1 mode register PM1 and port 2 m...

Page 258: ...ude cases in which a locally irrelevant extension code has been received The SCLn and SDAn lines are set to high impedance The following flags are cleared STDn ACKDn TRCn COIn EXCn MSTSn STTn SPTn The standby mode following exit from communications remains in effect until the following communications entry conditions are met After a stop condition is detected restart is in master mode An address m...

Page 259: ...mode After output of eight clocks clock output is set to low level and wait is set Slave mode After input of eight clocks the clock is set to low level and wait is set for master device 1 Interrupt request is generated at the ninth clock s falling edge Master mode After output of nine clocks clock output is set to low level and wait is set Slave mode After input of nine clocks the clock is set to ...

Page 260: ... Next after the rated amount of time has elapsed SCLn is changed to low level When bus is not used This trigger functions as a start condition reserve flag When set it releases the bus and then automatically generates a start condition In the wait state when master device Generates a restart condition after releasing the wait Cautions concerning set timing For master reception Cannot be set during...

Page 261: ...s STTn SPTn can be set only when in master mode Note When WTIMn has been set to 0 if SPTn is set during the wait period that follows output of eight clocks note that a stop condition will be generated during the high level period of the ninth clock When a ninth clock must be output WTIMn should be changed from 0 to 1 during the wait period following output of eight clocks and SPTn should be set du...

Page 262: ... 0 Condition for setting MSTSn 1 When a stop condition is detected When ALDn 1 Cleared by LRELn 1 When IICEn changes from 1 to 0 When RESET is input When a start condition is generated ALDn Detection of arbitration loss 0 This status means either that there was no arbitration or that the arbitration result was a win 1 This status indicates the arbitration result was a loss MSTSn is cleared Conditi...

Page 263: ...l address SVAn set at the rising edge of the eighth clock TRCn Detection of transmit receive status 0 Receive status other than transmit status The SDAn line is set for high impedance 1 Transmit status The value in the SO latch is enabled for output to the SDAn line valid starting at the falling edge of the first byte s ninth clock Condition for clearing TRCn 0 Condition for setting TRCn 1 When a ...

Page 264: ...was detected This indicates that the address transfer period is in effect Condition for clearing STDn 0 Condition for setting STDn 1 When a stop condition is detected At the rising edge of the next byte s first clock following address transfer Cleared by LRELn 1 When IICEn changes from 1 to 0 When RESET is input When a start condition is detected SPDn Detection of stop condition 0 Stop condition w...

Page 265: ...1 0 SCLn line was detected at low level 1 SCLn line was detected at high level Condition for clearing CLDn 0 Condition for setting CLDn 1 When the SCLn line is at low level When IICEn 0 When RESET is input When the SCLn line is at high level DADn Detection of SDAn line level valid only when IICEn 1 0 SDAn line was detected at low level 1 SDAn line was detected at high level Condition for clearing ...

Page 266: ...Set the IICCEn1 and IICCEn0 bits in combination with the SMCn CLn1 and CLn0 bits of IIC clock selection register n IICCLn and the CLXn bit of IIC function expansion register n IICXn see 10 3 2 6 I 2 Cn transfer clock setting method n 0 1 RESET input clears these registers to 00H Figure 10 13 IIC Clock Expansion Register n IICCEn 6 I 2 Cn transfer clock setting method The I 2 Cn transfer clock freq...

Page 267: ... fXX 12 4 0 MHz to 4 19 MHz x x 0 1 0 x fXX 24 4 0 MHz to 8 38 MHz x x 0 1 1 0 fXX 48 8 0 MHz to 16 67 MHz 0 1 0 1 1 1 fXX 36 12 0 MHz to 13 4 MHz 1 0 0 1 1 1 fXX 54 16 0 MHz to 20 0 MHz Note n 0 TM2 output 18 TM2 setting 0 0 0 1 1 1 n 1 TM3 output 18 TM3 setting High speed mode SMCn 1 x x 0 0 0 0 fXX 44 2 0 MHz to 4 19 Mhz x x 0 0 0 1 fXX 86 4 19 MHz to 8 38 MHz x x 0 0 1 0 fXX 172 8 38 MHz to 16...

Page 268: ...ddress Register n SVAn 10 3 3 I 2 C bus mode functions 1 Pin configuration The serial clock pin SCLn and serial data bus pin SDAn are configured as follows n 0 1 SCLn This pin is used for serial clock input and output This pin is an N ch open drain output for both master and slave devices Input is Schmitt input SDAn This pin is used for serial data input and output This pin is an N ch open drain o...

Page 269: ...the start condition data and stop condition output via the I 2 C bus s serial data bus is shown below Figure 10 17 I 2 C Bus s Serial Data Transfer Timing 1 to 7 8 9 1 to 7 8 9 1 to 7 8 9 SCL SDA Start condition Address R W ACK Data Data Stop condition ACK ACK The master device outputs the start condition slave address and stop condition The acknowledge signal ACK can be output by either the maste...

Page 270: ...s The 7 bits of data that follow the start condition are defined as an address An address is a 7 bit data segment that is output in order to select one of the slave devices that are connected to the master device via bus lines Therefore each slave device connected via the bus lines must have a unique address The slave devices include hardware that detects the start condition and checks whether or ...

Page 271: ...ress data the master device sends 1 bit that specifies the transfer direction When this transfer direction specification bit has a value of 0 it indicates that the master device is transmitting data to a slave device When the transfer direction specification bit has a value of 1 it indicates that the master device is receiving data from a slave device Figure 10 20 Transfer Direction Specification ...

Page 272: ... data was received When the receiving device sets the SDAn line to low level during the ninth clock the ACK signal becomes active normal receive response When bit 2 ACKEn of IIC control register n IICCn is set to 1 automatic ACK signal generation is enabled n 0 1 Transmission of the eighth bit following the 7 address data bits causes bit 3 TRCn of IIC status register n IICSn to be set When this TR...

Page 273: ... When 9 clock wait is selected ACK signal is automatically output at the falling edge of the SCLn s eighth clock if ACKEn has already been set to 1 5 Stop condition When the SCLn pin is at high level changing the SDAn pin from low level to high level generates a stop condition n 0 1 A stop condition is a signal that the master device outputs to the slave device when serial transfer has been comple...

Page 274: ... for both the master and slave devices the next data transfer can begin n 0 1 Figure 10 23 Wait Signal 1 2 a When master device has a nine clock wait and slave device has an eight clock wait master transmission slave reception and ACKEn 1 SCL 6 SDA 7 8 9 1 2 3 SCL IIC0 6 H 7 8 1 2 3 D2 D1 D0 ACK D7 D6 D5 9 IIC0 SCL ACKE Master Master returns to high impedance but slave is in wait state low level W...

Page 275: ...t according to previously set ACKE value Transfer lines Remarks 1 ACKEn Bit 2 of IIC control register n IICCn WRELn Bit 5 of IIC control register n IICCn 2 n 0 1 A wait may be automatically generated depending on the setting for bit 3 WTIMn of IIC control register n IICCn n 0 1 Normally when bit 5 WRELn of IICCn is set to 1 or when FFH is written to IIC shift register n IICn the wait status is can...

Page 276: ...a Data Stop normal transmission reception 1 When WTIMn 0 SPTn 1 ST AD6 to AD0 RW AK D7 to D0 AK D7 to D0 AK SP 1 2 3 4 5 1 IICSn 10XXX110B 2 IICSn 10XXX000B 3 IICSn 10XXX000B WTIMn 0 4 IICSn 10XXXX00B 5 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 X don t care n 0 1 2 When WTIMn 1 SPTn 1 ST AD6 to AD0 RW AK D7 to D0 AK D7 to D0 AK SP 1 2 3 4 1 IICSn 10XXX110B 2 IICSn 10XXX10...

Page 277: ...000B WTIMn 1 3 IICSn 10XXXX00B WTIMn 0 4 IICSn 10XXX110B WTIMn 0 5 IICSn 10XXX000B WTIMn 1 6 IICSn 10XXXX00B 7 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 X don t care n 0 1 2 When WTIMn 1 STTn 1 SPTn 1 ST AD6 to AD0 RW AK D7 to D0 AK ST AD6 to AD0 RW AK D7 to D0 AK SP 1 2 3 4 5 1 IICSn 10XXX110B 2 IICSn 10XXXX00B 3 IICSn 10XXX110B 4 IICSn 10XXXX00B 5 IICSn 00000001B Remark...

Page 278: ... 2 3 4 5 1 IICSn 1010X110B 2 IICSn 1010X000B 3 IICSn 1010X000B WTIMn 1 4 IICSn 1010XX00B 5 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 X don t care n 0 1 2 When WTIMn 1 SPTn 1 ST AD6 to AD0 RW AK D7 to D0 AK D7 to D0 AK SP 1 2 3 4 1 IICSn 1010X110B 2 IICSn 1010X100B 3 IICSn 1010XX00B 4 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 X don t care n 0 1 ...

Page 279: ... AD0 RW AK D7 to D0 AK D7 to D0 AK SP 1 2 3 4 1 IICSn 0001X110B 2 IICSn 0001X000B 3 IICSn 0001X000B 4 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 X don t care n 0 1 2 When WTIMn 1 ST AD6 to AD0 RW AK D7 to D0 AK D7 to D0 AK SP 1 2 3 4 1 IICSn 0001X110B 2 IICSn 0001X100B 3 IICSn 0001XX00B 4 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 X don t care n 0 ...

Page 280: ...ICSn 0001X110B 2 IICSn 0001X000B 3 IICSn 0001X110B 4 IICSn 0001X000B 5 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 X don t care n 0 1 2 When WTIMn 1 after restart match with SVAn ST AD6 to AD0 RW AK D7 to D0 AK ST AD6 to AD0 RW AK D7 to D0 AK SP 1 2 3 4 5 1 IICSn 0001X110B 2 IICSn 0001XX00B 3 IICSn 0001X110B 4 IICSn 0001XX00B 5 IICSn 00000001B Remark Always generated Genera...

Page 281: ...10B 2 IICSn 0001X000B 3 IICSn 0010X010B 4 IICSn 0010X000B 5 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 X don t care n 0 1 2 When WTIMn 1 after restart extension code reception ST AD6 to AD0 RW AK D7 to D0 AK ST AD6 to AD0 RW AK D7 to D0 AK SP 1 2 3 4 5 6 1 IICSn 0001X110B 2 IICSn 0001XX00B 3 IICSn 0010X010B 4 IICSn 0010X110B 5 IICSn 0010XX00B 6 IICSn 00000001B Remark Alway...

Page 282: ... AK SP 1 2 3 4 1 IICSn 0001X110B 2 IICSn 0001X000B 3 IICSn 00000X10B 4 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 X don t care n 0 1 2 When WTIMn 1 after restart mismatch with address not extension code ST AD6 to AD0 RW AK D7 to D0 AK ST AD6 to AD0 RW AK D7 to D0 AK SP 1 2 3 4 1 IICSn 0001X110B 2 IICSn 0001XX00B 3 IICSn 00000X10B 4 IICSn 00000001B Remark Always generated G...

Page 283: ... D7 to D0 AK SP 1 2 3 4 1 IICSn 0010X010B 2 IICSn 0010X000B 3 IICSn 0010X000B 4 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 X don t care n 0 1 2 When WTIMn 1 ST AD6 to AD0 RW AK D7 to D0 AK D7 to D0 AK SP 1 2 3 4 5 1 IICSn 0010X010B 2 IICSn 0010X110B 3 IICSn 0010X100B 4 IICSn 0010XX00B 5 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 X don t care n 0 1 ...

Page 284: ...10B 2 IICSn 0010X000B 3 IICSn 0001X110B 4 IICSn 0001X000B 5 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 X don t care n 0 1 2 When WTIMn 1 after restart match with SVAn ST AD6 to AD0 RW AK D7 to D0 AK ST AD6 to AD0 RW AK D7 to D0 AK SP 1 2 3 4 5 6 1 IICSn 0010X010B 2 IICSn 0010X110B 3 IICSn 0010XX00B 4 IICSn 0001X110B 5 IICSn 0001XX00B 6 IICSn 00000001B Remark Always generat...

Page 285: ...0010X000B 3 IICSn 0010X010B 4 IICSn 0010X000B 5 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 X don t care n 0 1 2 When WTIMn 1 after restart extension code reception ST AD6 to AD0 RW AK D7 to D0 AK ST AD6 to AD0 RW AK D7 to D0 AK SP 1 2 3 4 5 6 7 1 IICSn 0010X010B 2 IICSn 0010X110B 3 IICSn 0010XX00B 4 IICSn 0010X010B 5 IICSn 0010X110B 6 IICSn 0010XX00B 7 IICSn 00000001B Rema...

Page 286: ...3 4 1 IICSn 0010X010B 2 IICSn 0010X000B 3 IICSn 00000X10B 4 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 X don t care n 0 1 2 When WTIMn 1 after restart mismatch with address not extension code ST AD6 to AD0 RW AK D7 to D0 AK ST AD6 to AD0 RW AK D7 to D0 AK SP 1 2 3 4 5 1 IICSn 0010X010B 2 IICSn 0010X110B 3 IICSn 0010XX00B 4 IICSn 00000X10B 5 IICSn 00000001B Remark Always ge...

Page 287: ...sion of slave address data 1 When WTIMn 0 ST AD6 to AD0 RW AK D7 to D0 AK D7 to D0 AK SP 1 2 3 4 1 IICSn 0101X110B Example when ALDn is read during interrupt servicing 2 IICSn 0001X000B 3 IICSn 0001X000B 4 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 X don t care n 0 1 2 When WTIMn 1 ST AD6 to AD0 RW AK D7 to D0 AK D7 to D0 AK SP 1 2 3 4 1 IICSn 0101X110B Example when ALDn i...

Page 288: ...is read during interrupt servicing 2 IICSn 0010X000B 3 IICSn 0010X000B 4 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 X don t care n 0 1 2 When WTIMn 1 ST AD6 to AD0 RW AK D7 to D0 AK D7 to D0 AK SP 1 2 3 4 5 1 IICSn 0110X010B Example when ALDn is read during interrupt servicing 2 IICSn 0010X110B 3 IICSn 0010X100B 4 IICSn 0010XX00B 5 IICSn 00000001B Remark Always generated G...

Page 289: ...P 1 2 1 IICSn 01000110B Example when ALDn is read during interrupt servicing 2 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 n 0 1 b When arbitration loss occurs during transmission of extension code ST AD6 to AD0 RW AK D7 to D0 AK D7 to D0 AK SP 1 2 1 IICSn 0110X010B Example when ALDn is read during interrupt servicing IICCn s LRELn is set to 1 by software 2 IICSn 00000001B ...

Page 290: ...ICSn 10001110B 2 IICSn 01000000B Example when ALDn is read during interrupt servicing 3 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 n 0 1 2 When WTIMn 1 ST AD6 to AD0 RW AK D7 to D0 AK D7 to D0 AK SP 1 2 3 1 IICSn 10001110B 2 IICSn 01000100B Example when ALDn is read during interrupt servicing 3 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 n 0 1 ...

Page 291: ...n 01000110B Example when ALDn is read during interrupt servicing 3 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 X don t care Dn D6 to D0 n 0 1 2 Extension code ST AD6 to AD0 RW AK D7 to Dn ST AD6 to AD0 RW AK D7 to D0 AK SP 1 2 3 1 IICSn 1000X110B 2 IICSn 0110X010B Example when ALDn is read during interrupt servicing IICCn s LRELn is set to 1 by software 3 IICSn 00000001B Re...

Page 292: ...ed only when SPIEn 1 X don t care Dn D6 to D0 n 0 1 f When arbitration loss occurs due to low level data when attempting to generate a restart condition When WTIMn 1 STTn 1 ST AD6 to AD0 RW AK D7 to D0 AK D7 to D0 AK D7 to D0 AK SP 1 2 3 4 1 IICSn 1000X110B 2 IICSn 1000XX00B 3 IICSn 01000100B Example when ALDn is read during interrupt servicing 4 IICSn 00000001B Remark Always generated Generated o...

Page 293: ... 3 IICSn 01000001B Remark Always generated Generated only when SPIEn 1 X don t care n 0 1 h When arbitration loss occurs due to low level data when attempting to generate a stop condition When WTIMn 1 SPTn 1 ST AD6 to AD0 RW AK D7 to D0 AK D7 to D0 AK D7 to D0 AK SP 1 2 3 4 1 IICSn 1000X110B 2 IICSn 1000XX00B 3 IICSn 01000000B Example when ALDn is read during interrupt servicing 4 IICSn 00000001B ...

Page 294: ...lave address register n SVAn neither INTIICn nor a wait occurs Remarks 1 The numbers in the table indicate the number of the serial clock s clock signals Interrupt requests and wait control are both synchronized with the falling edge of these clock signals 2 n 0 1 1 During address transmission reception Slave device operation Interrupt and wait timing are determined regardless of the WTIMn bit Mas...

Page 295: ...ssion error is judged as having occurred when the compared data values do not match n 0 1 10 3 9 Extension code 1 When the higher 4 bits of the receive address are either 0000 or 1111 the extension code flag EXCn is set for extension code reception and an interrupt request INTIICn is issued at the falling edge of the eighth clock n 0 1 The local address stored in slave address register n SVAn is n...

Page 296: ...f clocks is adjusted until the data differs This kind of operation is called arbitration n 0 1 When one of the master devices loses in arbitration an arbitration loss flag ALDn in IIC status register n IICSn is set via the timing by which the arbitration loss occurred and the SCLn and SDAn lines are both set for high impedance which releases the bus n 0 1 The arbitration loss is detected based on ...

Page 297: ...xtension code transmission During data transmission During ACK signal transfer period after data transmission When restart condition is detected during data transfer When stop condition is detected during data transfer When stop condition is output when SPIEn 1 Note 2 When data is at low level while attempting to output a restart condition At falling edge of eighth or ninth clock following byte tr...

Page 298: ...lave function is a function that generates an interrupt request INTIICn when a local address and extension code have been received This function makes processing more efficient by preventing unnecessary interrupt requests from occurring when addresses do not match When a start condition is detected wake up standby mode is set This wake up standby mode is in effect while addresses are transmitted d...

Page 299: ...cted when a stop condition is detected writing to IIC shift register n IICn causes the master s address transfer to start At this point IICCn s bit 4 SPIEn should be set n 0 1 When STTn has been set the operation mode as start condition or as communication reservation is determined according to the bus status n 0 1 If the bus has been released a start condition is generated If the bus has not been...

Page 300: ...s access IICn IIC shift register n STTn Bit 1 of IIC control register n IICCn STDn Bit 1 of IIC status register n IICSn SPDn Bit 0 of IIC status register n IICSn Remark n 0 1 Communication reservations are accepted via the following timing After bit 1 STDn of IIC status register n IICSn is set to 1 a communication reservation can be made by setting bit 1 STTn of IIC control register n IICCn to 1 b...

Page 301: ...I MSTSn 0 Communication reservation Note Generate start condition Sets STT flag communication reservation Gets wait period set by software see Table 10 7 Confirmation of communication reservation Clear user flag IICn write operation Defines that communication reservation is in effect defines and sets user flag to any part of RAM Note The communication reservation operation executes a write to IIC ...

Page 302: ...irst generate a stop condition to release the bus then perform master device communication When using multiple masters it is not possible to perform master device communication when the bus has not been released when a stop condition has not been detected Use the following sequence for generating a stop condition a Set IIC clock selection register n IICCLn b Set bit 7 IICEn of IIC control register...

Page 303: ...Cn H IICEn SPIEn WTIMn 1 Start IICn write transfer Start IICn write transfer WRELn 1 Start reception Generate stop condition no slave with matching address Generate restart condition or stop condition START Data processing Data processing ACKEn 0 No Yes No No No No No No Yes Yes Yes Yes Yes INTIICn 1 WTIMn 0 ACKEn 1 INTIICn 1 Transfer completed INTIICn 1 ACKDn 1 TRCn 1 INTIICn 1 ACKDn 1 Stop condi...

Page 304: ...Flow Chart IICCn H IICEn 1 WRELn 1 Start reception Detect restart condition or stop condition START ACKEn 0 Data processing Data processing LRELn 1 No Yes No No No No No No No Yes No Yes Yes Yes Yes Yes Yes WTIMn 0 ACKEn 1 INTIICn 1 Yes Communicate Transfer completed INTIICn 1 WTIMn 1 Start IICn write transfer INTIICn 1 EXCn 1 COIn 1 TRCn 1 ACKDn 1 Remark n 0 1 ...

Page 305: ... device transmits the TRCn bit bit 3 of IIC status register n IICSn that specifies the data transfer direction and then starts serial communication with the slave device IIC bus shift register n IICn s shift operation is synchronized with the falling edge of the serial clock SCLn The transmit data is transferred to the SO latch and is output MSB first via the SDAn pin Data input via the SDAn pin i...

Page 306: ...H H L L L L H H H L L ACKEn MSTSn STTn SPTn WRELn INTIICn TRCn IICn ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn WRELn INTIICn TRCn SCLn SDAn Processing by master device Transfer lines Processing by slave device 1 2 3 4 5 6 7 8 9 4 3 2 1 AD6 AD5 AD4 AD3 AD2 AD1 AD0 W ACK D4 D5 D6 D7 IICn address IICn data IICn FFH Transmit Start condition Receive When EXC 1 Note Note Note To cancel slave wait write...

Page 307: ...L L L L L H H H H L L L L L ACKEn MSTSn STTn SPTn WRELn INTIICn TRCn IICn ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn WRELn INTIICn TRCn SCLn SDAn Processing by master device Transfer lines Processing by slave device 1 9 8 2 3 4 5 6 7 8 9 3 2 1 D7 D0 D6 D5 D4 D3 D2 D1 D0 D5 D6 D7 IICn data IICn FFH Note IICn FFH Note IICn data Transmit Receive Note Note Note To cancel slave wait write FFH to IICn ...

Page 308: ... ACKEn MSTSn STTn SPTn WRELn INTIICn TRCn IICn ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn WRELn INTIICn TRCn SCLn SDAn Processing by master device Transfer lines Processing by slave device 1 2 3 4 5 6 7 8 9 2 1 D7 D6 D5 D4 D3 D2 D1 D0 AD5 AD6 IICn data IICn address IICn FFH Note IICn FFH Note Stop condition Start condition Transmit Note Note When SPIEn 1 Receive When SPIEn 1 Note To cancel slave ...

Page 309: ...n SPDn WTIMn H H L L H H L ACKEn MSTSn STTn L L SPTn WRELn INTIICn TRCn IICn ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn WRELn INTIICn TRCn SCLn SDAn Processing by master device Transfer lines Processing by slave device 1 2 3 4 5 6 7 8 9 4 5 6 3 2 1 AD6 AD5 AD4 AD3 AD2 AD1 AD0 R D4 D3 D2 D5 D6 D7 IICn address IICn FFH Note Note IICn data Start condition Note To cancel slave wait write FFH to IICn ...

Page 310: ...L L L L H H H L L L L L ACKEn MSTSn STTn SPTn WRELn INTIICn TRCn IICn ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn WRELn INTIICn TRCn SCLn SDAn Processing by master device Transfer lines Processing by slave device 1 8 9 2 3 4 5 6 7 8 9 3 2 1 D7 D0 ACK D6 D5 D4 D3 D2 D1 D0 ACK D5 D6 D7 Note Note Receive Transmit IICn data IICn data IICn FFH Note IICn FFH Note Note To cancel slave wait write FFH to I...

Page 311: ... H L L L H H ACKEn MSTSn STTn SPTn WRELn INTIICn TRCn IICn ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn WRELn INTIICn TRCn SCLn SDAn Processing by master device Transfer lines Processing by slave device 1 2 3 4 5 6 7 8 9 2 1 D7 D6 D5 D4 D3 D2 D1 D0 AD5 AD6 IICn address IICn FFH Note Note IICn data Stop condition Start condition When SPIEn 1 N ACK When SPIEn 1 Note To cancel slave wait write FFH to ...

Page 312: ...selectable baud rates In addition a baud rate based on divided clock input to the ASCKn pin can also be defined The UARTn baud rate generator can also be used to generate a MIDI standard baud rate 31 25 Kbps 10 4 1 Configuration The UARTn includes the following hardware Table 10 8 Configuration of UARTn Item Configuration Registers Transmit shift registers 0 1 TXS0 TXS1 Receive buffer registers 0 ...

Page 313: ...ial data Writing data to TXSn starts the transmit operation TXSn can be written to by an 8 bit memory manipulation instruction It cannot be read from RESET input sets these registers to FFH Caution Do not write to TXSn during a transmit operation 2 Receive shift registers 0 1 RX0 RX1 RXn register converts serial data input via the RXD0 RXD1 pins to parallel data When one byte of data is received a...

Page 314: ...operations based on the values set to asynchronous serial interface mode register n ASIMn During a receive operation it performs error checking such as for parity errors and sets various values to asynchronous serial interface status register n ASISn according to the type of error that is detected 10 4 2 UARTn control registers UARTn uses the following registers for control function n 0 1 Asynchro...

Page 315: ...function 0 1 UARTn mode receive only Serial function Port function 1 0 UARTn mode transmit only Port function Serial function 1 1 UARTn mode transmit and receive Serial function Serial function PS1n PS0n Parity bit specification 0 0 No parity 0 1 Zero parity always added during transmission No parity detection during reception parity errors do not occur 1 0 Odd parity 1 1 Even parity UCLn Characte...

Page 316: ...y error flag 0 No parity error 1 Parity error Transmit data parity does not match FEn Framing error flag 0 No framing error 1 Framing error Note 1 Stop bit not detected OVEn Overrun error flag 0 No overrun error 1 Overrun error Note 2 Next receive operation was completed before data was read from receive buffer register Notes 1 Even if a stop bit length has been set as two bits by setting bit 2 SL...

Page 317: ...ng prohibited 0 0 0 0 1 0 0 0 fSCK 8 8 0 0 0 0 1 0 0 1 fSCK 9 9 0 0 0 0 1 0 1 0 fSCK 10 10 0 0 0 0 1 0 1 1 fSCK 11 11 0 0 0 0 1 1 0 0 fSCK 12 12 0 0 0 0 1 1 0 1 fSCK 13 13 0 0 0 0 1 1 1 0 fSCK 14 14 0 0 0 0 1 1 1 1 fSCK 15 15 0 0 0 1 0 0 0 0 fSCK 16 16 1 1 1 1 1 1 1 1 fSCK 255 255 Cautions 1 The value of BRGCn becomes 00H after reset Before starting operation select a setting other than Setting pr...

Page 318: ...Sn2 TPSn1 TPSn0 8 bit counter source clock selection m 0 0 0 0 External clock ASCKn 0 0 0 1 fXX 0 0 0 1 0 fXX 2 1 0 0 1 1 fXX 4 2 0 1 0 0 fXX 8 3 0 1 0 1 fXX 16 4 0 1 1 0 fXX 32 5 0 1 1 1 at n 0 TM3 output at n 1 TM2 output 1 0 0 0 fXX 64 6 1 0 0 1 fXX 128 7 1 0 1 0 fXX 256 8 1 0 1 1 fXX 512 9 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 Setting prohibited Caution If write is performed to BRGMCn0 n1 during com...

Page 319: ...d as ordinary ports a Register settings Operation stop mode settings are made via bits TxEn and RXEn of asynchronous serial interface mode register n ASIMn Figure 10 37 ASIMn Setting Operation Stop Mode After reset 00H R W Address FFFFF300H FFFFF310H 7 6 5 4 3 2 1 0 ASIMn TXEn RXEn PS1n PS0n CLn SLn ISRMn 0 n 0 1 TXEn RXEn Operation mode RXDn Pxx pin function TXDn Pxx pin function 0 0 Operation st...

Page 320: ...n PS0n CLn SLn ISRMn 0 n 0 1 TXEn RXEn Operation mode RXDn Pxx pin function TXDn Pxx pin function 0 1 UARTn mode receive only Serial function Port function 1 0 UARTn mode transmit only Port function Serial function 1 1 UARTn mode transmit and receive Serial function Serial function PS1n PS0n Parity bit specification 0 0 No parity 0 1 Zero parity always added during transmission No parity detection...

Page 321: ...top bit not detected OVEn Overrun error flag 0 No overrun error 1 Overrun error Note 2 Next receive operation was completed before data was read from receive buffer register Notes 1 Even if a stop bit length has been set as two bits by setting bit 2 SLn in asynchronous serial interface mode register n ASIMn stop bit detection during a receive operation only applies to a stop bit length of 1 bit 2 ...

Page 322: ...SCK 10 10 0 0 0 0 1 0 1 1 fSCK 11 11 0 0 0 0 1 1 0 0 fSCK 12 12 0 0 0 0 1 1 0 1 fSCK 13 13 0 0 0 0 1 1 1 0 fSCK 14 14 0 0 0 0 1 1 1 1 fSCK 15 15 0 0 0 1 0 0 0 0 fSCK 16 16 1 1 1 1 1 1 1 1 fSCK 255 255 Cautions 1 Before starting operation select a setting other than Setting prohibited Selecting Setting prohibited setting in stop mode does not cause any problems 2 If write is performed to BRGCn duri...

Page 323: ...0 1 1 fXX 4 2 0 1 0 0 fXX 8 3 0 1 0 1 fXX 16 4 0 1 1 0 fXX 32 5 0 1 1 1 at n 0 TM3 output at n 1 TM2 output 1 0 0 0 fXX 64 6 1 0 0 1 fXX 128 7 1 0 1 0 fXX 256 8 1 0 1 1 fXX 512 9 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 Setting prohibited Caution If write is performed to BRGMCn0 n1 during communication processing the output of the baud rate generator is disturbed and communication will not be performed nor...

Page 324: ...example of the baud rate tolerance Table 10 9 Relationship Between Main Clock and Baud Rate fXX 8 MHz fXX 12 58 MHz fXX 16 MHz Note fXX 20 MHz Note Baud Rate bps k m Error k m Error k m Error k m Error 32 244 9 0 06 64 244 8 0 06 192 9 0 02 244 9 0 06 128 244 7 0 06 192 8 0 02 244 8 0 06 152 9 0 39 300 208 6 0 16 164 7 0 12 208 7 0 16 130 8 0 16 600 208 5 0 16 164 6 0 12 208 6 0 16 130 7 0 16 1200...

Page 325: ... speed clock clock cycle T enabling normal reception START D0 D7 P STOP Low speed clock clock cycle T enabling normal reception START D0 D7 P STOP 32T 64T 256T 288T 320T 352T Ideal sampling point 304T 336T 30 45T 60 9T 304 5T 15 5T 15 5T 0 5T Sampling error 33 55T 67 1T 301 95T 335 5T Remark T 8 bit counter s source clock cycle Baud rate error tolerance when k 16 100 4 8438 15 5 320 ...

Page 326: ... D6 D7 Start bit Parity bit Stop bit 1 data frame Start bit 1 bit Character bits 7 bits or 8 bits Parity bit Even parity odd parity zero parity or no parity Stop bit s 1 bit or 2 bits When 7 bits is selected as the number of character bits only the lower 7 bits from bit 0 to bit 6 are valid so that during a transmission the highest bit bit 7 is ignored and during reception the highest bit bit 7 mu...

Page 327: ...a including a parity bit and a parity error is generated when the result is an odd number ii Odd parity During transmission The number of bits in transmit data including a parity bit is controlled so that the number is set an odd number of 1 bits The value of the parity bit is as follows If the transmit data contains an odd number of 1 bits The parity bit value is 0 If the transmit data contains a...

Page 328: ...ure 10 44 Timing of Asynchronous Serial Interface Transmit Completion Interrupt TxDn output D0 D1 D2 D6 D7 Parity STOP START INTSTn a Stop bit length 1 TxDn output D0 D1 D2 D6 D7 Parity START INTSTn b Stop bit length 2 STOP Caution Do not write to asynchronous serial interface mode register n ASIMn during a transmit operation Writing to ASIMn during a transmit operation may disable further transmi...

Page 329: ...eted the receive data in the shift register is transferred to receive buffer register n RXBn and a receive completion interrupt INTSRn occurs Even if an error has occurred the receive data in which the error occurred is still transferred to RXBn When an error occurs INSTRn is generated if bit 1 ISRMn of ASIMn is cleared 0 On the other hand INTSRn is not generated if the ISRMn bit is set 1 If the R...

Page 330: ...Receive Error Causes Receive Error Cause ASISn Value Parity error Parity specification at transmission and receive data parity do not match 04H Framing error Stop bit is not detected 02H Overrun error Reception of subsequent data was completed before data was read from the receive buffer register 01H Figure 10 46 Receive Error Timing RxDn Input INTSRn Note D7 D6 D2 D1 D0 Parity STOP START INTSERn ...

Page 331: ... transmit shift register n TXSn and receive buffer register n RXBn are stopped and their values immediately before the clock stopped are hold The TXDn pin output holds the data immediately before the clock is stopped in STOP mode during transmission When the clock is stopped during reception the receive data until the clock stopped are stored and subsequent receive operation is stopped Reception r...

Page 332: ...h serial I O mode the processing time of data transfer is shortened MSB and LSB can be switched for the first bit of data to be transferred in serial The 3 wire variable length serial I O mode is useful when connecting to a peripheral I O device that includes a clocked serial interface a display controller etc 10 5 1 Configuration CSI4 includes the following hardware Table 10 11 Configuration of C...

Page 333: ... SIO4 is set by a 16 bit memory manipulation instruction The serial operation starts when data is written to or read from SIO4 while the bit 7 CSIE4 of variable length serial control register 4 CSIM4 is 1 When transmitting data written to SIO4 is output via the serial output SO4 When receiving data is read from the serial input SI4 and written to SIO4 RESET input clears SIO4 to 0000H Caution Do no...

Page 334: ...ster regardless of whether MSB or LSB is set for the first transfer bit Any data can be set to the unused higher bits however in this case the received data after a serial transfer operation becomes 0 Figure 10 49 When Transfer Bit Length Other Than 16 Bits Is Set a When transfer bit length is 10 bits and MSB first b When transfer bit length is 12 bits and LSB first SI4 SO4 15 10 9 0 Fixed to 0 SI...

Page 335: ...ial Control Register 4 CSIM4 After reset 00H R W Address FFFFF2E2H 7 6 5 4 3 2 1 0 CSIM4 CSIE4 0 0 0 0 MODE4 0 SCL4 SIO4 operation enable disable specification CSIE4 Shift register operation Serial counter Port 0 Operation disabled Clear Port function Note 1 1 Operation enabled Count operation enabled Serial function port function Note 2 Transfer operation mode flag MODE4 Operation mode Transfer s...

Page 336: ... Variable Length Serial Setting Register 4 CSIB4 After reset 00H R W Address FFFFF2E4H 7 6 5 4 3 2 1 0 CSIB4 0 CMODE DMODE DIR BSEL3 BSEL2 BSEL1 BSEL0 CMODE DMODE SCK4 active level SI4 interrupt timing SO4 output timing 0 0 Low level Rising edge of SCK4 Falling edge of SCK4 0 1 Low level Falling edge of SCK4 Rising edge of SCK4 1 0 High level Falling edge of SCK4 Rising edge of SCK4 1 1 High level...

Page 337: ...anipulation instruction RESET input clears BRGCN4 to 00H Figure 10 52 Baud Rate Generator Source Clock Selection Register 4 BRGCN4 After reset 00H R W Address FFFFF2E6H 7 6 5 4 3 2 1 0 BRGCN4 0 0 0 0 0 BRGN2 BRGN1 BRGN0 BRGN2 BRGN1 BRGN0 Source clock fSCK n 0 0 0 fXX 0 0 0 1 fXX 2 1 0 1 0 fXX 4 2 0 1 1 fXX 8 3 1 0 0 fXX 16 4 1 0 1 fXX 32 5 1 1 0 fXX 64 6 1 1 1 fXX 128 7 ...

Page 338: ...1 0 3 0 1 1 fSCK 6 3 1 1 1 1 1 1 0 fSCK 252 126 1 1 1 1 1 1 1 fSCK 254 127 The baud rate transmit receive clock that is generated is obtained by dividing the main clock Generation of baud rate transmit receive clock using main clock The transmit receive clock is obtained by dividing the main clock The following equation is used to obtain the baud rate from the main clock When 1 k 127 Baud rate Hz ...

Page 339: ...de SI4 SO4 and SCK4 can be used as normal I O ports a Register settings Operation stop mode is set via CSIE4 bit of variable length serial control register 4 CSIM4 While CSIE4 0 SIO4 operation stop state the pins connected to SI4 SO4 or SCK4 function as port pins Figure 10 54 CSIM4 Setting Operation Stop Mode After reset 00H R W Address FFFFF2E2H 7 6 5 4 3 2 1 0 CSIM4 CSIE4 0 0 0 0 MODE4 0 SCL4 SI...

Page 340: ... I O mode is set via variable length serial control register 4 CSIM4 Figure 10 55 CSIM4 Setting 3 Wire Variable Length Serial I O Mode After reset 00H R W Address FFFFF2E2H 7 6 5 4 3 2 1 0 CSIM4 CSIE4 0 0 0 0 MODE4 0 SCL4 SIO4 operation enable disable specification CSIE4 Shift register operation Serial counter Port 1 Operation enabled Count operation enabled Serial function port function Transfer ...

Page 341: ...DIR BSEL3 BSEL2 BSEL1 BSEL0 CMODE DMODE SCK4 active level SI4 interrupt timing SO4 output timing 0 0 Low level Rising edge of SCK4 Falling edge of SCK4 0 1 Low level Falling edge of SCK4 Rising edge of SCK4 1 0 High level Falling edge of SCK4 Rising edge of SCK4 1 1 High level Rising edge of SCK4 Falling edge of SCK4 DIR Serial transfer direction 0 LSB first 1 MSB first BSEL3 BSEL2 BSEL1 BSEL0 Bit...

Page 342: ...can change the attribute of the serial clock SCK4 and the phases of serial data SI4 and SO4 Figure 10 57 Timing of 3 Wire Variable Length Serial I O Mode SCK4 CMODE 0 SIO4 write SO4 DMODE 1 INTCSI4 SCK4 CMODE 1 SO4 DMODE 0 Remark An arrow shows the SI4 data fetch timing When CMODE 0 the serial clock SCK4 stops at the high level during the operation stop and outputs the low level during a data tran...

Page 343: ...Transmit transmit and receive mode MODE4 0 Transfer starts when writing to SIO4 Receive only mode Transfer starts when reading from SIO4 Caution After data has been written to SIO4 transfer will not start even if the CSIE4 bit value is set to 1 Completion of the final bit transfer automatically stops the serial transfer operation and sets the interrupt request flag INTCSI4 Figure 10 58 Timing of 3...

Page 344: ...ger input ADTRG rising edge falling edge or both rising and falling edges can be specified 2 Software start Conversion is started by setting A D converter mode register 1 ADM1 One analog input channel is selected from ANI0 to ANI11 and A D conversion is performed If A D conversion has been started by means of a hardware start conversion stops once it has been completed and an interrupt request INT...

Page 345: ...REF AVSS INTAD 4 ADS3 ADS2 ADS1 ADS0 ADCS TRG FR2 FR1 FR0 EGA1 EGA0 ADPS Selector Sample hold circuit AVSS Voltage comparator Tap selector ADTRG Edge detector Controller A D conversion result register ADCR Trigger enable Analog input channel specification register ADS A D converter mode register 1 ADM1 Internal bus IEAD A D converter mode register 2 ADM2 Successive approximation register SAR AVDD ...

Page 346: ...s loaded to this register from the successive approximation register The higher 10 bits of this register holds the result of the A D conversion the lower 6 bits are fixed to 0 This register is read using a 16 bit memory manipulation instruction RESET input sets ADCR to 0000H When using only higher 8 bits of the result of the A D conversion ADCRH is read using an 8 bit memory manipulation instructi...

Page 347: ... of the absolute maximum ratings is input to a channel the conversion value of the channel is undefined and the conversion values of the other channels may also be affected 7 AVREF pin This pin inputs a reference voltage to the A D converter The signals input to the ANI0 to ANI11 pins are converted into digital signals based on the voltage applied across AVREF and AVSS 8 AVSS pin This is the groun...

Page 348: ...version time of the input analog signal to be converted into a digital signal starting or stopping the conversion and an external trigger ADM is set by a 1 bit or 8 bit memory manipulation instruction RESET input clears ADM1 to 00H Figure 11 2 A D Converter Mode Register 1 ADM1 1 2 After reset 00H R W Address FFFFF3C0H 7 6 5 4 3 2 1 0 ADM1 ADCS TRG FR2 FR1 FR0 EGA1 EGA0 ADPS ADCS A D conversion co...

Page 349: ...ting prohibited 6 7 3 3 µs 1 0 1 1 60 fXX 30 fXX Setting prohibited Setting prohibited 1 1 0 0 48 fXX 24 fXX Setting prohibited Setting prohibited 1 1 0 1 36 fXX 18 fXX Setting prohibited Setting prohibited 1 1 1 0 Setting prohibited Setting prohibited Setting prohibited 1 1 1 1 12 fXX 6 fXX Setting prohibited Setting prohibited EGA1 EGA0 Valid edge specification for external trigger signal 0 0 No...

Page 350: ...S2 ADS1 ADS0 Analog Input Channel Specification 0 0 0 0 ANI0 0 0 0 1 ANI1 0 0 1 0 ANI2 0 0 1 1 ANI3 0 1 0 0 ANI4 0 1 0 1 ANI5 0 1 1 0 ANI6 0 1 1 1 ANI7 1 0 0 0 ANI8 1 0 0 1 ANI9 1 0 1 0 ANI10 1 0 1 1 ANI11 Other than above Setting prohibited 3 A D converter mode register 2 ADM2 ADM2 specifies connection disconnection of AVDD and AVREF ADM2 is set by a 1 bit or 8 bit memory manipulation instruction...

Page 351: ... If the analog input voltage is less than 1 2 AVREF the MSB is reset 6 Next bit 8 of the SAR is automatically set and the analog input voltage is compared again Depending on the value of bit 9 to which the result of the preceding comparison has been set the voltage tap of the series resistor string is selected as follows Bit 9 1 3 4 AVREF Bit 9 0 1 4 AVREF The analog input voltage is compared with...

Page 352: ...ion result Conversion result A D conversion is successively executed until bit 7 ADCS of A D converter mode register 1 ADM1 is reset to 0 by software If ADM1 and the analog input channel specification register ADS are written during A D conversion the conversion is initialized If ADCS is set to 1 at this time conversion is started from the beginning RESET input sets the A D conversion result regis...

Page 353: ... 0 5 INT Function that returns integer of value in VIN Analog input voltage AVREF AVREF pin voltage ADCR Value of the A D conversion result register ADCR The relationship between the analog input voltage and A D conversion result is shown below Figure 11 6 Relationship Between Analog Input Voltage and A D Conversion Result 1 1 3 2 5 3 2043 1022 20451023 2047 1 2048 102420481024 2048 1024 2048 1024...

Page 354: ...log input pin specified by the analog input channel specification register ADS into a digital signal When the A D conversion has been completed the result of the conversion is stored in the A D conversion result register ADCR and an interrupt request signal INTAD is generated Once the A D conversion has been started and completed conversion is not started again unless a new external trigger signal...

Page 355: ... INTAD is generated Once A D conversion has been started and completed the next conversion is started immediately A D conversion is repeated until new data is written to ADS If ADS is rewritten during A D conversion the conversion under execution is stopped and conversion of the newly selected analog input channel is started If data with ADCS set to 0 is written to ADM1 during A D conversion the c...

Page 356: ...HALT mode At this time the current consumption of the A D converter can be reduced by stopping the conversion by resetting the bit 7 ADCS of A D converter mode register 1 ADM1 to 0 To reduce the current consumption in the STOP and IDLE modes set the AVREF potential in the user circuit to the same value 0 V as the AVSS potential 2 Input range of ANI0 to ANI11 Keep the input voltage of the ANI0 to A...

Page 357: ...I11 The analog input ANI0 to ANI11 pins are multiplexed with port pins To execute A D conversion with any of ANI0 to ANI11 selected do not execute an instruction that inputs data to the port during conversion otherwise the resolution may drop If a digital pulse is applied to pins adjacent to the pin whose input signal is converted into a digital signal the expected A D conversion result may not be...

Page 358: ...st flag may be set immediately before ADS is rewritten If ADIF is read immediately after ADS has been rewritten it may be set despite the fact that conversion of the newly selected analog input signal has not been completed yet When stopping A D conversion and then resuming clear ADIF before resuming conversion Figure 11 10 A D Conversion End Interrupt Generation Timing Rewriting ADS ANIn conversi...

Page 359: ...AVDD pin as shown in Figure 11 11 Figure 11 11 Handling of AVDD Pin AVREF VDD VSS AVDD AVSS Main power supply Back up capacitor 9 Reading out A D converter result register ADCR A write operation to A D converter mode register 1 ADM1 and the analog input channel specification register ADS may cause the ADCR contents to be undefined After the conversion read out the conversion result before the writ...

Page 360: ...pt Request After a DMA transfer has occurred a specified number of times and the TCn bit in the corresponding DMA channel control register DCHCn has been set to 1 a DMA transfer completion interrupt request INTDMA0 to INTDMA5 occurs on each channel in relation to the interrupt controller 12 3 Control Registers 12 3 1 DMA peripheral I O address registers 0 to 5 DIOA0 to DIOA5 These registers are us...

Page 361: ...3A 70F3033AY V850 SB2 µPD703035A 703035AY 70F3035A 70F3035AY 16 KB 16 KB xxFFB000H to xxFFEFFFH V850 SB1 µPD703030A 703030AY V850 SB2 µPD703036A 703036AY 20 KB 12 KB xxFFA000H to xxFFBFFFH xxFFE000H to xxFFEFFFH V850 SB1 µPD703032A 703032AY 70F3032A 70F3032AY V850 SB2 µPD703037A 703037AY 70F3037A 70F3037AY 24 KB 16 KB xxFF9000H to xxFFBFFFH xxFFE000H to xxFFEFFFH An address is incremented after ea...

Page 362: ...g Value and Internal RAM 12 KB xxFFFFFFH xxFFC000H xxFFBFFFH xxFFF000H xxFFEFFFH xxFF8000H xxFF7FFFH Access prohibited area Expansion ROM area Internal peripheral I O area Internal RAM area DRAn setting value 2FFFH 0000H 12 KB usable for DMA Cautions 1 Do not set odd addresses for 16 bit transfer DCHCn register DSn 1 2 While the increment function is being used DCHCn register DDADn 0 if the DRAn r...

Page 363: ...Figure 12 4 Correspondence Between DRAn Setting Value and Internal RAM 16 KB xxFFFFFFH xxFFB000H xxFFAFFFH xxFFF000H xxFFEFFFH xxFF8000H xxFF7FFFH Access prohibited area Expansion ROM area Internal peripheral I O area Internal RAM area DRAn setting value 2FFFH 3000H 3FFFH xxFFC000H xxFFBFFFH 0000H 16 KB usable for DMA Caution Do not set odd addresses for 16 bit transfer DCHCn register DSn 1 Remark...

Page 364: ... xxFFF000H xxFFEFFFH xxFF8000H xxFF7FFFH Access prohibited area Expansion ROM area Internal peripheral I O area Internal RAM area DRAn setting value 0FFFH 2000H 0000H 3FFFH xxFFC000H xxFFBFFFH 8 KB usable for DMA 4 KB usable for DMA xxFFE000H xxFFDFFFH Cautions 1 Do not set odd addresses for 16 bit transfer DCHCn register DSn 1 2 While the increment function is being used DCHCn register DDADn 0 if...

Page 365: ...pondence Between DRAn Setting Value and Internal RAM 24 KB xxFFFFFFH xxFF9000H xxFF8FFFH xxFFF000H xxFFEFFFH xxFF8000H xxFF7FFFH Access prohibited area Expansion ROM area Internal peripheral I O area Internal RAM area DRAn setting value 0FFFH 1000H 0000H 3FFFH xxFFC000H xxFFBFFFH 12 KB usable for DMA 4 KB usable for DMA xxFFE000H xxFFDFFFH Caution Do not set odd addresses for 16 bit transfer DCHCn...

Page 366: ... written in 8 bit units Figure 12 7 Format of DMA Byte Count Registers 0 to 5 DBC0 to DBC5 After reset Undefined R W Address DBC0 FFFFF184H DBC3 FFFFF1B4H DBC1 FFFFF194H DBC4 FFFFF1C4H DBC2 FFFFF1A4H DBC5 FFFFF1D4H 7 6 5 4 3 2 1 0 DBCn BCn7 BCn6 BCn5 BCn4 BCn3 BCn2 BCn1 BCn0 n 0 to 5 Caution Values set to bit 0 are ignored during 16 bit transfers 12 3 4 DMA start factor expansion register DMAS Thi...

Page 367: ...6H 7 6 5 4 3 2 1 0 DCHCn TCn 0 DDADn TTYPn1 TTYPn0 TDIRn DSn ENn n 0 to 5 TCn DMA transfer completed not completed Note 1 0 Not completed 1 Completed DDADn Internal RAM address count direction control 0 Increment 1 Address is fixed Channel n DMAS2 DMAS1 DMAS0 TTYPn1 TTYPn0 DMA transfer start factor setting 0 0 INTCSI0 INTIIC0 Note 2 0 1 INTCSI1 INTSR0 1 0 INTAD 0 x x x 1 1 INTTM00 0 0 0 INTCSI0 IN...

Page 368: ...nternal RAM Note 3 0 From internal RAM to peripheral I Os 1 From peripheral I Os to internal RAM DSn Control of transfer data size for DMA transfer Note 3 0 8 bit transfer 1 16 bit transfer ENn Control of DMA transfer enable disable status Note 4 0 Disable 1 Enable reset to 0 after DMA transfer is completed Notes 1 TCn n 0 to 5 is set to 1 when a specified number of transfers are completed and is ...

Page 369: ...rt called a real time output port Because RTO can output signals without jitter it is suitable for controlling a stepping motor The real time output port can be set in port mode or real time output port mode in 1 bit units The block diagram of RTO is shown below Figure 13 1 Block Diagram of RTO Internal bus Output latch RTP7 RTP6 RTP5 RTP4 RTP3 RTP2 RTP1 RTP0 RTPOE RTPEG BYTE EXTR RTPTRG Output tr...

Page 370: ... as shown in Figure 13 2 If an operation mode of 4 bits 2 channels is specified data can be individually set to RTBL and RTBH The data of both the registers can be read all at once by specifying the address of either of the registers If an operation mode of 8 bits 1 channel is specified 8 bit data can be set to both RTBL and RTBH respectively by writing the data to either of the registers The data...

Page 371: ...using the following two types of registers Real time output port mode register RTPM Real time output port control register RTPC 1 Real time output port mode register RTPM This register selects real time output port mode or port mode in 1 bit units RTPM is set by an 8 1 bit memory manipulation instruction RESET input clears RTPM to 00H Figure 13 3 Format of Real Time Output Port Mode Register RTPM ...

Page 372: ...4 3 2 1 0 RTPC RTPOE RTPEG BYTE EXTR 0 0 0 0 RTPOE Control of operation of real time output port 0 Disables operation Note 1 Enables operation RTPEG Valid edge of RTPTRG 0 Falling edge 1 Rising edge BYTE Operation mode of real time output port 0 4 bits 2 channels 1 8 bits 1 channel EXTR Control of real time output by RTPTRG signal 0 Does not use RTPTRG as real time output trigger 1 Uses RTPTRG as ...

Page 373: ...register RTPM is output from the bits of RTP0 to RTP7 The bits specified in the port mode by RTPM output 0 If the real time output operation is disabled by clearing RTPOE to 0 RTP0 to RTP7 output 0 regardless of the setting of RTPM Note EXTR Bit 4 of the real time output port control register RTPC BYTE Bit 5 of the real time output port control register RTPC Figure 13 5 Example of Operation Timing...

Page 374: ...fer registers RTBH and RTBL 3 Enable the real time output operation Set RTPOE to 1 4 Set the output latch of ports P100 to P107 to 0 and the next output to RTBH and RTBL until the selected transfer trigger is generated 5 Set the next real time output value to RTBH and RTBL by interrupt servicing corresponding to the selected trigger 13 6 Cautions 1 Before performing initialization disable the real...

Page 375: ...t I O port for which I O settings can be controlled in 1 bit units A pull up resistor can be connected in 1 bit units software pull up function When using P00 to P04 as the NMI or INTP0 to INTP3 pins noise is eliminated by the analog noise eliminator When using P05 to P07 as the INTP4 ADTRG INTP5 RTPTRG and INTP6 pins noise is eliminated by the digital noise eliminator Figure 14 1 Format of Port 0...

Page 376: ...f NMI and INTP0 to INTP6 are specified via rising edge specification register 0 EGP0 and falling edge specification register 0 EGN0 A pull up resistor can be connected in 1 bit units when specified via pull up resistor option register 0 PU0 When a reset is input the settings are initialized to input mode Also the valid edge of each interrupt request becomes invalid NMI and INTP0 to INTP6 do not fu...

Page 377: ...mination is not performed when these pins are used as an ordinary input port 3 Control registers a Port 0 mode register PM0 PM0 can be read written in 8 1 bit units Figure 14 2 Port 0 Mode Register PM0 After reset FFH R W Address FFFFF020H 7 6 5 4 3 2 1 0 PM0 PM07 PM06 PM05 PM04 PM03 PM02 PM01 PM00 PM0n Control of I O mode n 0 to 7 0 Output mode 1 Input mode b Pull up resistor option register 0 PU...

Page 378: ...ng edge 1 Interrupt request signal occurs at rising edge Remark n 0 Control of NMI pin n 1 to 7 Control of INTP0 to INTP6 pins d Falling edge specification register 0 EGN0 EGN0 can be read written in 8 1 bit units Figure 14 5 Falling Edge Specification Register 0 EGN0 After reset 00H R W Address FFFFF0C2H 7 6 5 4 3 2 1 0 EGN0 EGN07 EGN06 EGN05 EGN04 EGN03 EGN02 EGN01 EGN00 EGN0n Control of falling...

Page 379: ... to P07 P ch WRPM WRPORT RD WRPU VDD P00 NMI P01 INTP0 P02 INTP1 P03 INTP2 P04 INTP3 P05 INTP4 ADTRG P06 INTP5 RTPTRG P07 INTP6 Selector PU0n PU0 Output latch P0n PM0n PM0 Internal bus Remarks 1 PU0 Pull up resistor option register 0 PM0 Port 0 mode register RD Port 0 read signal WR Port 0 write signal 2 n 0 to 7 ...

Page 380: ...the P1 register is read the pin levels at that time are read Writing to P1 writes the values to that register This does not affect the input pins In output mode When the P1 register is read the P1 register s values are read Writing to P1 writes the values to that register and those values are immediately output Port 1 includes the following alternate functions SDA0 and SCL0 pins are available only...

Page 381: ...n specified via pull up resistor option register 1 PU1 Clear the P1 and PM1 registers to 0 when using alternate function pins as outputs The ORed result of the port output and the alternate function pin is output from the pins When a reset is input the settings are initialized to input mode 2 Control registers a Port 1 mode register PM1 PM1 can be read written in 8 1 bit units Figure 14 8 Port 1 M...

Page 382: ...rain output Note Bit 3 is fixed as a normal output 3 Block diagram Port 1 Figure 14 11 Block Diagram of P10 to P12 P14 and P15 P ch WRPM WRPF WRPORT RD WRPU VDD VDD Selector PF1n PF1 PM1n PM1 PU1n PU1 P ch N ch Internal bus Output latch P1n Alternate function P10 SI0 SDA0Note P11 SO0 P12 SCK0 SCL0Note P14 SO1 TxD0 P15 SCK1 ASCK0 Note The SDA0 SCL0 pins apply only to the µPD70303xAY and 70F303wAY R...

Page 383: ...re 14 12 Block Diagram of P13 P ch WRPM WRPORT RD WRPU VDD Selector Output latch P13 PM13 PM1 PU13 PU1 Internal bus Alternate function P13 SI1 RxD0 Remark PU1 Pull up resistor option register 1 PM1 Port 1 mode register RD Port 1 read signal WR Port 1 write signal ...

Page 384: ... 1 Outputs 1 Remark In input mode When the P2 register is read the pin levels at that time are read Writing to P2 writes the values to that register This does not affect the input pins In output mode When the P2 register is read the P2 register s values are read Writing to P2 writes the values to that register and those values are immediately output Port 2 includes the following alternate function...

Page 385: ...while in output mode A pull up resistor can be connected in 1 bit units when specified via pull up resistor option register 2 PU2 When using the alternate function as TI2 and TI3 pins noise elimination is provided by a digital noise eliminator same as digital noise eliminator for port 0 Clear the P2 and PM2 registers to 0 when using alternate function pins as outputs The ORed result of the port ou...

Page 386: ... 0 PU2 PU27 PU26 PU25 PU24 PU23 PU22 PU21 PU20 PU2n Control of on chip pull up resistor connection n 0 to 7 0 Do not connect 1 Connect c Port 2 function register PF2 PF2 can be read written in 8 1 bit units Figure 14 16 Port 2 Function Register PF2 After reset 00H R W Address FFFFF0A4H 7 6 5 4 3 2 1 0 PF2 0 0 PF25 PF24 0 PF22 PF21 PF20 PF2n Control of normal output N ch open drain output n 0 to 2 ...

Page 387: ...n PF2 PM2n PM2 PU2n PU2 P ch N ch Internal bus Output latch P2n Alternate function P20 SI2 SDA1Note P21 SO2 P22 SCK2 SCL1Note P24 SO3 TxD1 P25 SCK3 ASCK1 Note The SDA1 SCL1 pins apply only to the µPD70303xAY and 70F303wAY Remarks 1 PU2 Pull up resistor option register 2 PF2 Port 2 function register PM2 Port 2 mode register RD Port 2 read signal WR Port 2 write signal 2 n 0 to 2 4 5 ...

Page 388: ... Diagram of P23 P26 and P27 P ch WRPM WRPORT RD WRPU VDD Selector Output latch P13 PM13 PM1 PU13 PU1 Internal bus Alternate function P13 SI1 RxD0 Remarks 1 PU2 Pull up resistor option register 2 PM2 Port 2 mode register RD Port 2 read signal WR Port 2 write signal 2 n 3 6 or 7 ...

Page 389: ... data In output mode n 0 to 7 0 Outputs 0 1 Outputs 1 Remark In input mode When the P3 register is read the pin levels at that time are read Writing to P3 writes the values to that register This does not affect the input pins In output mode When the P3 register is read the P3 register s values are read Writing to P3 writes the values to that register and those values are immediately output Port 3 ...

Page 390: ...for port 0 When using the alternate function as A13 to A15 pins set the pin functions via the memory address output mode register MAM At this time be sure to set the PM3 registers PM34 PM35 PM36 and the P3 registers P34 P35 P36 to 0 Clear the P3 and PM3 registers to 0 when using alternate function pins as outputs The ORed result of the port output and the alternate function pin is output from the ...

Page 391: ...mal output N ch open drain output n 3 4 0 Normal output 1 N ch open drain output 3 Block diagram Port 3 Figure 14 23 Block Diagram of P30 to P32 and P35 to P37 P ch WRPM WRPORT RD WRPU VDD Selector Output latch P3n PM3n PM3 PU3n PU3 Internal bus Alternate function P30 TI00 P31 TI01 P32 TI10 SI4 P35 TO1 A14 P36 TI4 TO4 A15 P37 TI5 TO5 Remarks 1 PU3 Pull up resistor option register 3 PM3 Port 3 mode...

Page 392: ... WRPF WRPORT RD WRPU VDD VDD Selector PF3n PF3 PM3n PM3 PU3n PU3 P ch N ch Internal bus Output latch P3n Alternate function P33 TI11 SO4 P34 TO0 A13 SCK4 Remarks 1 PU3 Pull up resistor option register 3 RF3 Port 3 function register PM3 Port 3 mode register RD Port 3 read signal WR Port 3 write signal 2 n 3 4 ...

Page 393: ...pin levels at that time are read Writing to P4 and P5 writes the values to those registers This does not affect the input pins In output mode When the P4 and P5 registers are read their values are read Writing to P4 and P5 writes the values to those registers and those values are immediately output Ports 4 and 5 include the following alternate functions Table 14 6 Alternate Function Pins of Ports ...

Page 394: ... can be read by reading the P4 and P5 registers while in output mode A software pull up function is not implemented When using the alternate function as AD0 to AD15 set the pin functions via the memory expansion register MM This does not affect the PM4 and PM5 registers When a reset is input the settings are initialized to input mode 2 Control register a Port 4 mode register and port 5 mode regist...

Page 395: ...Block diagram Ports 4 and 5 Figure 14 27 Block Diagram of P40 to P47 and P50 to P57 WRPM WRPORT RD Selector Output latch mn PMmn PMm Internal bus Pmn ADx Remarks 1 PMm Port m mode register RD Port m read signal WR Port m write signal 2 m 4 5 n 0 to 7 x 0 to 15 ...

Page 396: ...ode When the P6 register is read the pin levels at that time are read Writing to P6 writes the values to that register This does not affect the input pins In output mode When the P6 register is read the P6 register s values are read Writing to P6 writes the values to that register and those values are immediately output Port 6 includes the following alternate functions Table 14 7 Port 6 Alternate ...

Page 397: ... output latch values can be read by reading the P6 register while in output mode A software pull up function is not implemented When using the alternate function as A16 to A21 set the pin functions via the memory expansion register MM This does not affect the PM6 register When a reset is input the settings are initialized to input mode 2 Control register a Port 6 mode register PM6 PM6 can be read ...

Page 398: ...0EJ4V0UM 398 3 Block diagram Port 6 Figure 14 30 Block Diagram P60 to P65 WRPM WRPORT RD Selector Output latch P6n PM6n PM6 Internal bus P6n Ax Remarks 1 PM6 Port 6 mode register RD Port 6 read signal WR Port 6 write signal 2 n 0 to 5 x 16 to 21 ...

Page 399: ... P71 P70 P7n Pin level n 0 to 7 0 1 Read pin level of bit n After reset Undefined R Address FFFFF010H 7 6 5 4 3 2 1 0 P8 0 0 0 0 P83 P82 P81 P80 P8n Pin level n 0 to 3 0 1 Read pin level of bit n Ports 7 and 8 include the following alternate functions Table 14 8 Alternate Function Pins of Ports 7 and 8 Pin Name Alternate Function I O PULL Note Remark Port 7 P70 ANI0 Input No P71 ANI1 P72 ANI2 P73 ...

Page 400: ...s P7 and P8 Data cannot be written to P7 or P8 A software pull up function is not implemented Values read from pins specified as analog inputs are undefined values Do not read values from P7 or P8 during A D conversion 2 Block diagram Ports 7 and 8 Figure 14 32 Block Diagram of P70 to P77 and P80 to P83 Pmn ANIx RD Internal bus Remarks 1 RD Port 7 port 8 read signals 2 m 7 8 n 0 to 7 m 7 0 to 3 m ...

Page 401: ... P9 register is read the pin levels at that time are read Writing to P9 writes the values to that register This does not affect the input pins In output mode When the P9 register is read the P9 register s values are read Writing to P9 writes the values to that register and those values are immediately output Port 9 includes the following alternate functions Table 14 9 Port 9 Alternate Function Pin...

Page 402: ...egister output latch values can be read by reading the P9 register while in output mode A software pull up function is not implemented When using the P9 for control signals in expansion mode set the pin functions via the memory expansion mode register MM When a reset is input the settings are initialized to input mode 2 Control register a Port 9 mode register PM9 PM9 can be read written in 1 bit o...

Page 403: ...ort 9 Figure 14 35 Block Diagram of P90 to P96 WRPM WRPORT RD Selector Output latch P9n PM9n PM9 Internal bus P90 LBEN WRL P91 UBEN P92 R W WRH P93 DSTB RD P94 ASTB P95 HLDAK P96 HLDRQ Remarks 1 PM9 Port 9 mode register RD Port 9 read signal WR Port 9 write signal 2 n 0 to 6 ...

Page 404: ...puts 1 Remark In input mode When the P10 register is read the pin levels at that time are read Writing to P10 writes the values to that register This does not affect the input pins In output mode When the P10 register is read the P10 register s values are read Writing to P10 writes the values to that register and those values are immediately output Port 10 includes the following alternate function...

Page 405: ...1 bit units when specified via pull up resistor option register 10 PU10 When using the alternate function as A5 to A12 pins see the pin functions via the memory address output mode register MAM At this time be sure to set P10 and PM10 to 0 When used as KR0 to KR7 pins noise is eliminated by the analog noise eliminator Clear the P10 and PM10 registers to 0 when using alternate function pins as outp...

Page 406: ... PU106 PU105 PU104 PU103 PU102 PU101 PU100 PU10n Control of on chip pull up resistor connection n 0 to 7 0 Do not connect 1 Connect c Port 10 function register PF10 PF10 can be read written in 8 1 bit units Figure 14 39 Port 10 Function Register PF10 After reset 00H R W Address FFFFF0B4H 7 6 5 4 3 2 1 0 PF10 PF107 PF106 PF105 PF104 PF103 PF102 PF101 PF100 PF10n Control of normal output N ch open d...

Page 407: ...rnal bus Output latch P10n Alternate function P100 RTP0 A5 KR0 P101 RTP1 A6 KR1 P102 RTP2 A7 KR2 P103 RTP3 A8 KR3 P104 RTP4 A9 KR4 IERXNote P105 RTP5 A10 KR5 IETXNote P106 RTP6 A11 KR6 P107 RTP7 A12 KR7 Note The IERX IETX pins apply only to the V850 SB2 Remarks 1 PU10 Pull up resistor option register 10 RF10 Port 10 function register PM10 Port 10 mode register RD Port 10 read signal WR Port 10 wri...

Page 408: ...1 0 0 0 Undefined P113 P112 P111 P110 P11n Control of output data in output mode n 0 to 3 0 Outputs 0 1 Outputs 1 Remark In input mode When the P11 register is read the pin levels at that time are read Writing to P11 writes the values to that register This does not affect the input pins In output mode When the P11 register is read the P11 register s values are read Writing to P11 writes the values...

Page 409: ...tion register 11 PU11 The on off of wait function can be switched with a port alternate function control register PAC When using the alternate function as A1 to A4 pins set the pin functions via the memory address output mode register MAM At this time be sure to clear P11 and PM11 to 0 When a reset is input the settings are initialized to input mode Caution A wait function generated by the WAIT pi...

Page 410: ... 4 3 2 1 0 PU11 0 0 0 0 PU113 PU112 PU111 PU110 PU11n Control of on chip pull up resistor connection n 0 to 3 0 Do not connect 1 Connect c Port alternate function control register PAC PAC can be read written in 8 1 bit units Figure 14 44 Port Alternate Function Control Register PAC After reset 00H R W Address FFFFF040H 7 6 5 4 3 2 1 0 PAC 0 0 0 0 0 0 0 WAC P120 Control of output data in output mod...

Page 411: ... Block Diagram of P110 to P113 P ch WRPM WRPORT RD WRPU VDD Selector PU11n PU11 Output latch P11n PM11n PM11 Internal bus P110 A1 WAIT P111 A2 P112 A3 P113 A4 Remarks 1 PU11 Pull up resistor option register 11 PM11 Port 11 mode register RD Port 11 read signal WR Port 11 write signal 2 n 0 to 3 ...

Page 412: ...ut PM02 1 Setting not needed for P02 P03 INTP2 Input PM03 1 Setting not needed for P03 P04 INTP3 Input PM04 1 Setting not needed for P04 INTP4 Input P05 ADTRG Input PM05 1 Setting not needed for P05 INTP5 Input P06 RTPTRG Input PM06 1 Setting not needed for P06 P07 INTP6 Input PM07 1 Setting not needed for P07 SI0 Input PM10 1 Setting not needed for P10 P10 SDA0 Note I O PM10 0 P10 0 P11 SO0 Outpu...

Page 413: ...24 TXD1 Output PM24 0 P24 0 Input PM25 1 Setting not needed for P25 SCK3 Output PM25 0 P25 0 P25 ASCK1 Input PM25 1 Setting not needed for P25 TI2 Input PM26 1 Setting not needed for P26 P26 TO2 Output PM26 0 P26 0 TI3 Input PM27 1 Setting not needed for P27 P27 TO3 Output PM27 0 P27 0 P30 TI00 Input PM30 1 Setting not needed for P30 P31 TI01 Input PM31 1 Setting not needed for P31 TI10 Input P32 ...

Page 414: ...1 MM P60 to P65 A16 to A21 Output Setting not needed for PM60 to PM65 Setting not needed for P60 to P65 Refer to Figure 3 21 MM P70 to P77 ANI0 to ANI7 Input None Setting not needed for P70 to P77 P80 to P83 ANI8 to ANI11 Input None Setting not needed for P80 to P83 LBEN Output P90 WRL Output Setting not needed for PM90 Setting not needed for P90 Refer to Figure 3 21 MM P91 UBEN Output Setting not...

Page 415: ...Input PM106 PM107 1 Setting not needed for P106 and P107 A1 Output PM110 0 P110 0 Refer to Figure 3 22 MAM P110 WAIT Input PM110 1 Setting not needed for P110 WAC 1 PAC P111 to P113 A2 to A4 Output PM111 to PM113 0 P111 to P113 0 Refer to Figure 3 22 MAM Note Only for the V850 SB2 Cautions 1 When changing the output level of port 0 by setting the port 0 s port function output mode the interrupt re...

Page 416: ...e related malfunction of the RESET pin 15 2 Pin Operations During the system reset period high impedance is set at almost all pins all pins except for RESET X2 XT2 REGC AVREF VDD VSS AVDD AVSS BVDD BVSS EVDD EVSS and VPP IC Accordingly if connected to an external memory device be sure to attach a pull up or pull down resistor for each pin If such a resistor is not attached high impedance will be s...

Page 417: ...or 3 0 V V850 SB2 Refer to 2 4 I O Circuit Types I O Buffer Power Supply and Connection of Unused Pins for the power supply corresponding to each pin Figure 16 1 Regulator A D converter 4 5 V to 5 5 V AVDD Main Sub oscillators On chip digital circuit 3 3 V V850 SB1 3 0 V V850 SB2 Regulator V DD BVDD EVDD Flash memory 3 0 V to 5 5 V 3 0 V to 5 5 V Bi directional level shifter EVDD system I O buffer...

Page 418: ...truction bugs found in the mask ROM can be avoided and program flow can be changed by using the ROM correction function Up to four correction addresses can be specified Cautions 1 The ROM correction function cannot be used for the data in the internal ROM it can only be used for instruction codes If ROM correction is carried out on data that data will replace the instruction code of the JMP r0 ins...

Page 419: ... matches the fetch address n 0 to 3 Whether match detection by a comparator is enabled or disabled can be set for each channel CORCN can be set by a 1 bit or 8 bit memory manipulation instruction Figure 17 2 Correction Control Register CORCN After reset 00H R W Address FFFFF36CH 7 6 5 4 3 2 1 0 CORCN 0 0 0 0 COREN3 COREN2 COREN1 COREN0 CORENn CORADn register and fetch address match detection contr...

Page 420: ...h address At this time the program can judge the following cases by reading CORRQ Reset input CORRQ 00H ROM correction generation CORRQn bit 1 n 0 to 3 Branch to 00000000H by user program CORRQ 00H Figure 17 3 Correction Request Register CORRQ After reset 00H R W Address FFFFF36EH 7 6 5 4 3 2 1 0 CORRQ 0 0 0 0 CORRQ3 CORRQ2 CORRQ1 CORRQ0 CORRQn Channel n ROM correction request flag 0 No ROM correc...

Page 421: ...ng on the product set the correction address within following ranges µPD703031A 703031AY 703034A 703034AY 128 KB 00000000H to 0001FFFEH µPD703033A 703033AY 703035A 703035AY 256 KB 00000000H to 0003FFFEH µPD703030A 703030AY 703036A 703036AY 384 KB 00000000H to 0005FFFEH µPD703032A 703032AY 703037A 703037AY 512 KB 00000000H to 0007FFFEH Bits 0 and 20 to 31 should be fixed to 0 Figure 17 4 Correction...

Page 422: ...address of the internal RAM that stores the correction code of channel n should be preset before the instruction that makes the program jump to this address is stored in the internal ROM Executed by a program stored in the internal ROM Executed by a program stored in the internal RAM Executed by the ROM correction function Caution Check the ROM correction generation from the vector table with a hi...

Page 423: ...he target system on board The dedicated flash programmer is connected to the target system to perform writing The following can be considered as the development environment and the applications using a flash memory Software can be altered after the V850 SB1 or V850 SB2 is solder mounted on the target system Small scale production of various models is made easier by differentiating software Data ad...

Page 424: ...000000H to xx01FFFFH 128 KB is erased Area 1 The area of xx020000H to xx03FFFFH 128 KB is erased Area 2 The area of xx040000H to xx05FFFFH 128 KB is erased Area 3 The area of xx060000H to xx07FFFFH 128 KB is erased 18 1 2 Write read time The write read time is shown below Write time 50 µs byte Read time 50 ns cycle time 18 2 Writing with Flash Programmer Writing can be performed either on board or...

Page 425: ...flash programmer UART0 or CSI0 is used for the interface between the dedicated flash programmer and the V850 SB1 or V850 SB2 to perform writing erasing etc A dedicated program adapter FA Series required for off board writing 18 4 Communication System The communication between the dedicated flash programmer and the V850 SB1 or V850 SB2 is performed by serial communication using UART0 or CSI0 of the...

Page 426: ...Serial clock Up to 1 MHz MSB first Figure 18 4 Communication with Dedicated Flash Programmer CSI0 HS V850 SB1 V850 SB2 RESET VSS VDD VPP Dedicated flash programmer SO0 SI0 VPP VDD GND RESET SI SO SCK0 SCK P15 HS The dedicated flash programmer outputs the transfer clock and the V850 SB1 and V850 SB2 operate as slaves When the PG FP3 is used as the dedicated flash programmer it generates the followi...

Page 427: ...VDD I O VDD voltage generation voltage monitoring VDD GND Ground VSS CLK Note Output Clock output to V850 SB1 V850 SB2 X1 RESET Output Reset signal RESET SI RxD Input Receive signal SO0 TxD0 SO TxD Output Transmit signal SI0 RxD0 SCK Output Transfer clock SCK0 HS Input Handshake signal of CSI0 HS P15 Note Supply clocks on the target board Remark Always connected Does not need to be connected if ge...

Page 428: ...nowledge the output high impedance status 18 5 1 VPP pin In the normal operation mode 0 V is input to the VPP pin In the flash memory programming mode a 7 8 V write voltage is supplied to the VPP pin The following shows an example of the connection of the VPP pin Figure 18 5 VPP Pin Connection Example VPP Dedicated flash programmer connection pin Pull down resistor RVPP V850 SB1 V850 SB2 18 5 2 Se...

Page 429: ...olate the connection to the other device or set the other device to the output high impedance status Figure 18 6 Conflict of Signals Serial Interface Input Pin V850 SB1 V850 SB2 Other device Output pin Conflict of signals Input pin In the flash memory programming mode the signal that the dedicated flash programmer sends out conflicts with signals another device outputs Therefore isolate the signal...

Page 430: ... so that the input signal to the other device is ignored Figure 18 7 Malfunction of Other Device V850 SB1 V850 SB2 Pin In the flash memory programming mode if the signal the V850 SB1 or V850 SB2 outputs affects the other device isolate the signal on the other device side Other device Input pin Dedicated flash programmer connection pin V850 SB1 V850 SB2 Pin In the flash memory programming mode if t...

Page 431: ...signals In the flash memory programming mode the signal the reset signal generator outputs conflicts with the signal the dedicated flash programmer outputs Therefore isolate the signals on the reset signal generator side Dedicated flash programmer connection pin 18 5 4 Port pins including NMI When the flash memory programming mode is set all the port pins except the pins that communicate with the ...

Page 432: ...18 6 1 Flash memory control The following shows the procedure for manipulating the flash memory Figure 18 9 Procedure for Manipulating Flash Memory Supplies RESET pulse Switch to flash memory programming mode Select communication system Manipulate flash memory End No Yes End Start ...

Page 433: ... set the V850 SB1 or V850 SB2 in the flash memory programming mode When switching modes set the VPP pin before releasing reset When performing on board writing change modes using a jumper etc Figure 18 10 Flash Memory Programming Mode VPP RESET Flash memory programming mode 7 8 V 3 V 0 V 1 2 n VPP Operation Mode 0 V Normal operation mode 7 8 V Flash memory programming mode ...

Page 434: ... CSI0 HS V850 SB1 and V850 SB2 perform slave operation MSB first 8 UART0 Communication rate 9600 bps at reset LSB first Others RFU Setting prohibited Caution When UART is selected the receive clock is calculated based on the reset command sent from the dedicated flash programmer after receiving the VPP pulse 18 6 4 Communication command The V850 SB1 and V850 SB2 communicate with the dedicated flas...

Page 435: ...m setting and control Status read out command Acquires the status of operations Oscillating frequency setting command Sets the oscillation frequency Erasing time setting command Sets the erasing time of one shot erase Writing time setting command Sets the writing time of data write Write back time setting command Sets the write back time Baud rate setting command Sets the baud rate when using UART...

Page 436: ...unication between one unit and plural units can be performed as follows Group unit broadcasting communication Broadcasting communication to group units All unit broadcasting communication Broadcasting communication to all units 3 Effective transfer rate The effective transfer rate is in mode 1 the V850 SB2 does not support modes 0 and 2 for the effective transfer rate Mode 1 Approx 17 Kbps Caution...

Page 437: ...om one unit to plural units takes precedence over normal communication communication from one unit to another 2 Priority by master address If the communication type is the same communication with the lower master address takes precedence A master address consists of 12 bits with unit 000H having the highest priority and unit FFFH having the lowest priority 19 1 3 Communication mode Although the IE...

Page 438: ...e plural slave units exist the slave units do not return an acknowledge signal during communication Whether broadcasting communication or normal communication is to be executed is selected by broadcasting bit for this bit refer to 19 1 6 2 Broadcasting bit Broadcasting communication is classified into two types group unit broadcasting communication and all unit broadcasting communication Group uni...

Page 439: ... complete the unit starts outputting the broadcasting bit in synchronization with the completion of the start bit output by the other unit The units other than the one that has started communication detect this start bit and enter the reception status 2 Broadcasting bit This bit indicates whether the master selects one slave individual communication or plural slaves broadcasting communication as t...

Page 440: ... the data on the bus as a result of comparison it is assumed that the master has lost in arbitration As a result the master stops transmission and enters the reception status Because the IEBus is configured of wired AND the unit having the minimum master address of the units participating in arbitration arbitration masters wins in arbitration After a 12 bit master address has been output only one ...

Page 441: ...ve address is FFFH All unit broadcasting communication If slave address is other than FFFH Group unit broadcasting communication Remark The group No during group unit broadcasting communication is the value of the higher 4 bits of the slave address If one unit occupies the bus as the master the address set by the slave address register SAR is output Figure 19 3 Slave Address Field Slave address fi...

Page 442: ... and locks Note 2 1 0 1 1 Writes data and locks Note 2 1 1 0 0 Undefined 1 1 0 1 Undefined 1 1 1 0 Writes command 1 1 1 1 Writes data Notes 1 The telegraph length bit of the telegraph length field and data transfer direction of the data field change as follows depending on the value of bit 3 MSB If bit 3 is 1 Transfer from master unit to slave unit If bit 3 is 0 Transfer from slave unit to master ...

Page 443: ...ds lock address lower 8 bits 0 0 0 1 Reads lock address higher 4 bits Moreover units for which lock is not set by the master unit reject acknowledgement and do not output an acknowledge bit when the control data shown in Table 19 4 is acknowledged Table 19 4 Control Field for Unlocked Slave Unit Bit 3 Bit 2 Bit 1 Bit 0 Function 0 1 0 0 Lock address read lower 8 bits 0 1 0 1 Lock address read highe...

Page 444: ...ceived Control Data Communication Target SLVRQ Slave Specification 1 No Specification 0 Lock Status LOCK Lock 1 Unlock 0 Master Unit Identification Match with PAR Lock Request Unit 1 Other 0 Slave Transmission Enable ENSLVTX Slave Reception Enable ENSLVRX 0H 3H 4H 5H 6H 7H 0 0 1 don t care don t care 1 1 1 1 don t care Other than above Caution If the received control data is other than the data sh...

Page 445: ...ster unit and the synchronization signals of bits are output by the master unit When the slave unit detects that the parity is even it outputs the acknowledge signal and starts outputting the data field During broadcasting communication however the slave unit does not output the acknowledge signal If the parity is odd the slave unit judges that the telegraph length bit has not been correctly recei...

Page 446: ...e configuration of the data field is as shown below Figure 19 6 Data Field Data field number specified by telegraph length field MSB LSB One data ACK Parity Control bit 8 bits ACK Parity Following the data bit the parity bit and acknowledge bit are respectively output by the master unit and slave unit Use broadcasting communication only for when the master unit transmits data At this time the ackn...

Page 447: ...ng broadcasting communication the slave unit judges that reception has not been performed correctly and stops reception b When master receives data When the master unit reads data from a slave unit the master unit outputs a sync signal corresponding to all the read bits The slave unit outputs the contents of the data and parity bits to the bus in response to the sync signal from the master unit Th...

Page 448: ...f the following cases and transmission is stopped If the parity of the control bit is incorrect If control bit 3 is 1 write operation when the slave reception enable flag ENSLVRX is not set 1 Note If the control bit indicates reading of data 3H or 7H when the slave transmission enable flag ENSLVTX is not set 1 Note If a unit other than that has set locking requests 3H 6H 7H AH BH EH or FH of the c...

Page 449: ...n the IEBus data register DR and no more data can be received Note Note In this case when the communication executed is individual communication if the maximum number of transmit bytes is within the value that can be transmitted in one frame the transmission side executes transmission of that data field again For broadcasting communication the transmission side does not execute transmission again ...

Page 450: ...ter DR Bit 2 Meaning 0 Unit is not locked 1 Unit is locked Bit 3 Meaning 0 Fixed to 0 Bit 4 Note 3 Meaning 0 Slave transmission is stopped 1 Slave transmission is ready Bit 5 Meaning 0 Fixed to 0 Bit 7 Bit 6 Meaning 0 0 Mode 0 0 1 Mode 1 1 0 Mode 2 1 1 Not used Indicates the highest mode supported by unit Note 4 Notes 1 After reset Bit 0 is set to 1 2 The receive buffer size is 1 byte 3 When the V...

Page 451: ...r than the one that has locked the unit does not receive broadcasting communication A unit is locked or unlocked as follows a Locking If the communication frame is completed without succeeding to transmit or receive data of the number of bytes specified by the telegraph length bit after the telegraph length field has been transmitted or received ACK 0 by the control bit that specifies locking 3H A...

Page 452: ...p to the maximum number of transfer bytes without being output 19 1 8 Bit format The format of the bits constituting the communication frame of the IEBus is shown below Figure 19 9 Bit Format of IEBus Logic 1 Logic 0 Preparation period Synchronization period Data period Stop period Preparation period First low level logic 1 period Synchronization period Next high level logic 0 period Data period P...

Page 453: ...rator Contention detection ACK generation Parity generation error detection TX RX Interrupt controller Interrupt control block INT request CPU interface block Internal registers handler DMA transfer IEBus interface block CLK Bit processing block Field processing block Internal bus R W PSR 8 bits 8 5 8 12 12 12 Internal bus 8 12 1 Hardware configuration and function The IEBus mainly consists of the...

Page 454: ...l registers refer to 19 3 Internal Registers of IEBus Controller d Bit processing block This block generates and disassembles bit timing and mainly consists of a bit sequence ROM 8 bit preset timer and comparator e Field processing block This block generates each field in the communication frame and mainly consists of a field sequence ROM 4 bit down counter and comparator f IEBus interface block T...

Page 455: ...s unit address register UAR FFFFF3E4H IEBus slave address register SAR R W FFFFF3E6H IEBus partner address register PAR R 0000H FFFFF3E8H IEBus control data register CDR FFFFF3EAH IEBus telegraph length register DLR 01H FFFFF3ECH IEBus data register DR R W FFFFF3EEH IEBus unit status register USR R FFFFF3F0H IEBus interrupt status register ISR R W 00H FFFFF3F2H IEBus slave status register SSR 41H ...

Page 456: ... IEBus is operating as the master writing to the BCR register including bit manipulation instructions is disabled until either the end of that communication or frame or until communication is stopped by the occurrence of an arbitration loss communication error Master requests cannot therefore be multiplexed However if the IEBus is specified as a slave while a master request is being held pending t...

Page 457: ... should be resent by software following a loss in arbitration When resending the master request in this case set 1 the MSTRQ flag after securing the required wait period This flag is unable to be set 1 before the end of this wait period INTIE2 interrupt signal Start interrupt generation Forcible reset period Wait period 61 7 s MAX µ MSTRQ flag reset signal 2 When a master request has been sent and...

Page 458: ...d and communication continued when the control data of a slave status request is returned even if the ENSLVTX flag is in the reset status e Slave reception enable flag ENSLVRX Bit 3 Set reset conditions Set By software Reset By software Caution If the ENSLVRX flag is reset when the IEBus is busy with other CPU processing NACK will be returned via the acknowledge bit of the control field making it ...

Page 459: ...rmat 15 0 14 0 13 0 12 0 UAR 11 10 9 8 7 6 5 4 3 2 1 0 Address FFFFF3E2H After reset 0000H R W R W 3 IEBus slave address register SAR During master request the value of this register is reflected in the value of the transmit data in the slave address field This register must be always set before starting communication Sets the slave address 12 bits to bits 11 to 0 Figure 19 13 IEBus Slave Address ...

Page 460: ...ta of the higher 4 bits to DR Sets the partner address 12 bits to bits 11 to 0 Figure 19 14 IEBus Partner Address Register PAR Format 15 0 14 0 13 0 12 0 PAR 11 10 9 8 7 6 5 4 3 2 1 0 Address FFFFF3E6H After reset 0000H R W R 5 IEBus control data register CDR a When master unit The data of the lower 4 bits is reflected in the data transmitted in the control field During master request this registe...

Page 461: ... 0 1 Undefined 1 1 1 0 Writes command 1 1 1 1 Writes data Cautions 1 Because the slave unit must judge whether the received data is a command or data it must read the value of this register after completing communication 2 If the master unit sets an undefined value NACK is returned from the slave unit and communication is aborted During broadcasting communication however the master unit continues ...

Page 462: ...han the unit that sent the lock request ACK returned 5 If 6H control data was received in the locked state from other than the unit that sent the lock request ACK not returned In all of the above cases the acknowledgement of a slave status or lock request will cause the STATUSF flag bit 4 of the ISR register to be set and the status interrupt INTIE2 to be generated The generation timing is at the ...

Page 463: ...IEBus unit is the communication target The STATUSF flag bit 4 of the ISR register is set and the status interrupt INTIE2 generated however if a slave status or lock address request is acknowledged Note that even if the same control data is received while the IEBus is in the locked state the interrupt generation timing for INTIE2 differs depending on whether the master unit 3 or another unit 4 is r...

Page 464: ...ster transmission slave transmission The data of this register is reflected in the data transmitted in the telegraph length field and indicates the number of bytes of the transmit data This register must be set in advance before transmission b When reception unit Master reception slave reception The receive data in the telegraph length field transmitted from the transmission unit is written to thi...

Page 465: ... 20H 32 bytes 1 1 1 1 1 1 1 1 FFH 255 bytes 0 0 0 0 0 0 0 0 00H 256 bytes Cautions 1 If the master issues a request 0H 4H 5H or 6H to transmit a slave status and lock address higher 4 bits lower 8 bits the contents of this register are set to 01H by hardware therefore the CPU does not have to set this register 2 In the case of defeat in a bus conflict and a slave status request is received from th...

Page 466: ...ister value However when the last byte and 32nd byte the last byte of 1 communication frame is stored in the shift register INTIE1 is not issued b When reception unit One byte of the data received by the shift register of the IEBus interface block is stored to this register Each time 1 byte has been correctly received an interrupt INTIE1 is issued When transmit receive data is transferred to and f...

Page 467: ...est flag SLVRQ Bit 6 A flag indicating whether there has been a slave request from the master Set reset conditions Set When the unit is requested as a slave if the received slave address and unit UAR match during individual communication reception or if the higher 4 bits of the received slave address match or if the received slave address is FFFH during broadcasting communication reception this fl...

Page 468: ...rforming broadcasting communication The contents of the flag are updated in the broadcast field of each frame Except for initialization reset by system reset the set reset conditions vary depending on the receive data of the broadcast field bit Set reset conditions Set When broadcasting is received by the broadcast field Reset When individual is received by the broadcast field or upon the input of...

Page 469: ...control field Reset When the communication enable flag is cleared When the communication end flag is set after receipt of a lock release 3H 6H AH BH in the control field Caution Lock specification release is not possible in broadcasting communication In the lock status individual communication from a unit other than the one that requests locking is not acknowledged However even communication from ...

Page 470: ... each flag satisfying the reset conditions in Table 19 8 Table 19 8 Reset Conditions of Flags in ISR Register Flag Name Reset Condition Processing Example IEERR STARTF STATUSF Byte write operation of ISR register Any value can be written ISR 00H etc ENDTRNS ENDFRAM Set MSTRQ ENSLVTX or ENSLVRX flag BCR register 88H or ENSLVTX 1 etc Caution Even if 0 is written to the ENDTRNS or ENDFRAM flag by acc...

Page 471: ...unication end flag 0 Communication does not end after the number of bytes set in the telegraph length field have been transferred 1 Communication ends after the number of bytes set in the telegraph length field have been transferred ENDFRAM Frame end flag 0 The frame transfer of the maximum number of bytes 32 bytes prescribed by mode 1 does not end 1 The frame transfer of the maximum number of byt...

Page 472: ...rom the unit requesting a lock Reset By software c Status transmission flag STATUSF Bit 4 A flag indicating that the transmission status is either the master to slave status or the lock address higher 4 bits lower 8 bits when IEBus is a slave unit Set reset conditions Set When 0H 4H 5H or 6H is received in the control field from the master when the IEBus is a slave unit Reset By software d Communi...

Page 473: ...r a slave unit A NACK reception error only occurs in individual communication ACK and NACK are not discriminated in broadcasting communication Remark An interrupt is generated if NACK is received in a field other than the data field Underrun Occurrence conditions Occurs during data transmission if there was insufficient time to write the next transmit data to the IEBus data register DR before ACK ...

Page 474: ...t starts in the overrun state the cause of the overrun NACK is not returned in the ACK period of the slave address control or telegraph length field the DR register is not updated If the next communication is not to the IEBus unit the DR register is not updated until it is read Because the IEBus unit is not a communication target the data interrupt INTIE1 and communication error interrupt INTIE2 a...

Page 475: ...re 19 25 IEBus Slave Status Register SSR Format After reset 41H R Address FFFFF3F2H 7 6 5 4 3 2 1 0 SSR 0 1 0 STATSLV 0 STATLOCK STATRX STATTX STATSLV Slave transmission status flag 0 Slave transmission stops 1 Slave transmission enabled STATLOCK Lock status flag 0 Unlock status 1 Lock status STATRX DR receive status 0 Receiving data not stored in DR 1 Receiving data stored in DR STATTX DR transmi...

Page 476: ...R Format After reset 01H R Address FFFFF3F4H 7 6 5 4 3 2 1 0 SCR Bit 7 6 5 4 3 2 1 0 Setting value Remaining number of communication data bytes 0 0 0 0 0 0 0 1 01H 1 byte 0 0 0 0 0 0 1 0 02H 2 bytes 0 0 1 0 0 0 0 0 20H 32 bytes 1 1 1 1 1 1 1 1 FFH 255 bytes 0 0 0 0 0 0 0 0 00H 0 byte end of communication or 256 bytes Note Note The actual hard counter consists of 9 bits When 00H is read it cannot b...

Page 477: ...ted when 1 byte has been communicated regardless of whether ACK or NACK When the count value has reached 00H the frame end flag ENDFRAM is set The maximum number of transfer bytes of the preset value of mode 1 per frame is 20H 32 bytes Figure 19 27 IEBus Communication Count Register CCR Format After reset 20H R Address FFFFF3F6H 7 6 5 4 3 2 1 0 CCR 13 IEBus clock selection register IECLK This regi...

Page 478: ... 5 of the above interrupt requests are assigned to the interrupt status register ISR For details refer to Table 19 9 Interrupt Source List The configuration of the interrupt control block is illustrated below Figure 19 29 Configuration of Interrupt Control Block IEERR STARTF STATUSF ENDTRNS ENDFRAM STATTX STATRX IEBus macro Interrupt control block V850 SB2 CPU INTIE1 INTIE2 Cautions 1 OR output of...

Page 479: ...t Contention judgment If loses remaster processing Communication preparation processing Interrupt always occurs if loses in contention during master request Start interrupt Slave Slave address Slave request judgment Communication preparation processing Generated only during slave request Status transmission Slave Control Refer to transmission processing example such as slave status Interrupt occur...

Page 480: ... Reception stops INTIE2 occurs NACK is returned To start bit waiting status Transmission stops INTIE2 occurs To start bit waiting status Individual communication Software processing Error processing such as retransmission request Error processing such as retransmission request NACK Reception Error Unit status Reception Transmission Occurrence condition Unit NACK transmission Unit NACK transmission...

Page 481: ...g INTIE2 does not occur NACK is returned Data is retransmitted from other unit Remark Data cannot be received until overrun status is cleared Transmission stops INTIE2 occurs To start bit waiting status Individual communication Software processing DR is read and overrun status is cleared Error processing such as retransmission request Error processing such as retransmission request Parity Error Un...

Page 482: ...ode 1 µ µ 1 Interrupt INTIE2 occurrence Judgment of occurrence of error Error processing Judgment of slave request Slave reception processing See 19 5 1 1 Slave reception processing Judgment of contention result Remaster request processing 2 Interrupt INTIE2 occurrence Judgment of occurrence of error Error processing Judgment of end of communication End of communication processing Judgment of end ...

Page 483: ... is received from the slave in the data field an interrupt INTIE1 is not issued to the CPU and the same data is retransmitted by hardware If the transmit data is not written in time during the period of writing the next data a communication error interrupt occurs due to occurrence of underrun and communication ends midway 3 Recommunication processing The vector interrupt processing in 2 judges whe...

Page 484: ...rt Broad casting M address P S address P A Control A P Telegraph length A P Data 1 Approx 390 s mode 1 µ Data 1 P A Data 2 P A Data n 1 P A Data n P A 2 1 1 Interrupt INTIE2 occurrence Judgment of occurrence of error Error processing Judgment of slave request Slave processing Judgment of collision result Remaster request processing 2 Interrupt INTIE2 occurrence Judgment of occurrence of error Erro...

Page 485: ...ave If the receive data is not read in time until the next data is received the hardware automatically transmits NACK 2 Frame end processing The vector interrupt processing in 2 judges whether the data has been correctly received within one frame If the data has not been correctly received if the number of data to be received in one frame could not be received a request to retransmit the data must...

Page 486: ... Judgment of slave request 2 Interrupt INTIE2 occurrence Judgment of occurrence of error Error processing Judgment of end of communication End of communication processing Judgment of end of frame Frame end processing See 19 5 3 2 Frame end processing Remarks 1 Interrupt INTIE1 occurrence See 19 5 3 1 Interrupt INTIE1 occurrence The transmit data of the second byte and those that follow are written...

Page 487: ...he period of writing the next data a communication error interrupt occurs due to occurrence of underrun and communication is abnormally ended 2 Frame end processing The vector interrupt processing in 2 judges whether the data has been correctly transmitted within one frame If the data has not been correctly transmitted if the number of data to be transmitted in one frame could not be transmitted t...

Page 488: ... s mode 1 µ µ Broad casting Telegraph length 1 Interrupt INTIE2 occurrence Judgment of occurrence of error Error processing Judgment of slave request Slave processing 2 Interrupt INTIE2 occurrence Judgment of occurrence of error Error processing Judgment of end of communication End of communication processing Judgment of end of frame Frame end processing See 19 5 4 2 Frame end processing Remarks 1...

Page 489: ...field an interrupt INTIE1 is not issued to the CPU and the same data is retransmitted from the master If the receive data is not read in time until the next data is received NACK is automatically transmitted 2 Frame end processing The vector interrupt processing in 2 judges whether the data has been correctly received within one frame ...

Page 490: ...e following interrupt does not occur in that communication frame 1 Master transmission Figure 19 34 Master Transmission Interval of Interrupt Occurrence Start bit T t1 T Broad casting Master address T t2 P Slave address T P A A T T t3 Control P A A t4 T A T Telegraph length P A Data P A Communication starts Communication start interrupt P A Data Data A P Data T T t4 End of communication End of fra...

Page 491: ... of frame Communication start interrupt T T T T T A T t4 t4 t5 t2 A P T A t3 Remarks 1 T Timing error P Parity error A ACK error Data set interrupt INTIE1 2 End of frame occurs at the end of 32 byte data IEBus at 6 29 MHz Item Symbol MIN Unit Communication starts timing error t1 Approx 93 µs Communication starts communication start interrupt t2 Approx 1282 µs Communication start interrupt timing e...

Page 492: ... Control Data Telegraph length Remarks 1 T Timing error P Parity error A ACK error U Underrun error Data set interrupt INTIE1 2 End of frame occurs at the end of 32 byte data IEBus at 6 29 MHz Item Symbol MIN Unit Communication starts timing error t1 Approx 96 µs Communication starts communication start interrupt t2 Approx 1192 µs Communication start interrupt timing error t3 Approx 15 µs Communic...

Page 493: ...ts Broad casting Master address Slave address Control Data Telegraph length Remarks 1 T Timing error P Parity error A ACK error O Overrun error Data set interrupt INTIE1 2 End of frame occurs at the end of 32 byte data IEBus at 6 29 MHz Item Symbol MIN Unit Communication starts timing error t1 Approx 96 µs Communication starts communication start interrupt t2 Approx 1192 µs Communication start int...

Page 494: ...output clock selection register 4 BRG 338 BRGCN4 Baud rate generator source clock selection register 4 BRG 337 BRGMC00 Baud rate generator mode control register 00 BRG 318 BRGMC01 Baud rate generator mode control register 01 BRG 318 BRGMC10 Baud rate generator mode control register 10 BRG 318 BRGMC11 Baud rate generator mode control register 11 BRG 318 CCR IEBus communication count register IEBus ...

Page 495: ...mode register 1 CSI 247 CSIM2 Serial operation mode register 2 CSI 247 CSIM3 Serial operation mode register 3 CSI 247 CSIM4 Variable length serial control register 4 CSI 335 CSIS0 Serial clock selection register 0 CSI 248 CSIS1 Serial clock selection register 1 CSI 248 CSIS2 Serial clock selection register 2 CSI 248 CSIS3 Serial clock selection register 3 CSI 248 DBC0 DMA byte counter register 0 D...

Page 496: ...dress register 3 DMAC 361 DRA4 DMA internal RAM address register 4 DMAC 361 DRA5 DMA internal RAM address register 5 DMAC 361 DWC Data wait control register BCU 111 ECR Interrupt source register CPU 76 EGN0 Falling edge specification register 0 INTC 132 378 EGP0 Rising edge specification register 0 INTC 132 378 EIPC Status saving register during interrupt CPU 76 EIPSW Status saving register during...

Page 497: ...t 375 P1 Port 1 Port 380 P2 Port 2 Port 384 P3 Port 3 Port 389 P4 Port 4 Port 393 P5 Port 5 Port 393 P6 Port 6 Port 396 P7 Port 7 Port 399 P8 Port 8 Port 399 P9 Port 9 Port 401 P10 Port 10 Port 404 P11 Port 11 Port 408 PAC Port alternate function control register Port 410 PAR IEBus partner address register IEBus 460 PCC Processor clock control register CG 160 PF1 Port 1 function register Port 382 ...

Page 498: ...gister 0 Port 377 PU1 Pull up resistor option register 1 Port 381 PU2 Pull up resistor option register 2 Port 386 PU3 Pull up resistor option register 3 Port 390 PU10 Pull up resistor option register 10 Port 406 PU11 Pull up resistor option register 11 Port 410 RTBH Real time output buffer register H RPU 370 RTBL Real time output buffer register L RPU 370 RTPC Real time output port control registe...

Page 499: ...egister 50 RPU 212 TCL51 Timer clock selection register 51 RPU 212 TCL60 Timer clock selection register 60 RPU 212 TCL61 Timer clock selection register 61 RPU 212 TCL70 Timer clock selection register 70 RPU 212 TCL71 Timer clock selection register 71 RPU 212 TM0 16 bit timer register 0 RPU 176 TM1 16 bit timer register 1 RPU 176 TM2 8 bit counter 2 RPU 211 TM23 16 bit counter 23 when connected to ...

Page 500: ...pt control register INTC 139 to 141 TMIC6 Interrupt control register INTC 139 to 141 TMIC7 Interrupt control register INTC 139 to 141 TOC0 16 bit timer output control register 0 RPU 182 TOC1 16 bit timer output control register 1 RPU 182 TXS0 Transmit shift register 0 UART 313 TXS1 Transmit shift register 1 UART 313 UAR IEBus unit address register IEBus 459 USR IEBus unit status register IEBus 467...

Page 501: ...lines refer to Table B 2 This column shows instruction operations refer to Table B 3 This column shows flag statuses refer to Table B 4 Operand Op Code Operation Flag OV S Z SAT Table B 1 Symbols in Operand Description Symbol Description reg1 General purpose register r0 to r31 Used as source register reg2 General purpose register r0 to r31 Mainly used as destination register ep Element pointer r30...

Page 502: ...d memory a b Reads data of size b from address a store memory a b c Writes data b of size c to address a load memory bit a b Reads bit b from address a store memory bit a b c Writes c to bit b of address a saturated n Performs saturated processing of n n is 2 s complements Result of calculation of n If n is n 7FFFFFFFH as result of calculation 7FFFFFFFH If n is n 80000000H as result of calculation...

Page 503: ...V 1 Overflow NV 1000 OV 0 No overflow C L 0001 CY 1 Carry Lower Less than NC NL 1001 CY 0 No carry No lower Greater than or equal Z E 0010 Z 1 Zero Equal NZ NE 1010 Z 0 Not zero Not equal NH 0011 CY OR Z 1 Not higher Less than or equal H 1011 CY OR Z 0 Higher Greater than N 0100 S 1 Negative P 1100 S 0 Positive T 0101 Always unconditional SA 1101 SAT 1 Saturated LT 0110 S XOR OV 1 Less than signed...

Page 504: ... rrrrr0111ddddddd adr ep zero extend disp7 Store memory adr GR reg2 Byte SST H reg2 disp8 ep rrrrr1001ddddddd Note 1 adr ep zero extend disp8 Store memory adr GR reg2 Halfword SST W reg2 disp8 ep rrrrr1010dddddd1 Note 2 adr ep zero extend disp8 Store memory adr GR reg2 Word ST B reg2 disp16 reg1 rrrrr111010RRRRR dddddddddddddddd adr GR reg1 sign extend disp16 Store memory adr GR reg2 Byte ST H reg...

Page 505: ...RRRRR result GR reg2 GR reg1 CMP imm5 reg2 rrrrr010011iiiii result GR reg2 sign extend imm5 Arithmetic operation SETF cccc reg2 rrrrr1111110cccc 0000000000000000 if conditions are satisfied then GR reg2 00000001H else GR reg2 00000000H SATADD reg1 reg2 rrrrr000110RRRRR GR reg2 saturated GR reg2 GR reg1 SATADD imm5 reg2 rrrrr010001iiiii GR reg2 saturated GR reg2 sign extend imm5 SATSUB reg1 reg2 rr...

Page 506: ...0101iiiii GR reg2 GR reg2 arithmetically shift right by zero extend imm5 0 JMP reg1 00000000011RRRRR PC GR reg1 JR disp22 0000011110dddddd ddddddddddddddd0 Note 1 PC PC sign extend disp22 JARL disp22 reg2 rrrrr11110dddddd ddddddddddddddd0 Note 1 GR reg2 PC 4 PC PC sign extend disp22 Jump Bcond disp9 ddddd1011dddcccc Note 2 if conditions are satisfied then PC PC sign extend disp9 SET1 bit 3 disp16 ...

Page 507: ...1FH RETI 0000011111100000 0000000101000000 if PSW EP 1 then PC EIPC PSW EIPSW else if PSW NP 1 then PC FEPC PSW FEPSW else PC EIPC PSW EIPSW R R R R R HALT 0000011111100000 0000000100100000 Stops DI 0000011111100000 0000000101100000 PSW ID 1 Maskable interrupt disabled EI 1000011111100000 0000000101100000 PSW ID 0 Maskable interrupt enabled Special NOP 0000000000000000 Uses 1 clock cycle without d...

Page 508: ...ess match detection method 295 Address space 79 ADIC 139 to 141 ADM1 348 ADM2 350 ADS 350 ADTRG 59 Analog input channel specification register 350 ANI0 to ANI11 64 Arbitration 296 ASCK0 60 ASCK1 61 ASIM0 ASIM1 315 ASIS0 ASIS1 316 ASTB 65 Asynchronous serial interface 312 Asynchronous serial interface mode registers 0 1 315 Asynchronous serial interface status registers 0 1 316 AVDD 67 AVREF 67 AVS...

Page 509: ...sters 0 to 5 366 DMA channel control registers 0 to 5 367 DMA internal RAM address registers 0 to 5 361 DMA peripheral I O address registers 0 to 5 360 DMAIC0 to DMAIC5 139 to 141 DMA start factor expansion register 366 DMAS 366 DR 466 DRA0 to DRA5 361 DSTB 65 DWC 110 E ECR 76 EGN0 142 378 EGP0 142 378 EIPC 76 EIPSW 76 Error detection 295 EVDD 68 EVSS 68 Exception trap 148 Extension code 295 Exter...

Page 510: ...ntrol register 139 Interrupt controller 38 48 Interrupt request signal generator 256 Interrupt source register 76 Interrupt status saving register 76 Interrupt exception processing function 124 Interval timer mode 237 INTP0 to INTP6 59 ISPR 142 ISR 470 K Key interrupt function 156 Key return mode register 156 KR0 to KR7 66 KRIC 139 to 141 KRM 156 L LBEN 64 Low power consumption mode 356 M Main sys...

Page 511: ...5 Port 3 389 Port 3 function register 391 Port 3 mode register 390 Port 4 393 Port 4 mode register 394 Port 5 393 Port 5 mode register 394 Port 6 396 Port 6 mode register 397 Port 7 399 Port 8 399 Port 9 401 Port 9 mode register 402 Port alternate function control register 411 Power save control register 162 Power save function 164 PRCMD 105 Prescaler mode register 0n 183 Prescaler mode register 1...

Page 512: ...rface function 244 Serial operation mode registers 0 to 3 247 SERIC0 SERIC1 139 to 141 SI0 SI1 60 SI2 SI3 61 SI4 62 Single chip mode 78 SIO0 to SIO3 245 SIO4 333 Slave address registers 0 1 268 SO latch 255 SO0 SO1 60 SO2 SO3 61 SO4 62 Software exception 146 Software start 344 Software STOP mode 170 Specific register 103 SSR 475 Standby function 331 Start condition 270 STIC0 STIC1 139 to 141 Stop ...

Page 513: ... 4 336 VDD 68 VPP 68 VSS 68 W WAIT 67 Wait function 110 Wake up controller 255 Wake up function 298 Watch timer clock selection register 233 Watch timer function 230 Watch timer mode control register 232 Watchdog timer clock selection register 239 Watchdog timer function 236 Watchdog timer mode 237 Watchdog timer mode register 143 240 WDCS 239 WDTIC 139 to 141 WDTM 143 240 Word access 108 Wrap aro...

Page 514: ...User s Manual U13850EJ4V0UM 514 MEMO ...

Page 515: ...886 2 2719 5951 Address North America NEC Electronics Inc Corporate Communications Dept Fax 1 800 729 9288 1 408 588 6130 Europe NEC Electronics Europe GmbH Technical Documentation Dept Fax 49 211 6503 274 South America NEC do Brasil S A Fax 55 11 6462 6829 Asian Nations except Philippines NEC Electronics Singapore Pte Ltd Fax 65 250 3583 Japan NEC Semiconductor Technical Hotline Fax 81 44 435 960...

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