National Semiconductor ST-NIC DP83902A Manual Download

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DP83902A

DP83902A ST-NIC(TM) Serial Network Interface Controller for Twisted Pair

Literature Number: SNLS082A

Summary of Contents for ST-NIC DP83902A

Page 1: ...DP83902A DP83902A ST NIC TM Serial Network Interface Controller for Twisted Pair Literature Number SNLS082A ...

Page 2: ...ENDEC module interfaces directly to the transceiver module and also provides a fully IEEE compliant AUI At tachment Unit Interface for connection to other media transceivers Continued Features Y Single chip solution for IEEE 802 3 10BASE T Y Integrated controller ENDEC and transceiver Y Full AUI interface Y No external precision components required Y 3 levels of loopback supported Transceiver Modu...

Page 3: ... processing isola tion is required at the AUI differential signal interface for 10BASE5 and 10BASE2 applications Capacitive or induc tive isolation may be used Table Of Contents 1 0 SYSTEM DIAGRAM 2 0 PIN DESCRIPTION 3 0 BLOCK DIAGRAM 4 0 FUNCTIONAL DESCRIPTION 5 0 TRANSMIT RECEIVE PACKET ENCAPSULATION DECAPSULATION 6 0 DIRECT MEMORY ACCESS CONTROL DMA 7 0 PACKET RECEPTION 8 0 PACKET TRANSMISSION ...

Page 4: ...Connection Diagrams Continued TL F 11157 56 Order Number DP83902AVLJ See NS Package Number VLJ100A 3 O b s o l e t e ...

Page 5: ... 6 93 WACK I WRITE ACKNOWLEDGE Issued from system to DP83902A to indicate that data has been written to the external latch The DP83902A will begin a write cycle to place the data in local memory 98 7 95 PRD O PORT READ Enables data from external latch on to local bus during a memory write cycle to local memory remote write operation This allows asynchronous transfer of data from the system memory ...

Page 6: ...nal register selected by RA0 RA3 Data is latched into the DP83902A on the rising edge of this input 32 37 30 SRD I SLAVE READ STROBE Strobe from CPU to read an internal register selected by RA0 RA3 The register data is output when SRD goes low 33 38 31 ACK O ACKNOWLEDGE Active low when DP83902A grants access to CPU Used to insert WAIT states to CPU until DP83902A is synchronized for a register rea...

Page 7: ...isted pair medium 64 65 61 62 61 62 RXIa I TWISTED PAIR RECEIVE INPUTS These inputs feed a differential amplifier RXIb which passes valid data to the ENDEC module 69 67 65 GDLNK I O GOOD LINK LINK DISABLE This pin has a dual function both input and output LNKDIS The function is latched by the DP83902A on the rising edge of the Reset signal i e on the chip returning to normal operation after reset ...

Page 8: ... SUPPLY PINS 20 34 48 2 26 39 17 32 46 GND NEGATIVE GROUND SUPPLY PINS It is suggested that a 68 90 49 64 64 88 decoupling capacitor be connected between the VCC and GND pins POWER SUPPLY PINS ANALOG 93 4 90 VCC VCO 5V SUPPLY PIN Care should be taken to reduce noise on this pin as it supplies power to the analog VCO to the Phase Lock Loop 92 3 89 GND VCO GROUND SUPPLY PIN Care should be taken to r...

Page 9: ... 3 FIGURE 1 Typical Connection to Twisted Pair Cable TL F 11157 4 Recommended integrated modules are 1 Pulse Engineering PE65431 2 Belfuse 0556 2006 01 or 0556 3392 00 3 Valor FL1012 ST NIC Twisted Pair Interface 8 O b s o l e t e ...

Page 10: ...ch levels are reduced to minimize the effect of noise causing premature End of Packet detection The reduced squelch mode functions the same as the 10BASE T mode except that only the lower level is used for both turn on and turn off COLLISION A collision is detected by the TPI module when the receive and transmit channels are active simultaneously If the TPI is receiving when a collision is detecte...

Page 11: ...ith SEL high for IEEE 802 3 Transmita and Transmitb are equal in the idle state This provides zero differential voltage to operate with transform er coupled loads MANCHESTER DECODER The decoder consists of a differential receiver and a PLL to separate a Manchester decoded data stream into internal clock signals and data The differential input must be exter nally terminated with two 39X resistors c...

Page 12: ...s ical address registers stored in the Address Register Array If any one of the six bytes does not match the pre pro grammed physical address the Protocol Control Logic re jects the packet All multicast destination addresses are fil tered using a hashing technique See register description If the multicast address indexes a bit that has been set in the filter bit array of the Multicast Address Regi...

Page 13: ...nowledge handshake protocol 5 0 Transmit Receive Packet Encapsulation Decapsulation A standard IEEE 802 3 packet consists of the following fields preamble Start of Frame Delimiter SFD destination address source address length data and Frame Check Sequence FCS The typical format is shown in Figure 2 The packets are Manchester encoded and decoded by the ENDEC module and transferred serially to the N...

Page 14: ...MA capabilities of the ST NIC greatly simplify the use of the DP83902A in typical configurations The local DMA channel transfers data between the FIFO and memory On transmission the packet is DMAed from memory to the FIFO in bursts Should a collision occur up to 15 times the packet is retransmitted with no processor intervention On reception packets are DMAed from the FIFO to the receive buffer ri...

Page 15: ...loaded networks The assignment of buffers for storing packets is controlled by Buffer Man agement Logic in the ST NIC The Buffer Management Log ic provides three basic functions linking receive buffers for long packets recovery of buffers when a packet is rejected and recirculation of buffer pages that have been read by the host At initialization a portion of the 64 kbyte or 32k word ad dress spac...

Page 16: ...rted The Boundary Pointer is also used to initialize the Remote DMA for remov ing a packet and is advanced when a packet is removed A simple analogy to remember the function of these registers is that the Current Page Register acts as a Write Pointer and the Boundary Pointer acts as a Read Pointer Note At initialization the Page Start Register value should be loaded into both Current Page Register...

Page 17: ...uals the Page Stop Register the buffer manage ment logic will restore the DMA to the first buffer in the Receive Buffer Ring value programmed in the Page Start Address Register The second comparison tests for equality between the DMA address of the next buffer address and the contents of the Boundary Pointer Register If the two values are equal the reception is aborted The Boundary Pointer Registe...

Page 18: ...ecessary to time out for the maximum possible duration of an Ethernet transmission or reception By waiting 1 6 ms this is achieved with some guard band added Previously it was recommended that the RST bit of the Interrupt Status Register be polled to insure that the pending transmission or reception is completed This bit is not a reliable indicator and subsequently should be ignored 4 Clear the ST...

Page 19: ...IC out of loopback This is done by writ ing the Transmit Configration Register with the value it contains during normal operation Bits D2 and D1 should both be programmed to 0 11 If the Resend variable is set to a 1 reset the Re send variable and reissue the transmit command This is done by writing a value of 26H to the Command Reg ister If the Resend variable is 0 nothing needs to be done Note 1 ...

Page 20: ... The local receive DMA is still not active since the ST NIC is in LOOPBACK 11 Initialize the Transmit Configuration for the intended value The ST NIC is now ready for transmission and reception END OF PACKET OPERATIONS At the end of the packet the ST NIC determines whether the received packet is to be accepted or rejected It either branches to a routine to store the Buffer Header or to anoth er ro...

Page 21: ... to store the rejected packet This operation will not be performed if the ST NIC is programmed to accept either runt packets or packets with CRC or Frame Alignment errors The received CRC is always stored in buffer memory after the last byte of received data for the packet Error Recovery If the packet is rejected as shown the DMA is restored by the ST NIC by reprogramming the DMA starting address ...

Page 22: ...NDRY the buffer is full STORAGE FORMAT FOR RECEIVED PACKETS The following diagrams describe the format for how re ceived packets are placed into memory by the local DMA channel These modes are selected in the Data Configura tion Register AD15 AD8 AD7 AD0 Next Packet Pointer Receive Status Receive Byte Count 1 Receive Byte Count 0 Byte 2 Byte 1 BOS e 0 WTS e 1 in Data Configuration Register This fo...

Page 23: ...ier sense is asserted before a byte has been loaded into the FIFO the ST NIC will become a receiver COLLISION RECOVERY During transmission the Buffer Management logic monitors the transmit circuitry to determine if a collision has occurred If a collision is detected the Buffer Management logic will reset the FIFO and restore the Transmit DMA pointers for retransmission of the packet The COL bit wi...

Page 24: ...st The Remote DMA will sequentially read data from the local buffer memory begin ning at the Remote Start Address and write data to the I O port The DMA Address will be incremented and the Byte Counter will be decremented after each transfer The DMA is terminated when the Remote Byte Count Register reach es zero SEND PACKET COMMAND The Remote DMA channel can be automatically initialized to transfe...

Page 25: ... Register Address 1 CLDA1 PSTOP 03H Boundary Pointer Boundary Pointer BNRY BNRY 04H Transmit Status Transmit Page Start Register TSR Address TPSR 05H Number of Collisions Transmit Byte Count Register NCR Register 0 TBCR0 06H FIFO FIFO Transmit Byte Count Register 1 TBCR1 07H Interrupt Status Interrupt Status Register ISR Register ISR 08H Current Remote DMA Remote Start Address Address 0 CRDA0 Regi...

Page 26: ...egister 4 MAR4 0DH Multicast Address Multicast Address Register 5 MAR5 Register 5 MAR5 0EH Multicast Address Multicast Address Register 6 MAR6 Register 6 MAR6 0FH Multicast Address Multicast Address Register 7 MAR7 Register 7 MAR7 Page 2 Address Assignments PS1 e 1 PS0 e 0 RA0 RA3 RD WR 00H Command CR Command CR 01H Page Start Register Current Local DMA PSTART Address 0 CLDA0 02H Page Stop Registe...

Page 27: ...powers up high Note If the ST NIC has previously been in start mode and the STP is set both the STP and STA bits will remain set D1 STA Start This bit is used to activate the ST NIC after either power up or when the ST NIC has been placed in a reset mode by software command or error STA powers up low D2 TXP Transmit Packet This bit must be set to initiate the transmission of a packet TXP is intern...

Page 28: ...D2 RXE Receive Error Indicates that a packet was received with one or more of the following errors Ð CRC Error Ð Frame Alignment Error Ð FIFO Overrun Ð Missed Packet D3 TXE Transmit Error Set when packet transmitted with one or more of the following errors Ð Excessive Collisions Ð FIFO Underrun D4 OVW Overwrite Warning Set when receive buffer ring storage resources have been exhausted Local DMA ha...

Page 29: ...packet received D1 PTXE Packet Transmitted Interrupt Enable 0 Interrupt Disabled 1 Enables Interrupt when packet is transmitted D2 RXEE Receive Error Interrupt Enable 0 Interrupt Disabled 1 Enables Interrupt when packet received with error D3 TXEE Transmit Error Interrupt Enable 0 Interrupt Disabled 1 Enables Interrupt when packet transmission results in error D4 OVWE Overwrite Warning Interrupt E...

Page 30: ...DMA registers RSAR0 1 are issued as A16 A31 Power up high D3 LS Loopback Select 0 Loopback mode selected Bits D1 and D2 of the TCR must also be programmed for Loopback operation 1 Normal Operation D4 ARM Auto Initialize Remote 0 Send Command not executed all packets removed from Buffer Ring under program control 1 Send Command executed Remote DMA auto initialized to remove packets from Buffer Ring...

Page 31: ...Operation LPBK e 0 Mode 1 0 1 Internal NIC Module Loopback LPBK e 0 Mode 2 1 0 Internal ENDEC Module Loopback LPBK e 1 Mode 3 1 1 External Loopback LPBK e 0 D3 ATD Auto Transmit Disable This bit allows another station to disable the ST NIC s transmitter by transmission of a particular multicast packet The transmitter can be re enabled by resetting this bit or by reception of a second particular mu...

Page 32: ...s recorded in the Number of Collisions Registers NCR D3 ABT Transmit Aborted Indicates the ST NIC aborted transmission because of excessive collisions Total number of transmissions including original transmission attempt equals 16 D4 CRS Carrier Sense Lost This bit is set when carrier is lost during transmission of the packet Transmission is not aborted on loss of carrier D5 FU FIFO Underrun If th...

Page 33: ...lticast Enables the receiver to accept a packet with a multicast address All multicast addresses must pass the hashing array 0 Packets with multicast destination address not checked 1 Packets with multicast destination address checked D4 PRO Promiscuous Physical Enables the receiver to accept all packets with a physical address 0 Physical address of node must match the station address programmed i...

Page 34: ...ncrements Tally Counter CNTR1 This bit will also be set for Frame Alignment errors D2 FAE Frame Alignment Error Indicates that the incoming packet did not end on a byte boundary and the CRC did not match at the last byte boundary Increments Tally Counter CNTR0 D3 FO FIFO Overrun This bit is set when the FIFO is not serviced causing overflow during reception Reception of the packet will be aborted ...

Page 35: ...n on the bus Thus they are shifted to positions 15 8 in the diagram above 10 5 TRANSMIT DMA REGISTERS TRANSMIT PAGE START REGISTER TPSR This register points to the assembled packet to be transmit ted Only the eight higher order addresses are specified since all transmit packets are assembled on 256 byte page boundaries The bit assignment is shown below The values placed in bits D7 D0 will be used ...

Page 36: ...e transferred and the Remote Byte Count is used to indicate the length of the block in bytes 7 6 5 4 3 2 1 0 RSAR1 A15 A14 A13 A12 A11 A10 A9 A8 7 6 5 4 3 2 1 0 RSAR0 A7 A6 A5 A4 A3 A2 A1 A0 REMOTE BYTE COUNT REGISTERS RBCR0 1 7 6 5 4 3 2 1 0 RBCR1 BC15 BC14 BC13 BC12 BC11 BC10 BC9 BC8 7 6 5 4 3 2 1 0 RBCR0 BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0 Note RSAR0 programs the start address bits A0 A7 RSAR1 prog...

Page 37: ...n binary in CT0 CT7 of each Tally Register Frame Alignment Error Tally CNTR0 This counter increments every time a packet is received with a Frame Alignment Error The packet must have been recognized by the address recognition logic The counter is cleared after it is read by the processor 7 6 5 4 3 2 1 0 CNTR0 CT7 CT6 CT5 CT4 CT3 CT2 CT1 CT0 CRC Error Tally CNTR1 This counter is incremented every t...

Page 38: ...n of the Receive Buffer Ring This is programmed in the Page Start and Page Stop Registers In addition the Boundary and Current Page Register must be initialized to the value of the Page Start Register These registers will be modified during reception of packets 12 0 Loopback Diagnostics Three forms of local loopback are provided on the ST NIC The user has the ability to loopback through the deseri...

Page 39: ...n the ST NIC will insert wait states Note The FIFO may only be read during Loopback Reading the FIFO at any other time will cause the ST NIC to malfunction Alignment of the Received Packet in the FIFO Reception of the packet in the FIFO begins at location zero after the FIFO pointer reaches the last location in the FIFO the pointer wraps to the top of the FIFO overwriting the previously received d...

Page 40: ...ly the PTX bit in the ISR is set the PRX bit is only set if status is written to memory In loopback this action does not occur and the PRX bit remains 0 for all loopback modes Note 4 All values are hex Path TCR RCR TSR RSR ISR ST NIC Internal 04 1F 43 02 02 Note 1 Note 1 CDH is set CRS is not set since it is generated by the external encoder decoder Path TCR RCR TSR RSR ISR ST NIC External 06 1F 0...

Page 41: ...verflow occurs The counters are sticky so that when they reach a count of 192 C0H counting is halted An additional counter is provided to count the number of packets the ST NIC misses due to buffer overflow or being offline The structure of the counters is shown below Additional information required for network management is available in the Receive and Transmit Status Registers Transmit status is...

Page 42: ...T NIC is issued a Start command and the ST NIC enters Idle state Until the DMA is required the ST NIC remains in idle state The idle state is exited by a request from the FIFO on the case of receiver or transmit or from the Remote DMA in the case of Remote DMA operation After acquiring the bus in a BREQ BACK hand shake the Remote or Local DMA transfer is completed and the ST NIC re enters the idle...

Page 43: ...Bit Data TL F 11157 23 32 Bit Address 8 Bit Data TL F 11157 24 32 Bit Address 16 Bit Data TL F 11157 25 Note In 32 bit address mode ADS1 is at TRI STATE after the first T1 T4 states thus a 4 7k pull down resistor is required for 32 bit address 42 O b s o l e t e ...

Page 44: ...he bus FIFO AND BUS OPERATIONS Overview To accommodate the different rates at which data comes from or goes to the network and goes to or comes from the system memory the ST NIC contains a 16 byte FIFO for buffering data between the bus and the media The FIFO threshold is programmable allowing filling or emptying the FIFO at different rates When the FIFO has filled to its pro grammed threshold the...

Page 45: ...EQ extend ed 3 ST NIC flushes remaining bytes from FIFO 4 ST NIC performs internal processing to prepare for writ ing the header 5 ST NIC writes 4 byte 2 word header 6 ST NIC deasserts BREQ End of Packet Processing EOPP times for 10 MHz and 20 MHz have been tabulated in the table below Mode Threshold Bus Clock EOPP Byte 2 Bytes 7 0 ms 4 Bytes 10 MHz 8 6 ms 8 Bytes 11 0 ms Byte 2 Bytes 3 6 ms 4 Byt...

Page 46: ...umber of bytes prefetched is the programmed FIFO threshold The next BREQ is not issued until after the ST NIC actually begins transmitting data i e after SFD The Transmit Prefetch diagram illus trates this process Transmit Prefetch Timing TL F 11157 59 Maximum Bus Latency for Byte Mode TL F 11157 60 Maximum Bus Latency for Word Mode TL F 11157 61 45 O b s o l e t e ...

Page 47: ...emote DMA Transfers TL F 11157 28 REMOTE READ TIMING 1 The DMA reads byte word from local buffer memory and writes byte word into latch increments the DMA address and decrements the byte count RBCR0 1 2 A Request Line PRQ is asserted to inform the system that a byte is available 3 The system reads the port the read strobe RACK is used as an acknowledge by the Remote DMA and it goes back to step 1 ...

Page 48: ...e To remedy this situation a single Remote Read cycle should be insert ed before the actual DMA Write Command is given This will ensure that PRQ is asserted when the Remote DMA Write is subsequently executed This single Remote Read cycle is called a dummy Remote Read In order for the dummy Remote Read cycle to operate correctly the Start Address should be programmed to a known safe location in the...

Page 49: ...t start address is usually a safe location 2 Issue the dummy Remote Read command 3 Read the Current Remote DMA Address CRDA both bytes 4 Compare to previous CRDA value if different go to 6 5 Delay and jump to 3 6 Set up for the Remote Write command by setting the Remote Byte Count and the Remote Start Address note that if the Remote Byte count in step 1 can be set to the transmit byte count plus o...

Page 50: ...s used to hold off the CPU until the ST NIC leaves master mode Some number of BSCK cycles is also required to allow the ST NIC to syn chronize to the read or write cycles Write to Register TL F 11157 31 Read from Register TL F 11157 32 TIME BETWEEN CHIP SELECTS The ST NIC requires that successive chip selects be no closer than 4 bus clocks BSCK together If the condition is violated the ST NIC may ...

Page 51: ...e IOL e 20 mA 0 1 V Notes 1 4 IOL e 2 0 mA 0 4 V VIH Minimum High Level Input Voltage Note 2 2 0 V VIH2 Minimum High Level Input Voltage 2 7 V For RACK WACK Note 2 VIL Maximum Low Level Input Voltage Note 2 0 8 V VIL2 Maximum Low Level Input Voltage 0 6 V For RACK WACK Note 2 VLOL Good Link Output Voltage IOL e 16 mA 0 4 V IIN Input Current VI e VCC or GND b1 0 a1 0 mA IINSEL Input Current VIN e V...

Page 52: ...OR PINS X1 AND X2 VIH X1 Input High Voltage X1 is Connected to an Oscillator 2 0 V and GND X2 is Grounded VIL X1 Input Low Voltage X1 is Connected to an Oscillator 0 8 V and GND X2 is Grounded IOSC X1 Input Current GND X2 is Grounded 3 mA VIN e VCC or GND IX2 X2 Input Current X2 Grounded 4 mA Driven Mode TWISTED PAIR INTERFACE PINS TXOg TXOdg and RXIg RTOL TXOdg TXOg Low Level IOL e 25 mA 15 X Out...

Page 53: ... 1 ACK is not generated until CS and SRD are low and the ST NIC has synchronized to the register access The ST NIC will insert an integral number of Bus Clock cycles until it is synchronized In Dual Bus systems additional cycles will be used for a local or remote DMA to complete Wait states must be issued to the CPU until ACK is asserted low Note 2 CS may be asserted before or after SRD If CS is a...

Page 54: ...ote 2 15 70 ns rackl Read Strobe to ACK Low Note 3 n bcyc a 30 ns rackh Read Strobe to ACK High 30 ns Note 1 rsrs includes flow through time of latch Note 2 These limits include the RC delay inherent in our test method These signals typically turn off within 15 ns enabling other devices to drive these lines with no contention Note 3 CS may be asserted before of after RA0 3 and SRD since address de...

Page 55: ...ter Write Data Hold 21 ns ww Write Strobe Width from ACK 50 ns wackh Write Strobe High to ACK High 30 ns wackl Write Low to ACK Low Notes 1 2 n bcyc a 30 ns rswsl Register Select to Write Strobe Low 10 ns Note 1 ACK is not generated until CS and SWR are low and the ST NIC has synchronized to the register access In Dual Bus Systems additional cycles will be used for a local DMA or Remote DMA to com...

Page 56: ...0 ns rwds Register Write Data Setup 20 ns rwdh Register Write Data Hold 21 ns wackl Write Low to ACK Low Note 2 n bcyc a 30 ns wackh Write High to ACK High 30 ns ww Write Width from ACK 50 ns Note 1 Assumes ADS0 is high when RA0 3 changing Note 2 ACK is not generated until CS and SWR are low and the ST NIC has synchronized to the register access In Dual Bus systems additional cycles will be used f...

Page 57: ...ntrol Enable 60 ns bcctr Bus Clock to Control Release Notes 2 3 70 ns Note 1 BACK must be setup before T1 after BREQ is asserted Missed setup will slip the beginning of the DMA by four bus clocks The Bus Latency will influence the allowable FIFO threshold Note 2 During remote DMA transfers only a single bus transfer is performed During local DMA operations burst mode transfers are performed Note 3...

Page 58: ... 45 ns bcadz Bus Clock to Address TRI STATE Note 3 15 55 ns ads Address Setup to ADS0 1 Low bch b 15 ns adh Address Hold from ADS0 1 Low bcl b 5 ns Note 1 Cycles T1Ê T2Ê T3Ê and T4Ê are only issued for the first transfer in a burst when 32 bit mode has been selected Note 2 The rate of bus clock must be high enough to support transfers to from the FIFO at a rate greater than the serial network tran...

Page 59: ... raz Memory Read High to Address TRI STATE bch a 40 ns Notes 1 2 asds Address Strobe to Data Strobe bcl a 10 ns dsada Data Strobe to Address Active bcyc b 10 ns avrh Address Valid to Read Strobe High 3 bcyc b 18 ns Note 1 During a burst A8 A15 are not TRI STATE if byte wide transfers are selected On the last transfer A8 A15 are TRI STATE as shown above Note 2 These limits include the RC delay inhe...

Page 60: ... a 7 ns waz Write Strobe to Address TRI STATE Notes 1 2 bch a 40 ns asds Address Strobe to Data Strobe bcl a 10 ns aswd Address Strobe to Write Data Valid bcl a 30 ns Note 1 When using byte mode transfers A8 A15 are only TRI STATE on the last transfer waz timing is only valid for last transfer in a burst Note 2 These limits include the RC delay inherent in our test method These signals typically t...

Page 61: ...nding on the bus clock and network rates The allowable wait states are found in the table below Assumes 10 Mbit sec data rate BSCK MHz Max Ý of Wait States Byte Transfer Word Transfer 8 0 1 10 0 1 12 1 2 14 1 2 16 1 3 18 2 3 20 2 4 Table assumes 10 MHz network clock The number of allowable wait states in byte mode can be calculated using ÝW byte mode e 8 tnw 4 5 tbsck b 1 J ÝW e Number of Wait Sta...

Page 62: ...Clock to Port Write Low 43 ns bpwrh Bus Clock to Port Write High 40 ns prqh Port Write High to Port Request High Note 1 30 ns prql Port Request Low from Read Acknowledge High 60 ns rakw Remote Acknowledge Read Strobe Pulse Width 20 ns Note 1 Start of next transfer is dependent on where RACK is generated relative to BSCK and whether a local DMA is pending 61 O b s o l e t e ...

Page 63: ...30 ns prql Port Request Low from Read Acknowledge High 60 ns rakw Remote Acknowledge Read Strobe Pulse Width 20 ns rhpwh Read Acknowledge High to Next Port Write Cycle 11 BSCK Notes 2 3 4 Note 1 Start of next transfer is dependent on where RACK is generated relative to BSCK and whether or not a local DMA is pending Note 2 This is not a measured value but guaranteed by design Note 3 RACK must be hi...

Page 64: ... wackw WACK Pulse Width 25 ns bprdl Bus Clock to Port Read Low Note 2 55 ns bprdh Bus Clock to Port Read High 40 ns Note 1 The first port request is issued in response to the remote write command It is subsequently issued on T1 clock cycles following completion of remote DMA cycles Note 2 The start of the remote DMA write following WACK is dependent on where WACK is issued relative to BSCK and whe...

Page 65: ...lowing WACK is dependent on where WACK is issued relative to BSCK and whether a local DMA is pending Note 3 Assuming wackw k 1 BSCK and no local DMA interleave no CS immediate BACK and WACK goes high before T4 Note 4 WACK must be high for a minimum of 7 BSCK Note 5 This is not a measured value but guaranteed by design Reset Timing TL F 11157 64 Symbol Parameter Min Max Units rstw Reset Pulse Width...

Page 66: ...utput High before Idle Half Step 200 ns tTOl Transmit Output Idle Time Half Step 8000 ns AUI TPI Receive End of Packet Timing TL F 11157 47 Symbol Parameter Min Max Units teop1 Receive End of Packet Hold Time after Logic 1 Note 1 225 ns teop0 Receive End of Packet Hold Time after Logic 0 Note 1 225 ns Note 1 This parameter is guaranteed by design and is not tested 65 O b s o l e t e ...

Page 67: ... tipw Link Integrity Output Pulse Width 80 130 ns TPI Transmit and End of Packet Timing TL F 11157 49 Symbol Parameter Min Max Units tdel Pre Emphasis Output Delay 46 54 ns TXOg to TXOdg Note 1 toff Transmit Hold Time at End of Packet TXOg Note 1 250 ns toffd Transmit Hold Time at End of Packet TXOdg Note 1 200 ns Note 1 This parameter is guaranteed by design and is not tested 66 O b s o l e t e ...

Page 68: ... timing tests for push pull outputs S1 e VCC for VOL test S1 e GND for VOH test S1 e VCC for High Impedance to active low and active low to High Impedance measurements S1 e GND for High Impedance to active high and active high to High Impedance measurements Pin Capacitance TA e 25 C f e 1 MHz Symbol Parameter Typ Units CIN Input Capacitance 7 pF COUT Output Capacitance 7 pF DERATING FACTOR Output ...

Page 69: ...7 0 Physical Dimensions inches millimeters Plastic Chip Carrier V Order Number DP83902AV NS Package Number V84A 100 Pin Quad Flat Pack Order Number DP83902AVF NS Package Number VF100B 68 O b s o l e t e ...

Page 70: ...17 0 Physical Dimensions inches millimeters Continued Plastic Quad Flatpack VJG Order Number DP83902AVJG NS Package Number VJG100A 69 O b s o l e t e ...

Page 71: ...port device or system or to affect its safety or with instructions for use provided in the labeling can effectiveness be reasonably expected to result in a significant injury to the user National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Hong Kong Ltd Japan Ltd 1111 West Bardin Road Fax a49 0 180 530 85 86 13th Floor Straight Block Tel 81...

Page 72: ...for use in safety critical applications such as life support where a failure of the TI product would reasonably be expected to cause severe personal injury or death unless officers of the parties have executed an agreement specifically governing such use Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications and acknowledge and agre...

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