Motorola PPC/PMC-8260/DS1, Reference Manual, Page: 74 / 150

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4 - 10 PPC/PMC-8260/DS1
Table 11: ROM Image Configuration Section
Offset Bytes Mnemonic Description
E0
16
1 CSUM_ID If this byte is set to C5
16
the checksum information in the
subsequent fields IMG_SIZE and IMG_CSUM is con-
sidered valid. Otherwise, no checksum test is performed.
E4
16
4 IMG_SIZE The size of the ROM image in bytes (without the 256
bytes configuration section). Values of FFFF.FFFF
16
and 0 are considered invalid.
This parameter must be set for checksum calculation and
the shadow feature.
E8
16
4 IMG_CSUM Checksum of the ROM image
The valid 32-bit checksum of a ROM image is calculated
by adding IMG_SIZE bytes beginning at ROM image
offset 100
16
. To perform the checksum test, CSUM_ID
must be set to C5
16
.
F0
16
1 SYPCR_WR If set to 0, the firmware will preset the SYPCR register
of the PowerQUICC II with SYPCR_VAL (see below)
before executing the ROM image. Otherwise the SYPCR
register is left in its reset state.
F1
16
1 POST_SKIP If set to 0, no POST will be executed by the firmware. If
set to FF
16
POST execution depends on the setting of the
PCR[PSKIP] bit (see Table 12 “PCR Register Settings”
on page 4-13).
F2
16
1 FLAGS Various flags
Bit Mnemonic Description
0 FPOST POST execution
0: Normal POST
1: Fast POST
1 SHADOW RAM shadow
0: No shadow to RAM is
executed
1: Shadow to RAM is
executed
2 SMODE Shadow incl. configura-
tion section
0: Shadow without con-
figuration section
1: Shadow with configu-
ration section