Motorola PPC/PMC-8260/DS1, Reference Manual, Page: 119 / 150

Memory Map and Devices SDRAM and its Performance
PPC/PMC-8260/DS1 5 - 15
SDRAM and its Performance
The PPC/PMC-8260/DS1 module provides 64 MByte on-board Synchronous
DRAM (SDRAM) which is 64-bit wide. The SDRAM is clocked with the 60x bus
system clock of 66 MHz.
The SDRAM interface supports page-based bank interleaving which allows highest
efficiency of the four-bank SDRAM architecture. The burst performance of the
SDRAM interface is 3:1:1:1 accesses for 32-byte burst reads and 2:1:1:1 accesses
for 32-byte burst writes (CAS latency = 2). Parity generation and check is not sup-
ported. This results in high performance main memory access bandwidth for the
PowerQUICC II processor.
The SDRAM is accessible from the PowerQUICC II or the PCI bus via the Power-
SPAN II PCI bus bridge.
Table 28: SDRAM Access on 60x Bus (PowerPC Bus)
Device Size Width 60x-bus Address Controlled by
PowerQUICC II
SDRAM 64 MByte 64 bit 00000000
16
- 03FFFFFF
16
(programmable)
SDRAM machine
SDRAM Machine Memory Controller
The SDRAM interface supports back-to-back page mode. A page remains open as
long as back-to-back accesses that hit the page are generated on the bus. The page
is closed once the bus becomes idle. The SDRAM interface uses SDRAM devices
with four internal banks and supports bank interleaving on a page-based boundary.
This method uses low address bits as the bank-select for the SDRAM, thus allow-
ing interleaving on every page boundary. This means that if a missed page is in a
different SDRAM bank from the page currently open, the SDRAM machine issues
an “activate” command hiding the precharge time of the already open bank.
The SDRAM interface supports single-beat reads/writes up to DWORD (64-bit, 8
byte) size and burst reads/writes of four DWORDs (32-byte).