Motorola PPC/PMC-8260/DS1, Reference Manual, Page: 118 / 150

PowerSPAN II PCI Bus Bridge Memory Map and Devices
5 - 14 PPC/PMC-8260/DS1
Opening Windows in the 60x Bus Slave Channel
The PowerSPAN II provides eight 60x bus slave images to map 60x bus cycles to
the PCI bus. No window is opened by the default settings in the E
2
PROM. To
enable the PMC module to access the PCI bus and memory of the carrier board, the
following basic programming steps are necessary to set up a 60x bus slave image:
1. Program PB_SIx_BADDR register with 60x bus base address
2. Program PB_SIx_TADDR register with PCI base address
3. Set translation attributes and enable translation in PB_SIx_CTL register
4. Ensure that P1_CSR[BM] bit is set to allow PCI mastership to Power-
SPAN II
This is usually done by the PCI enumerator
The following programming example for 60x bus slave image 1 shows the register
contents necessary to map 256 MBytes of 60x bus space, beginning at address
20000000
16
to PCI memory space address 0.
Table 27: 60x Bus Slave Image#0 Programming Example
PowerSPAN II
Register
Register Contents Comment
PB_SI0_BADDR 20000000
16
60x bus address: 20000000
16
PB_SI0_TADDR 00000008
16
PCI memory space address: 00000000
16
Mx = 1: Claim transactions from all masters.
PB_SI0_CTL D0000040
16
IMG_EN = 1: Image enabled
TA_EN = 1: Translation enabled
MD_EN = 0: Master decode disabled
BS = 10000
2
: Block size 256 MByte
MODE = 0: Map to PCI memory space
PRKEEP = 0: Do not keep prefetched data.
END = 10
2
: Big endian data format
RD_AMT = 0: 8 byte prefetch
P1_CSR 02B00006
16
MS = 1: Memory space enable
BM = 1: Bus master enable