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IN-5
I
N
D
E
X
L2 Cache SRAM Size
L2 cache support
SMC
L2CLK bits
L2CLM_
latency
PCI Slave
Little Endian
mode of PPC devices
little-endian mode
Lock Resolution
M
Main Memory
map decoders
mapping
master initiated termination
mcken
memory
ECC
Memory Controller
memory map
PCI local bus
processor (default)
Memory maps
memory maps
Memory Subsystem Data
mien
Miscellaneous
MVME5100 features
MODFAIL Bit Register
MODRST Bit Register
MPC arbiter
MPC bus address space
MPC slave
MPC slave response command types
MPC to PCI address decoding
MPC750
processor/memory domain
MPIC
MPIC Registers
MPIC registers
MPIC’s involvement
Multi-Processor Interrupt Controller
MVME Key Features
MVME5100
MVME5100 Block Diagram
MVME510x VME Processor Module
N
NVRAM
NVRAM/RTC & Watchdog Timer
O
SMC
P
P2 I/O modes
PCI Slave
Parity checking
PC100 ECC
PCI
arbiter, Hawk internal version
arbitration
Configuration Register map
contention with PPC
FIFO
FIFO, as used with PCI Slave
Summary of Contents for MVME5100 Series
Page 1: ...MVME5100 Single Board Computer Programmer s Reference Guide V5100A PG2 September 2001 Edition ...
Page 16: ...xvi ...
Page 20: ...xx ...
Page 28: ...xxviii ...
Page 62: ...1 34 Computer Group Literature Center Web Site Product Data and Memory Maps 1 ...
Page 278: ...3 88 Computer Group Literature Center Web Site System Memory Controller SMC 3 ...
Page 288: ...4 10 Computer Group Literature Center Web Site Hawk Programming Details 4 ...
Page 320: ...Index IN 12 Computer Group Literature Center Web Site I N D E X ...