App. - 34 App. - 34
APPENDIXES
(2) Error completion (receive wait timeout error)
C24
LCPU
Execute dedicated
instruction
(G(P).CPRTCL)
Completion device
Status display device
at completion
t: Receive waiting time
ON at error
completion
* Only if it is specified
(Receive
buffer clear)
Receive packet
Receive packet
Other device
Error occurs
Verification
mismatch
POINT
• When variables are included in receive packet elements, variable parts are not
verified.
• With multiple receive packet specifications, receive data are verified with
registered receive packet information starting from information of the first
registered packet, in the registration order. Once the receive data match one of
them, the receiving process is performed and the following verification is
cancelled.
• The number of a receive packet which is matched in the verification is stored in
the control data of the dedicated instruction (CPRTCL instruction).
Summary of Contents for MELSEC LJ71C24
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Page 18: ...A 16 A 16 INDEX REVISIONS WARRANTY...
Page 22: ...A 20 A 20 2 LJ71C24 R2 LJ71C24 R2 Before Using the Product...
Page 23: ...A 21 A 21 MEMO...
Page 38: ...4 2 4 2 4 PROCEDURES PRIOR TO OPERATION MEMO 4...
Page 105: ...7 30 7 30 7 SETTINGS FOR THE C24 MEMO...
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