LSI LSI53C895A, Technical Manual

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2-62 Functional Description
2.6.3 Power State D2
Power state D2 is a lower power state than D1. In this state the
LSI53C895A core is placed in the coma mode. The following PCI
Configuration Space command register enable bits are suppressed:
•
I/O Space Enable
•
Memory Space Enable
•
Bus Mastering Enable
•
SERR/Enable
•
Enable Parity Error Response
Thus, the memory and I/O spaces cannot be accessed, and the
LSI53C895A cannot be a PCI bus master. Furthermore, all interrupts are
disabled when in power state D2. If changed from power state D2 to
power state D0, the previous values of the PCI command register are
restored. Also, any pending interrupts before the function entered power
state D2 are asserted.
2.6.4 Power State D3
Power state D3 is the minimum power state, which includes settings
called D3hot and D3cold. D3hot allows the device to transition to D0
using software. The LSI53C895A is considered to be in power state
D3cold when power is removed from the device. D3cold can transition to
D0 by applying V
CC
and resetting the device. Furthermore, the device's
soft reset is continually asserted while in power state D3, which clears
all pending interrupts and 3-states the SCSI bus. In addition, the device's
PCI command register is cleared and the Clock Quadrupler is disabled,
which results in additional power savings.