LSI LSI53C895A, Technical Manual

Page: 323 / 364

SCSI Timing Diagrams 6-63
Figure 6.39 Initiator and Target Synchronous Transfer
Table 6.50 Ultra2 SCSI Transfers 40.0 Mbytes (8-Bit Transfers) or 80.0 Mbytes
(16-Bit Transfers) Quadrupled 40 MHz Clock
1, 2
1. Transfer period bits (bits [7:5] in the SCSI Transfer (SXFER) register) are set to zero and the Extra
Clock Cycle of Data Setup bit (bit 7 in SCSI Control One (SCNTL1) ) is set.
2. During Ultra2 SCSI transfers, the value of the Extend REQ/ACK Filtering bit ( SCSI Test Two
(STEST2) , bit 1) has no effect.
Symbol Parameter Min Max Unit
t
1
Send SREQ/ or SACK/ assertion pulse width 8 – ns
t
2
Send SREQ/ or SACK/ deassertion pulse width 8 – ns
t
1
Receive SREQ/ or SACK/ assertion pulse width 6.5 – ns
t
2
Receive SREQ/ or SACK/ deassertion pulse width 6.5 – ns
t
3
Send data setup to SREQ/ or SACK/ asserted 9.5 – ns
t
4
Send data hold from SREQ/ or SACK/ asserted 9.5 – ns
t
5
Receive data setup to SREQ/ or SACK/ asserted 4.5 – ns
t
6
Receive data hold from SREQ/ or SACK/ asserted 4.5 – ns
SREQ/
or SACK/
Send Data
SD[15:0]/, SDP[1:0]/
Receive Data
SD[15:0]/,
SDP[1:0]/
t
3
t
4
t
1
t
2
t
5
t
6
n n + 1
Valid n Valid n + 1
Valid n Valid n + 1