LSI LSI53C895A Technical Manual Download Page 53

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SCSI Functional Description

2-27

Table 2.3

Bits Used for Parity Control and Generation

Bit Name

Location

Description

Assert SATN/ on
Parity Errors

SCSI Control Zero
(SCNTL0)

, Bit 1

Causes the LSI53C895A to automatically assert SATN/
when it detects a SCSI parity error while operating as an
initiator.

Enable Parity
Checking

SCSI Control Zero
(SCNTL0)

, Bit 3

Enables the LSI53C895A to check for parity errors. The
LSI53C895A checks for odd parity.

Assert Even SCSI
Parity

SCSI Control One
(SCNTL1)

, Bit 2

Determines the SCSI parity sense generated by the
LSI53C895A to the SCSI bus.

Disable Halt on
SATN/ or a Parity
Error (Target Mode
Only)

SCSI Control One
(SCNTL1)

, Bit 5

Causes the LSI53C895A not to halt operations when a
parity error is detected in target mode.

Enable Parity Error
Interrupt

SCSI Interrupt
Enable Zero
(SIEN0)

, Bit 0

Determines whether the LSI53C895A generates an
interrupt when it detects a SCSI parity error.

Parity Error

SCSI Interrupt
Status Zero
(SIST0)

, Bit 0

This status bit is set whenever the LSI53C895A detects a
parity error on the SCSI bus.

Status of SCSI
Parity Signal

SCSI Status Zero
(SSTAT0)

, Bit 0

This status bit represents the active HIGH current state of
the SCSI SDP0 parity signal.

SCSI SDP1 Signal

SCSI Status Two
(SSTAT2)

, Bit 0

This bit represents the active HIGH current state of the
SCSI SDP1 parity signal.

Latched SCSI Parity

SSTAT 2, Bit 3 and

SCSI Status One
(SSTAT1)

, Bit 3

These bits reflect the SCSI odd parity signal
corresponding to the data latched into the

SCSI Input

Data Latch (SIDL)

Master Parity Error
Enable

Chip Test Four
(CTEST4)

, Bit 3

Enables parity checking during PCI master data phases.

Master Data Parity
Error

DMA Status
(DSTAT)

, Bit 6

Set when the LSI53C895A

as a PCI master, detects a

target device signaling a parity error during a data phase.

Master Data Parity
Error Interrupt
Enable

DMA Interrupt
Enable (DIEN)

Bit 6

By clearing this bit, a Master Data Parity Error does not
cause assertion of INTA/ (or INTB/), but the status bit is
set in the

DMA Status (DSTAT)

Summary of Contents for LSI53C895A

Page 1: ...S14028 B LSI53C895A PCI to Ultra2 SCSI Controller TECHNICAL MANUAL A p r i l 2 0 0 1 Version 2 2...

Page 2: ...in at any time without notice LSI Logic does not assume any responsibility or liability arising out of the application or use of any product described herein except as expressly agreed to in writing b...

Page 3: ...sed personal computers workstations servers or embedded applications Organization This document has the following chapters and appendixes Chapter 1 General Description includes general information abo...

Page 4: ...eet New York NY 10036 212 642 4900 Ask for document number X3 131 199X SCSI 2 Global Engineering Documents 15 Inverness Way East Englewood CO 80112 800 854 7179 or 303 397 7956 outside U S FAX 303 397...

Page 5: ...ctive Hexadecimal numbers are indicated by the prefix 0x for example 0x32CF Binary numbers are indicated by the prefix 0b for example 0b0011 0010 1100 1111 Revision Record Revision Date Remarks 0 5 4...

Page 6: ...vi Preface...

Page 7: ...ity 1 10 Chapter 2 Functional Description 2 1 PCI Functional Description 2 2 2 1 1 PCI Addressing 2 2 2 1 2 PCI Bus Commands and Functions Supported 2 4 2 1 3 PCI Cache Mode 2 9 2 2 SCSI Functional De...

Page 8: ...gement 2 60 2 6 1 Power State D0 2 61 2 6 2 Power State D1 2 61 2 6 3 Power State D2 2 62 2 6 4 Power State D3 2 62 Chapter 3 Signal Descriptions 3 1 LSI53C895A Functional Signal Grouping 3 2 3 2 Sign...

Page 9: ...k Move Instruction 5 5 5 3 1 First Dword 5 6 5 3 2 Second Dword 5 12 5 4 I O Instruction 5 13 5 4 1 First Dword 5 13 5 4 2 Second Dword 5 21 5 5 Read Write Instructions 5 22 5 5 1 First Dword 5 22 5 5...

Page 10: ...y Appendix B External Memory Interface Diagram Examples Index Customer Feedback Figures 1 1 Typical LSI53C895A System Application 1 2 1 2 Typical LSI53C895A Board Application 1 3 2 1 LSI53C895A Block...

Page 11: ...Address and Data 6 25 6 19 Back to Back Read 32 Bit Address and Data 6 27 6 20 Back to Back Write 32 Bit Address and Data 6 29 6 21 Burst Read 32 Bit Address and Data 6 31 6 22 Burst Read 64 Bit Addr...

Page 12: ...B 4 Tables 2 1 PCI Bus Commands and Encoding Types for the LSI53C895A 2 4 2 2 PCI Cache Mode Alignment 2 13 2 3 Bits Used for Parity Control and Generation 2 27 2 4 SCSI Parity Control 2 28 2 5 SCSI P...

Page 13: ...ress Ratings 6 2 6 2 Operating Conditions 6 2 6 3 LVD Driver SCSI Signals SD 15 0 SDP 1 0 SREQ SREQ2 SACK SACK2 SMSG SIO SCD SATN SBSY SSEL SRST 6 3 6 4 LVD Receiver SCSI Signals SD 15 0 SDP 1 0 SREQ...

Page 14: ...Burst Write 32 Bit Address and Data 6 34 6 31 Burst Write 64 Bit Address and 32 Bit Data 6 36 6 32 External Memory Read 6 39 6 33 External Memory Write 6 43 6 34 Normal Fast Memory 128 Kbytes Single B...

Page 15: ...16 Bit Transfers 80 MHz Clock 6 62 6 50 Ultra2 SCSI Transfers 40 0 Mbytes 8 Bit Transfers or 80 0 Mbytes 16 Bit Transfers Quadrupled 40 MHz Clock 6 63 6 51 272 BGA Pin List by Location 6 66 6 52 BGA...

Page 16: ...xvi Contents...

Page 17: ...a 208 Plastic Quad Flat Pack PQFP and a 272 Ball Grid Array BGA The LSI53C895A can be used as a drop in replacement for the LSI53C895 The LSI53C895A has a local memory bus for local storage of the dev...

Page 18: ...typical LSI53C895A system and Figure 1 2 illustrates a typical LSI53C895A board application Figure 1 1 Typical LSI53C895A System Application PCI Bus Interface Controller LSI53C895A PCI to Wide Ultra2...

Page 19: ...ary scanning Supports RAID ready alternative interrupt signaling Supports PC99 Power Management Automatically downloads Subsystem Vendor ID Subsystem ID and PCI power management levels D0 D1 D2 and D3...

Page 20: ...es s This advantage is most noticeable in heavily loaded systems or with applications with large block requirements such as video on demand and image processing An advantage of Ultra2 SCSI is that it...

Page 21: ...d up by terminators Active negation is enabled by setting bit 7 in the SCSI Test Three STEST3 register TolerANT receiver technology improves data integrity in unreliable cabling environments where oth...

Page 22: ...e length Save the cost of external differential transceivers Support a long term performance migration path Bursts up to 512 bytes across the PCI bus through its 944 byte FIFO Performs wide Ultra2 SCS...

Page 23: ...etic capability with the Expanded Register Move instruction 1 5 2 PCI Performance To improve PCI performance the LSI53C895A Complies with PCI 2 2 specification Supports 32 bit 33 MHz PCI interface wit...

Page 24: ...PTS storage Reduced SCSI development effort Compiler compatible with existing LSI53C7XX and LSI53C8XX family SCRIPTS Direct connection to PCI and SCSI SE LVD and HVD needs external transceivers Develo...

Page 25: ...all registers and all SCSI bus signals Fetch Master and Memory Access control pins Separate SCSI and system clocks SCSI clock quadrupler bits enable Ultra2 SCSI transfer rates with a 40 MHz SCSI cloc...

Page 26: ...gnals for improved fast SCSI transfer rates Input signal filtering on SCSI receivers improves data integrity even in noisy cabling environments 1 5 7 Testability The LSI53C895A provides improved testa...

Page 27: ...Parallel ROM Interface Section 2 4 Serial EEPROM Interface Section 2 5 Alternative SSVID SSID Loading Mechanism Section 2 6 Power Management The LSI53C895A PCI to Ultra2 SCSI Controller is composed o...

Page 28: ...ters Memory space for operating registers 32 Bit PCI Interface PCI Configuration Register 8 Kbyte SCRIPTS RAM 8 Dword SCRIPTS Prefetch Buffer 944 byte DMA FIFO SCSI SCRIPTS Processor Operating Registe...

Page 29: ...device is assigned a base address for I O and memory accesses In the case of the LSI53C895A the upper 24 bits of the address are selected On every access the LSI53C895A compares its assigned base add...

Page 30: ...LSI53C895A C_BE 3 0 Command Type Supported as Master Supported as Slave 0b0000 Interrupt Acknowledge No No 0b0001 Special Cycle No No 0b0010 I O Read Yes Yes 0b0011 I O Write Yes Yes 0b0100 Reserved...

Page 31: ...ever generates this command as a master 2 1 2 6 Memory Read Command The Memory Read command reads data from an agent mapped in the Memory Address Space The target is free to do an anticipatory read fo...

Page 32: ...hen the following conditions are met The CLSE bit Cache Line Size Enable bit 7 DMA Control DCNTL register and the ERMP bit Enable Read Multiple bit 2 DMA Mode DMODE register are set The Cache Line Siz...

Page 33: ...ssuing this command If the cache mode is disabled Read Line commands are not issued If the cache mode is enabled a Read Line command is issued on all read cycles except nonprefetch opcode fetches when...

Page 34: ...rol DCNTL register WRIE bit Write and Invalidate Enable bit 0 Chip Test Three CTEST3 register and PCI configuration Command register bit 4 are set 2 The Cache Line Size register contains a legal burst...

Page 35: ...continues to transfer up to a cache line boundary At that point the chip relinquishes the bus and finishes the transfer at a later time using another bus ownership If the chip is transferring multiple...

Page 36: ...to or greater than the Cache Line Size register The DMA Mode DMODE register bits 7 6 and Chip Test Five CTEST5 bit 2 are the burst length bits The part must be doing a PCI Master transfer The followi...

Page 37: ...not required nor optimal per PCI 2 2 specification and reads will always be either a programmed burst length in size as set in the DMA Mode DMODE and Chip Test Three CTEST3 registers In the case of a...

Page 38: ...onal Description A single Memory Write to align to a cache boundary Multiple Memory Write and Invalidates A single data residual Memory Write to complete the transfer Table 2 2 describes PCI cache mod...

Page 39: ...onal Description 2 13 Table 2 2 PCI Cache Mode Alignment Host Memory A 0x00 B 0x04 0x08 C 0x0C D 0x10 0x14 0x18 0x1C E 0x20 0x24 0x28 0x2C F 0x30 0x34 0x38 0x3C G 0x40 0x44 0x48 0x4C H 0x50 0x54 0x58...

Page 40: ...y Write and Invalidate Read Example 1 Burst 4 Dwords Cache Line Size 4 Dwords A to B MRL 6 bytes A to C MRL 13 bytes A to D MRL 15 bytes MR 2 bytes C to D MRM 5 bytes C to E MRM 15 bytes MRM 6 bytes D...

Page 41: ...to D MRM 17 bytes C to D MRM 5 bytes C to E MRM 21 bytes D to F MRM 31 bytes MR 1 byte A to H MRM 31 bytes MRM 32 bytes MRM 18 bytes A to G MRM 31 bytes MRM 32 bytes MR 3 bytes A to B MRL 6 bytes A t...

Page 42: ...bytes A to C MW 13 bytes A to D MW 17 bytes C to D MW 5 bytes C to E MW 3 bytes MWI 16 bytes MW 2 bytes D to F MW 15 bytes MWI 16 bytes MW 1 byte A to H MW 15 bytes MWI 16 bytes MWI 16 bytes MWI 16 by...

Page 43: ...4 Dwords A to B MW 6 bytes A to C MW 13 bytes A to D MW 17 bytes C to D MW 5 bytes C to E MW 3 bytes MWI 16 bytes MW 2 bytes D to F MW 15 bytes MWI 16 bytes MW 1 byte A to H MW 15 bytes MWI 32 bytes M...

Page 44: ...performed and Memory Write and Invalidate commands are not issued The LSI53C895A is little endian only 2 2 SCSI Functional Description The LSI53C895A provides an Ultra2 SCSI controller that supports...

Page 45: ...ost memory or internal SCRIPTS RAM Algorithms written in SCSI SCRIPTS control the actions of the SCSI and DMA cores The SCRIPTS processor executes complex SCSI bus sequences independently of the host...

Page 46: ...er types of access to the RAM by the chip except Load Store use the PCI bus as if they were external accesses The SCRIPTS RAM powers up enabled by default The RAM can be relocated by the PCI system BI...

Page 47: ...ity Crossing the 4 Gbyte boundary on any one SCRIPTS operation is not permitted and software needs to take care that any given SCRIPTS operation will not cross the 4 Gbyte boundary 2 2 4 Hardware Cont...

Page 48: ...in the draft standard make the following software and hardware adjustments to accommodate Ultra2 SCSI transfers Set the Ultra Enable bit to enable Ultra2 SCSI transfers Set the TolerANT Enable bit bi...

Page 49: ...e maximum burst size that it can perform based on the burst length as determined by the values in the DMA Mode DMODE register If the unit cannot perform bursts of at least four Dwords it disables itse...

Page 50: ...NTL register bit 6 is set The unit flushes whenever this bit is set The bit is self clearing 2 2 7 Opcode Fetch Burst Capability Setting the Burst Opcode Fetch Enable bit bit 1 in the DMA Mode DMODE r...

Page 51: ...e optional CLAMP HIGH Z and IDCODE instructions The LSI53C895A uses an 8 bit instruction register to support all boundary scan instructions The data registers included in the device are the Boundary D...

Page 52: ...s Programming Guide 2 2 11 Parity Options The LSI53C895A implements a flexible parity scheme that allows control of the parity sense allows parity checking to be turned on or off and has the ability t...

Page 53: ...y error Parity Error SCSI Interrupt Status Zero SIST0 Bit 0 This status bit is set whenever the LSI53C895A detects a parity error on the SCSI bus Status of SCSI Parity Signal SCSI Status Zero SSTAT0 B...

Page 54: ...Checks for odd parity on SCSI data received Parity is generated when sending SCSI data Asserts even parity when sending SCSI data Table 2 5 SCSI Parity Errors and Interrupts DHP1 1 DHP Disable Halt o...

Page 55: ...5 in the Chip Test Five CTEST5 register PCI Interface PCI Interface PCI Interface PCI Interface DMA FIFO 64 bits X 118 DMA FIFO 64 bits X 118 DMA FIFO 64 bits X 118 DMA FIFO 64 bits X 118 SODL Registe...

Page 56: ...The data path through the LSI53C895A is dependent on whether data is being moved into or out of the chip and whether SCSI data is being transferred asynchronously or synchronously Figure 2 4 shows ho...

Page 57: ...e of the DFIFO register AND the result with 0x7F for a byte count between zero and 112 If the DMA FIFO size is set to 944 bytes bit 5 of the Chip Test Five CTEST5 register is set subtract the 10 least...

Page 58: ...of the DMA Byte Counter DBC register from the 7 bit value of the DMA FIFO DFIFO register AND the result with 0x7F for a byte count between zero and 112 If the DMA FIFO size is set to 944 bytes bit 5...

Page 59: ...the DMA FIFO register AND the result with 0x3FF for a byte count between zero and 944 Step 2 Read bit 7 in the SCSI Status Zero SSTAT0 and SCSI Status Two SSTAT2 registers to determine if any bytes a...

Page 60: ...e signal lines The negative signals perform the SCSI data and control function In the SE mode the positive signals become virtual ground drivers In the HVD mode the positive signals provide directiona...

Page 61: ...s bit 3 states the BSY SEL and RST pads so they can be used as pure input pins In addition to the standard SCSI lines the signals shown in Table 2 6 are used by the LSI53C895A during HVD operation In...

Page 62: ...no lower than the transceiver IOL can tolerate but not so high as to cause RC timing problems The three remaining pins SSEL SBSY and SRST are connected to the SN75976A with a pull down resistor The pu...

Page 63: ...L BSY RST REQ BSY RST ACK MSG C_D I_O ATN VDD 1 5 K DIFFSENS Schottky Diode DIFFSENS pin 21 SEL SCSI Bus SEL BSY BSY RST 42 RST REQ REQ ACK ACK MSG MSG C D C D I O I O ATN ATN 1B 1B 2B 2B 3B 3B 4B 4B...

Page 64: ...de a means of accommodating terminators There should be a means of disabling the termination SE cables can use a 220 pull up resistor to the terminator power supply Term Power line and a 330 pull down...

Page 65: ...he Selection and Reselection Enable bits SCSI Chip ID SCID bits 5 and 6 respectively should both be asserted so that the LSI53C895A may respond as an initiator or as a target If only selection is enab...

Page 66: ...data from the SCSI bus at a synchronous transfer period as short as 25 ns regardless of the transfer period used to send data The LSI53C895A can receive data at one fourth of the divided SCLK frequen...

Page 67: ...at which data can be received is 40 MHz 160 1 4 40 SCLK Clock Quadrupler QCLK SCF Divider CCF Divider Synchronous Divider Asynchronous SCSI Logic Divide by 4 SCF2 SCF1 SCF0 SCF Divisor 0 0 1 1 0 1 0 1...

Page 68: ...0 Mbytes s on a 16 bit LVD SCSI bus The LSI53C895A has a SCSI clock quadrupler that must be enabled for the chip to perform Ultra2 SCSI transfers with a 40 MHz oscillator In addition the following bit...

Page 69: ...nterrupts for long waits and use polling for short waits 2 2 16 2 Registers The registers in the LSI53C895A that are used for detecting or defining interrupts are Interrupt Status Zero ISTAT0 Interrup...

Page 70: ...s receiving data from the SCSI bus and a fatal interrupt condition occurs the chip attempts to send the contents of the DMA FIFO to memory before generating the interrupt If the LSI53C895A is sending...

Page 71: ...PTS instruction during SCRIPTS execution 2 2 16 3 Fatal vs Nonfatal Interrupts A fatal interrupt as the name implies always causes the SCRIPTS to stop running All nonfatal interrupts become fatal when...

Page 72: ...epends on whether polling or hardware interrupts are being used whether the interrupt is fatal or nonfatal and whether the chip is operating in the Initiator or Target mode If a nonfatal interrupt is...

Page 73: ...additional bits in the extra registers behind SCSI Interrupt Status Zero SIST0 SCSI Interrupt Status One SIST1 and DMA Status DSTAT When the first level of interrupts are cleared all the interrupts th...

Page 74: ...tion fetch the fetch is completed except in the case of a Bus Fault Execution does not begin but the DMA SCRIPTS Pointer DSP points to the next instruction since it is updated when the current instruc...

Page 75: ...ermine what action is required to service the interrupts 5 If both the SIP and DIP bits are set read SCSI Interrupt Status Zero SIST0 SCSI Interrupt Status One SIST1 and DMA Status DSTAT to clear the...

Page 76: ...sing multiple interrupt inputs The LSI53C895A supports four different interrupt routing modes Additional information for these modes may be found in the Register 0x4D SCSI Test One STEST1 description...

Page 77: ...ersions of the LSI Logic drivers support this capability The third option is to have the system BIOS not report the existence of the SCSI controller when the SCSI BIOS and operating systems make PCI B...

Page 78: ...he following MOVE instruction MOVE 5 9 when Data_Out Moves five bytes from address 0x09 in the host memory to the SCSI bus 2 2 18 1 Wide SCSI Send Bit The WSS bit is set whenever the SCSI controller i...

Page 79: ...ses 2 2 18 2 Wide SCSI Receive Bit The WSR bit is set whenever the SCSI controller is receiving data Data In for initiator or Data Out for target and the controller detects a partial transfer at the e...

Page 80: ...ransferred to memory The contents of the SWIDE register should be the first byte transferred to memory at the start of the chained Block Move data stream Since the byte count always represents data tr...

Page 81: ...ed Block Moves 2 3 Parallel ROM Interface The LSI53C895A supports up to one megabyte of external memory in binary increments from 16 Kbytes to allow the use of expansion ROM for add in PCI cards This...

Page 82: ...f the external memory interface is not used MAD 3 1 should be pulled HIGH Note There are internal pull downs on all of the MAD bus signals The LSI53C895A allows the system to determine the size of the...

Page 83: ...D SSID Loading Mechanism for additional information 2 4 1 Default Download Mode In this mode MAD7 is pulled down internally GPIO0 is the serial data signal SDA and GPIO1 is the serial clock signal SCL...

Page 84: ...ble 2 8 Mode A Serial EEPROM Data Format Byte Name Description 0xFB SVID 0 Subsystem Vendor ID LSB This byte is loaded into the least significant byte of the Subsystem Vendor ID register in the approp...

Page 85: ...uence is written the next write to offset 0x48 0x4B is shadowed into the Subsystem register At no time can any of the data written to the Subsystem ID register be read back The register always reads b...

Page 86: ...onfiguration Write 6 Read back the Subsystem register at PCI offset 0x2C 0x2F to verify the new value written in Step 5 7 Return to Step 2 to change the subsystem value at offset 0x2C Note During the...

Page 87: ...bles the SCSI CLK Therefore D2 will include this attribute as well as the attributes defined in the Power State D2 section The PCI Function Power States D0 D1 D2 and D3 are described below Power state...

Page 88: ...ious values of the PCI command register are restored Also any pending interrupts before the function entered power state D2 are asserted 2 6 4 Power State D3 Power state D3 is the minimum power state...

Page 89: ...s chapter contains the following sections Section 3 1 LSI53C895A Functional Signal Grouping Section 3 2 Signal Descriptions Section 3 3 PCI Bus Interface Signals Section 3 4 SCSI Bus Interface Signals...

Page 90: ...REQ GNT PERR SERR IRQ ALT_IRQ GPIO0_FETCH GPIO1_MASTER GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 MWE MCE MOE MAC _TESTOUT MAS0 MAS1 MAD 7 0 SCLK SD 15 0 SDP 1 0 DIFFSENS SCD SIO SMSG SREQ SREQ2 SACK...

Page 91: ...Several signals in the LSI53C895A have internal pull up resistors Table 3 1 describes the conditions that enable these pull ups I Input a standard input only signal O Output a standard output driver t...

Page 92: ...I N A Clock provides timing for all transactions on the PCI bus and is an input to every PCI device All other PCI signals are sampled on the rising edge of CLK and other timing parameters are defined...

Page 93: ...2 bit physical byte address If the command is a DAC implying a 64 bit address a second address phase is required During the first phase AD 31 0 will contain the lower 32 bits of the address followed b...

Page 94: ...current master to indicate the beginning and duration of an access FRAME is asserted to indicate that a bus transaction is beginning While FRAME is deasserted either the transaction is in the final da...

Page 95: ...serted until both IRDY and TRDY are asserted together STOP 27 W11 S T S 8 mA PCI Stop indicates that the selected target is requesting the master to stop the current transaction DEVSEL 25 Y10 S T S 8...

Page 96: ...CI bus has been granted This is a point to point signal Every master has its own GNT signal Table 3 6 Error Reporting Signals Name PQFP BGA Pos Type Strength Description PERR 28 V11 S T S 8 mA PCI Par...

Page 97: ...es that an interrupting condition has occurred and that service is required from the host CPU The output drive of this pin is open drain ALT_IRQ 1 Y2 O 8 mA PCI Alt Interrupt Request When asserted LOW...

Page 98: ...the LSI53C895A is bus master This pin is programmable at power up through the MAD7 pin to serve as the clock signal for the serial EEPROM interface GPIO2 65 R20 I O 8 mA SCSI General Purpose I O pin T...

Page 99: ...9 SCSI Bus Interface Signal Name PQFP BGA Pos Type Strength Description SCLK 80 J20 I N A SCSI Clock is used to derive all SCSI related timings The speed of this clock is determined by the application...

Page 100: ...J2 G19 F19 E19 D19 B9 B8 B7 A5 A4 A3 B2 D1 F3 C10 I O 48 mA SCSI SCSI Data SCSI Parity LVD Mode Positive half of LVDlink pair for SCSI data lines SD 15 0 are the 16 bit data bus and SDP 1 0 are the S...

Page 101: ...SI phase line input output SCSI phase line message Data handshake line from target device Data handshake line from target device Duplicate of SREQ and SREQ enabled by pulling MAD5 HIGH at reset Data h...

Page 102: ...nable signal to an external EEPROM or flash memory during read operations It is also used to test the connectivity of the LSI53C895A signals in test mode MAC _ TESTOUT 79 K19 O 16 mA Memory Access Con...

Page 103: ...71 72 74 75 76 77 N19 N20 M18 M19 M20 L19 L20 K20 I O 4 mA Memory Address Data Bus This bus is used in conjunction with the memory address strobe pins and external address latches to assemble up to a...

Page 104: ...181 L1 I N A Test Mode Select The signal received at TMS is decoded by the TAP controller to control JTAG test operations This pin has a static pull down TDI 183 L3 I N A Test Data In Serial test inst...

Page 105: ...4 144 164 174 184 197 D6 D11 D15 F4 F17 K4 L17 R4 R17 U6 U10 U15 P N A Power for PCI bus drivers receivers SCSI bus drivers receivers local memory interface drivers receivers and other I O pins VDD_CO...

Page 106: ...O driver pad rows and digital core have isolated power supplies as indicated by the I O and CORE extensions on their respective VSS and VDD names These power and ground pins should be connected direct...

Page 107: ...EPROM Interface in Chapter 2 and Subsystem ID and Subsystem Vendor ID registers in Chapter 4 for additional information MAD 6 This signal is Reserved and may be left floating MAD 5 Enables duplicate S...

Page 108: ...icates a pull up resistor is attached MAD 0 This pin is the slow ROM pin When pulled up it enables two extra cycles of data access time to allow use of slower memory devices Note All MAD pins have int...

Page 109: ...s in registers are active HIGH that is the feature is enabled by setting the bit The bottom row of every register diagram shows the default register values which are enabled after the chip is powered...

Page 110: ...tency Timer Cache Line Size 0x0C Base Address Register Zero I O 0x10 Base Address Register One MEMORY bits 31 0 0x14 Base Address Register Two SCRIPTS RAM 0x18 Not Supported 0x1C Not Supported 0x20 No...

Page 111: ...e LSI53C895A Device ID is 0x0012 Registers 0x04 0x05 Command Read Write The Command register provides coarse control over a device s ability to generate and respond to PCI cycles When a zero is writte...

Page 112: ...bit in the DMA Control DCNTL register must also be set for the device to generate Write and Invalidate commands R Reserved 3 EBM Enable Bus Mastering 2 This bit controls the ability of the LSI53C895A...

Page 113: ...onding bit location is a one For instance to clear bit 15 and not affect any other bits write the value 0x8000 to the register DPE Detected Parity Error from Slave 15 This bit is set by the LSI53C895A...

Page 114: ...Data Parity Error Reported 8 This bit is set when all of the following conditions are met The bus agent asserted PERR itself or observed PERR asserted The agent setting this bit acted as the bus mast...

Page 115: ...is a subclass code and the lower byte identifies a specific register level programming interface The value of this register is 0x010000 which identifies a SCSI controller Register 0x0C Cache Line Size...

Page 116: ...The Latency Timer register specifies in units of PCI bus clocks the value of the Latency Timer for this PCI bus master The LSI53C895A supports this timer All eight bits are writable allowing latency v...

Page 117: ...iled information on the operation of this register refer to the PCI 2 2 specification Registers 0x14 0x17 Base Address Register One MEMORY Read Write BAR1 Base Address Register One 31 0 This base addr...

Page 118: ...register refer to the PCI 2 2 specification Registers 0x1C 0x27 Not Supported Registers 0x28 0x2B Reserved Registers 0x2C 0x2D Subsystem Vendor ID Read Only SVID Subsystem Vendor ID 15 0 This 16 bit r...

Page 119: ...ase see Section 2 4 Serial EEPROM Interface in Chapter 2 for more information on downloading a value for this register In addition if the Subsystem ID Access register 0x48 0x4B is enabled and unlocked...

Page 120: ...ection 2 5 Alternative SSVID SSID Loading Mechanism in Chapter 2 for additional information Registers 0x30 0x33 Expansion ROM Base Address Read Write ERBA Expansion ROM Base Address 31 0 This four byt...

Page 121: ...ze of the external memory is set through MAD 3 1 Please see the section on MAD Bus Programming for the possible size encodings available Register 0x34 Capabilities Pointer Read Only CP Capabilities Po...

Page 122: ...errupt pin the device uses Its value is set to 0x01 for the INTA signal Register 0x3E Min_Gnt Read Only MG MIN_GNT 7 0 This register is used to specify the desired settings for latency timer values Mi...

Page 123: ...register to 0x40 Register 0x40 Capability ID Read Only CID Cap_ID 7 0 This register indicates the type of data structure currently being used It is set to 0x01 indicating the Power Management Data St...

Page 124: ...lization 5 This bit is cleared to indicate that the LSI53C895A requires no special initialization before the generic class device driver is able to use it APS Auxiliary Power Source 4 Because the LSI5...

Page 125: ...ot support the data register Therefore these four bits are always cleared PEN PME_Enable 8 The LSI53C895A always returns a zero for this bit to indicate that PME assertion is disabled R Reserved 7 2 P...

Page 126: ...g data The LSI53C895A does not use this register and always returns 0x00 Registers 0x48 0x4B Subsystem ID Access Write Only SIDA Subsystem ID Access 31 0 The Subsystem ID Access register is the PCI co...

Page 127: ...g The address map of the SCSI registers is shown in Table 4 2 Note The only registers that the host CPU can access while the LSI53C895A is executing SCRIPTS are the Interrupt Status Zero ISTAT0 Interr...

Page 128: ...0x28 DSP 0x2C DSPS 0x30 SCRATCH A 0x34 DCNTL SBR DIEN DMODE 0x38 ADDER 0x3C SIST1 SIST0 SIEN1 SIEN0 0x40 GPCNTL0 MACNTL SWIDE SLPAR 0x44 RESPID1 RESPID0 STIME1 STIME0 0x48 STEST3 STEST2 STEST1 STEST0...

Page 129: ...us Zero SSTAT0 register 3 After an arbitration delay the CPU should read the SCSI Bus Data Lines SBDL register to check if a higher priority SCSI ID is present If no higher priority ID bit is set and...

Page 130: ...and the LSI53C895A s ID stored in the SCSI Chip ID SCID register 6 After a selection is complete the Function Complete bit is set in the SCSI Interrupt Status Zero SIST0 register bit 6 7 If a selecti...

Page 131: ...d an interrupt may be generated If the LSI53C895A is operating in the initiator mode and a parity error is detected assertion of SATN is optional but the transfer continues until the target changes ph...

Page 132: ...LSI53C895A drives the contents of the SCSI Output Data Latch SODL register onto the SCSI data bus When the LSI53C895A is an initiator the SCSI I O signal must be inactive to assert the SODL contents...

Page 133: ...not connected to the SCSI bus The CPU can force a connected or disconnected condition by setting or clearing this bit This feature is used primarily during loopback mode RST Assert SCSI RST Signal 3 S...

Page 134: ...he Won Arbitration bit SCSI Status Zero SSTAT0 bit 2 will be set In this case the Immediate Arbitration bit needs to be cleared This completes the abort sequence and disconnects the chip from the SCSI...

Page 135: ...e SCSI core expects a disconnect to occur normally prior to sending an Abort Abort Tag Bus Device Reset Clear Queue or Release Recovery message or before deasserting SACK after receiving a Disconnect...

Page 136: ...nd WSS flag Asserting this bit clears the WSS flag This clearing function is self clearing When the WSS flag is HIGH following a wide SCSI send operation the SCSI core is holding a byte of chain data...

Page 137: ...vior must occur at the start of the next data receive transfer When the flag is set the stored data in SWIDE may be residue data valid data for a subsequent data transfer or overrun data The byte is r...

Page 138: ...es are assumed to be eight bits transmitted on SD 7 0 and SDP0 When this bit is asserted data transfers are done 16 bits at a time with the least significant byte on SD 7 0 and SDP0 and the most signi...

Page 139: ...SRE Enable Response to Selection 5 When this bit is set the LSI53C895A is able to respond to bus initiated selection at the chip ID in the RESPID0 and RESPID1 registers Note that the chip does not au...

Page 140: ...the programmable dividers in the chip The synchronous transfer period the LSI53C895A should use when transferring SCSI data is determined in the following example The LSI53C895A is connected to a hard...

Page 141: ...I 1 SXFERP Synchronous transfer period SSCP SCSI synchronous core period SSCF SCSI synchronous core frequency ExtCC Extra clock cycle of data setup Table 4 3 Examples of Synchronous Transfer Periods a...

Page 142: ...o the synchronous data offset used by the LSI53C895A These bits determine the LSI53C895A s method of transfer for Data In and Data Out phases only all other information transfers occur asynchronously...

Page 143: ...0 0 1 0 0 4 0 0 1 0 1 5 0 0 1 1 0 6 0 0 1 1 1 7 0 1 0 0 0 8 0 1 0 0 1 9 0 1 0 1 0 10 0 1 0 1 1 11 0 1 1 0 0 12 0 1 1 0 1 13 0 1 1 1 0 14 0 1 1 1 1 15 1 0 0 0 0 16 1 0 0 0 1 17 1 0 0 1 0 18 1 0 0 1 1 1...

Page 144: ...IDs in descending order is Register 0x07 General Purpose GPREG0 Read Write Reads to this register will always yield the same values A write to this register will cause the data written to be output to...

Page 145: ...This register contains the first byte received in any asynchronous information transfer phase For example when a LSI53C895A is operating in the initiator mode this register contains the first byte re...

Page 146: ...Read Write REQ Assert SCSI REQ Signal 7 ACK Assert SCSI ACK Signal 6 BSY Assert SCSI BSY Signal 5 SEL Assert SCSI SEL Signal 4 ATN Assert SCSI ATN Signal 3 MSG Assert SCSI MSG Signal 2 C_D Assert SCS...

Page 147: ...n These bits are invalid for targets that are selected under the single initiator option of the SCSI 1 specification This condition is detected by examining the VAL bit above Register 0x0B SCSI Bus Co...

Page 148: ...conditions individually through the DMA Interrupt Enable DIEN register When performing consecutive 8 bit reads of the DSTAT SCSI Interrupt Status Zero SIST0 and SCSI Interrupt Status One SIST1 regist...

Page 149: ...ister SSI Single Step Interrupt 3 If the Single Step Mode bit in the DMA Control DCNTL register is set this bit is set and an interrupt is generated after successful execution of each SCRIPTS instruct...

Page 150: ...gisters of the chip not including ROM or RAM A Load Store instruction is issued when the register address is not aligned with the memory address A Load Store instruction is issued with bit 5 in the DM...

Page 151: ...en sending data synchronously It is not readable or writable by the user It is possible to use this bit to determine how many bytes reside in the chip when an error occurs OLF SODL Least Significant B...

Page 152: ...must be full arbitration and selection to set this bit RST SCSI RST Signal 1 This bit reports the current status of the SCSI RST signal and the SRST signal bit 6 in the Interrupt Status Zero ISTAT0 re...

Page 153: ...ytes or Words in the SCSI FIFO 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 2 0 0 0 1 1 3 0 0 1 0 0 4 0 0 1 0 1 5 0 0 1 1 0 6 0 0 1 1 1 7 0 1 0 0 0 8 0 1 0 0 1 9 0 1 0 1 0 10 0 1 0 1 1 11 0 1 1 0 0 12 0 1 1 0 1...

Page 154: ...STAT2 Read Only ILF1 SIDL Most Significant Byte Full 7 This bit is set when the most significant byte in the SCSI Input Data Latch SIDL contains data Data is transferred from the SCSI bus to the SCSI...

Page 155: ...ete description of this field see the definition for SCSI Status One SSTAT1 bits 7 4 SPL1 Latched SCSI Parity for SD 15 8 3 This active HIGH bit reflects the SCSI odd parity signal corresponding to th...

Page 156: ...indeterminate Register 0x14 Interrupt Status Zero ISTAT0 Read Write This register is accessible by the host CPU while a LSI53C895A is executing SCRIPTS without interfering in the operation of the func...

Page 157: ...default values and all SCSI signals are deasserted Setting this bit does not assert the SCSI RST signal This reset does not clear the ID Mode bit or any of the PCI configuration registers This bit is...

Page 158: ...LSI53C895A is not connected to the SCSI bus INTF Interrupt on the Fly 2 This bit is asserted by an INTFLY instruction during SCRIPTS execution SCRIPTS programs do not halt when the interrupt occurs Th...

Page 159: ...determine exactly which condition s caused the interrupt read the SCSI Interrupt Status Zero SIST0 and SCSI Interrupt Status One SIST1 registers DIP DMA Interrupt Pending 0 This status bit is set whe...

Page 160: ...e SCRIPTS engine is active If it is cleared the SCRIPTS engine is not active This bit is read only and writes will have no effect on the value of this bit SI SYNC_IRQD 0 Setting this bit disables the...

Page 161: ...ster as a read only and the other as a write only will prevent this type of conflict Register 0x17 Mailbox One MBOX1 Read Write MBOX1 Mailbox One 7 0 These are general purpose bits that may be read or...

Page 162: ...status of bytes at the bottom of the FIFO if all FMT bits are set the DMA FIFO is empty Register 0x19 Chip Test One CTEST1 Read Only FFL Byte Full in DMA FIFO 7 0 These status bits identify the top b...

Page 163: ...I O 5 This bit is defined as the Configuration I O Enable Status bit This read only bit indicates if the chip is currently enabled as I O space CM Configured as Memory 4 This bit is defined as the co...

Page 164: ...SCRIPTS Fetch Selector SFS registers return to normal operation Note Bit 3 is the only writable bit in this register All other bits are read only When modifying this register all other bits must be w...

Page 165: ...ta is successfully transferred by the LSI53C895A Note Polling of FIFO flags is allowed during flush operations CLF Clear DMA FIFO 2 When this bit is set all data pointers for the DMA FIFO are cleared...

Page 166: ...eturn instruction is executed This address points to the next instruction to execute Do not write to this register while the LSI53C895A is executing SCRIPTS During any Memory to Memory Move operation...

Page 167: ...5 is set 1 Subtract the ten least significant bits of the DMA Byte Counter DBC register from the 10 bit value of the DFBOC The DFBOC consists of the Chip Test Five CTEST5 register bits 1 and 0 and the...

Page 168: ...sed by Memory to Memory Move operations When this bit is set register accesses to the Temporary TEMP and Data Structure Address DSA registers are directed to the shadow copies STEMP Shadow TEMP and SD...

Page 169: ...64 bit DMA FIFO If the FBL3 bit is set then FBL2 through FBL0 determine which of eight byte lanes can be read or written When cleared the byte lane read or written is determined by the current conten...

Page 170: ...IFO When clear the DMA FIFO appears as only 112 bytes deep When set the DMA FIFO size increases to 944 bytes Using an 112 byte FIFO allows software written for other LSI53C8XX family chips to properly...

Page 171: ...FO DFIFO register bits 7 0 Register 0x23 Chip Test Six CTEST6 Read Write DF DMA FIFO 7 0 Writing to this register writes data to the appropriate byte lane of the DMA FIFO as determined by the FBL bits...

Page 172: ...that are transferred The maximum number of bytes that can be transferred in any one Block Move command is 16 777 215 bytes The maximum value that can be loaded into the DMA Byte Counter DBC register i...

Page 173: ...er At the start of some SCRIPTS operations its value is copied from the DMA SCRIPTS Pointer Save DSPS register Its value may not be valid except in certain abort conditions The default value of this r...

Page 174: ...d execute the next SCRIPTS command When writing this register eight bits at a time writing the upper eight bits begins execution of SCSI SCRIPTS The default value of this register is zero Registers 0x...

Page 175: ...0 of the Scratch Reg ister A SCRATCHA when read Bits 9 0 of SCRATCH A will always return zero in this mode Writes to the SCRATCH A register are unaffected Clearing the PCI Configuration Into Enable bi...

Page 176: ...5 of the Chip Test Five CTEST5 register In the big FIFO mode the LSI53C895A will support burst thresholds of up to 128 Dwords SIOM Source I O Memory Enable 5 This bit is defined as an I O Memory Enab...

Page 177: ...egal BOF Burst Opcode Fetch Enable 1 Setting this bit causes the LSI53C895A to fetch instructions in burst mode Specifically the chip bursts in the first two Dwords of all instructions using a single...

Page 178: ...interrupt is masked by clearing the appropriate mask bit Masking an interrupt prevents IRQ from being asserted for the corresponding interrupt but the status bit is still set in the DSTAT register Mas...

Page 179: ...nts The default value of this register is zero This register is called the DMA Watchdog Timer on previous LSI53C8XX family products Register 0x3B DMA Control DCNTL Read Write CLSE Cache Line Size Enab...

Page 180: ...reshold is set to 16 Dwords or greater the prefetch unit will fetch instructions in one burst of 8 Dwords Burst thresholds of less than 8 Dwords will cause the prefetch unit to be disabled PCI Cache c...

Page 181: ...step mode set the Start DMA bit to restart execution of SCRIPTS after a single step interrupt IRQD IRQ Disable 1 Setting this bit disables the IRQ pin Clearing the bit enables normal operation As with...

Page 182: ...register contains the interrupt mask bits corresponding to the interrupting conditions described in the SCSI Interrupt Status Zero SIST0 register An interrupt is masked by clearing the appropriate mas...

Page 183: ...ons are considered SCSI Gross Errors Data underflow reading the SCSI FIFO when no data is present Data overflow writing to the SCSI FIFO while it is full Offset underflow receiving a SACK pulse in tar...

Page 184: ...pt Enable One SIEN1 Read Write This register contains the interrupt mask bits corresponding to the interrupting conditions described in the SCSI Interrupt Status One SIST1 register An interrupt is mas...

Page 185: ...st to Request target or Acknowledge to Acknowledge initiator period See the description of the SCSI Timer Zero STIME0 register bits 7 4 for more information on the handshake to handshake timer Registe...

Page 186: ...hen the SATN signal is asserted by the initiator CMP Function Complete 6 This bit is set when an arbitration only or full arbitration sequence is completed SEL Selected 5 This bit is set when the LSI5...

Page 187: ...itiator mode and the target device unexpectedly disconnects from the SCSI bus This bit is only valid when the LSI53C895A operates in the initiator mode When the LSI53C895A operates in low level mode a...

Page 188: ...IFFSENS pin detects a change in voltage level that indicates the SCSI bus has switched between SE LVD or HVD modes R Reserved 3 STO Selection or Reselection Time out 2 The SCSI device which the LSI53C...

Page 189: ...SCSI core If one of the bytes received or sent usually the last is the set of correct even parity bits SLPAR should go to zero assuming it started at zero As an example suppose that the following thre...

Page 190: ...tudinal parity function is made to operate as a word wide function During 16 bit transfers the high byte of the SCSI bus is XORed with the high byte of the current longitudinal parity value and the lo...

Page 191: ...on ID and PCI Device ID which will be shadowed in the SCRIPTS Fetch Selector SFS register Any devices that contain the value 0xF in this register should use this mechanism to uniquely identify the dev...

Page 192: ...set regardless of the state of bit 1 GPIO1 FE Fetch Enable 6 The internal opcode fetch signal is presented on GPIO0 if this bit is set regardless of the state of bit 0 GPIO0 LEDC LED_CNTL 5 The inter...

Page 193: ...mum time between SCSI handshakes SREQ to SREQ in target mode or SACK to SACK in initiator mode When this timing is exceeded an interrupt is generated and the HTH bit in the SCSI Interrupt Status One S...

Page 194: ...t Cleared1 1 These values are correct if the CCF bits in the SCSI Control Three SCNTL3 register are set according to the valid combinations in the bit description A quadrupled 40 MHz clock is required...

Page 195: ...his timer to shift by a factor of 16 Refer to the SCSI Timer Zero STIME0 register description for details GEN 3 0 General Purpose Timer Period 3 0 These bits select the period of the general purpose t...

Page 196: ...egisters However the chip can arbitrate with only one ID value in the SCID register Register 0x4B Response ID One RESPID1 Read Write Response ID Zero RESPID0 and RESPID1 contain the selection or resel...

Page 197: ...not take into account the bus settle delay of 400 ns This bit is used for functional test and fault purposes ART Arbitration Priority Encoder Test 2 This bit is always set when the LSI53C895A exhibits...

Page 198: ...hen set this bit disables the external SCLK SCSI Clock pin and the chip uses the PCI clock as the internal SCSI clock When set it will also select the PCI clock as the internal SCSI clock if the inter...

Page 199: ...0 The LSI53C895A supports different interrupt routing modes These modes are described in the following table For additional information on the LSI53C895A interrupt routing modes see Section 2 2 17 In...

Page 200: ...895A to perform SCSI loopback diagnostics That is it enables the SCSI core to simultaneously perform as both the initiator and the target SZM SCSI High Impedance Mode 3 Setting this bit places all the...

Page 201: ...Lines SBCL and input registers Register 0x4F SCSI Test Three STEST3 Read Write TE TolerANT Enable 7 Setting this bit enables the active negation portion of LSI Logic TolerANT technology Active negatio...

Page 202: ...be asserted Assert this bit in SCSI 2 systems so that a single bit error on the SCSI bus is not interpreted as a single initiator response S16 16 Bit System 3 If this bit is set all devices in the SC...

Page 203: ...he SCSI FIFO pointers the SCSI Input Data Latch SIDL SCSI Output Data Latch SODL and SODR a hidden buffer register which is not accessible full bits in the SCSI Status Zero SSTAT0 and SCSI Status Two...

Page 204: ...L contains latched data and the SBDL always contains exactly what is currently on the SCSI data bus Reading this register causes the SCSI parity bit to be checked and causes a parity error interrupt i...

Page 205: ...L SCSI Output Data Latch 15 0 This register is used primarily for diagnostic testing or programmed I O operation Data written to this register is asserted onto the SCSI data bus by setting the Assert...

Page 206: ...that may appear in SCSI Wide Residue SWIDE This byte must be flushed manually This bit also enables the flushing mechanism to flush data during a Data In phase mismatch in a more efficient manner PMJ...

Page 207: ...trols whether or not the FIFO is automatically cleared during a Data Out phase mismatch When set data in the DMA FIFO as well as data in the SCSI Output Data Latch SODL and SODR a hidden buffer regist...

Page 208: ...ycle 3 When this bit is set all 64 bit addressing as a master will be disabled No dual address cycles will be generated by the LSI53C895A When this bit is cleared the LSI53C895A will generate dual add...

Page 209: ...SBDL SCSI Bus Data Lines 15 0 This register contains the SCSI data bus status Even though the SCSI data bus is active low these bits are active HIGH The signal status is not latched and is a true rep...

Page 210: ...8 5 GPIO Enable 3 0 General purpose control corresponding to bits 3 0 in the General Purpose One GPREG1 register GPIO 8 5 power up as general purpose inputs Register 0x5B General Purpose One GPREG1 R...

Page 211: ...13 of the SCRIPTS RAM PCI Base Address Register Two SCRIPTS RAM in bits 31 13 of the SCRATCH B register when read When read bits 12 0 of SCRATCH B will always return zeros in this mode Writes to the S...

Page 212: ...ialized before they are used All selectors can be read written using the Load and Store SCRIPTS instruction Memory to Memory Move Read Write SCRIPTS instruction or CPU with SCRIPTS not running Note Cr...

Page 213: ...ess the MMWS register is always read as 0x00000000 when in the special mode Writes to the MMWS register are unaffected Clearing the PCI Configuration Enable bit causes the MMWS register to return to n...

Page 214: ...31 0 Supplies the upper Dword of a 64 bit address during table indirect fetches and Load and Store Data Structure Address DSA relative operations Registers 0xB0 0xB3 Static Block Move Selector SBMS Re...

Page 215: ...th the upper 32 bit data address upon execution of a 64 bit direct BMOVs Registers 0xB8 0xBB DMA Next Address 64 DNAD64 Read Write DNAD64 DMA Next Address 64 31 0 This register holds the current selec...

Page 216: ...0xC3 Phase Mismatch Jump Address 1 PMJAD1 Read Write PMJAD1 Phase Mismatch Jump Address 1 31 0 This register contains the 32 bit address that will be jumped to upon a phase mismatch Depending upon th...

Page 217: ...8 0xCB Remaining Byte Count RBC Read Write RBC Remaining Byte Count RBC 31 0 This register contains the byte count that remains for the BMOV that was executing when the phase mismatch occurred In the...

Page 218: ...f a SCSI data receive if there is a byte in the SCSI Wide Residue SWIDE register then this address will point to the location where that byte must be stored The SWIDE byte must be manually written to...

Page 219: ...BMOV in which case the ESA will have the address of the table indirect entry and this register will point to the address of the BMOV instruction 31 0 ESA 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 220: ...sent by one This will also happen in an odd byte count wide receive case Also in the case of a wide send in which there is a chain byte from a previous transfer the count will not reflect the chain b...

Page 221: ...s It will count bytes as long as the phase mismatch enable ENPMJ bit in the Chip Control 0 CCNTL0 register is set Unlike the SCSI Byte Count SBC this count will not be cleared on each BMOV instruction...

Page 222: ...4 114 Registers...

Page 223: ...ce Mode Section 5 2 High Level SCSI SCRIPTS Mode Section 5 3 Block Move Instruction Section 5 4 I O Instruction Section 5 5 Read Write Instructions Section 5 6 Transfer Control Instructions Section 5...

Page 224: ...to the external processor Once an interrupt is generated the LSI53C895A halts all operations until the interrupt is serviced Then the start address of the next SCRIPTS instruction may be written to t...

Page 225: ...at points to a SCSI SCRIPTS program for execution Loading the DMA SCRIPTS Pointer DSP register causes the LSI53C895A to fetch its first instruction at the address just loaded This is from main memory...

Page 226: ...lly stored remaining byte count increment the address pointer and then release the PCI bus The LSI53C895A stays off the PCI bus until the FIFO can again hold for a write or has collected for a read en...

Page 227: ...is being moved off of the SCSI bus DIOM controls whether that data goes to I O or memory space System Processor System Memory SCSI Initiator Write Example Select ATN 0 alt_addr Move from identify_msg...

Page 228: ...data to move is in the second Dword of this instruction When this bit is one the 32 bit user data start address for the Block Move is the address of a pointer to the actual data buffer address The val...

Page 229: ...alue in the start address of the move is treated as a relative displacement from the value in the Data Structure Address DSA register Both the transfer count and the source destination address are fet...

Page 230: ...system I O data structures saving time at the beginning of an I O operation The I O data structure can begin on any longword boundary and may cross system segment boundaries There are two restriction...

Page 231: ...ptor Block 6 10 or 12 bytes If the Vendor Unique Enhancement 1 VUE1 bit SCNTL2 bit 1 is set the LSI53C895A receives the number of bytes in the byte count regardless of the group code If the Vendor Uni...

Page 232: ...I bus as an Initiator before executing this instruction 2 The LSI53C895A waits for an unserviced phase to occur An unserviced phase is any phase with SREQ asserted for which the LSI53C895A has not yet...

Page 233: ...andshake 7 When the LSI53C895A is performing a block move for Message In phase it does not deassert the SACK signal for the last SREQ SACK handshake Clear the SACK signal using the Clear SACK I O inst...

Page 234: ...nt is instead fetched from a table pointed to by the Data Structure Address DSA register 5 3 2 Second Dword Start Address 31 0 This 32 bit field specifies the starting address of the data to move to f...

Page 235: ...d but the OpCode bit meanings change in Target mode compared to Initiator mode OpCode bit configurations 101 110 and 111 are considered Read Write instructions and are described in Section 5 5 Read Wr...

Page 236: ...instruction before the reselection completes It continues executing SCRIPTS until a SCRIPT that requires a response from the Initiator is encountered If the LSI53C895A is selected or reselected before...

Page 237: ...SCSI Output Control Latch SOCL register are set Do not set SACK or SATN except for testing purposes When the target bit is set the corresponding bit in the SCSI Control Zero SCNTL0 register is also s...

Page 238: ...g SCRIPTS until a SCRIPT that requires a response from the Target is encountered If the LSI53C895A is selected or reselected before winning arbitration it fetches the next instruction from the address...

Page 239: ...the target bit is set the corresponding bit in the SCSI Control Zero SCNTL0 register is also set When the carry bit is set the corresponding bit in the ALU is set Clear Instruction When the SACK or SA...

Page 240: ...chip SCRIPTS can directly execute operating system I O data structures saving time at the beginning of an I O operation The I O data structure can begin on any Dword boundary and may cross system segm...

Page 241: ...nchronous offset and synchronous period indirectly The value in bits 23 0 of the first four bytes of the SCRIPTS instruction is added to the data structure base address to form the fetch address Sel S...

Page 242: ...ar instruction to set or clear Target mode Setting this bit with a Set instruction configures the LSI53C895A as a Target device this sets bit 0 of the SCSI Control Zero SCNTL0 register Clearing this b...

Page 243: ...he last message byte For example if the Initiator wishes to reject a message it issues an Assert SCSI ATN instruction before a Clear SCSI ACK instruction R Reserved 2 0 5 4 2 Second Dword SA Start Add...

Page 244: ...guration of all these bits determine which instruction is currently selected OPC 2 0 OpCode 29 27 The combinations of these bits determine if the instruction is a Read Write or an I O instruction OpCo...

Page 245: ...Modify Write Cycles During these cycles the register is read the selected operation is performed and the result is written back to the source register The Add operation is used to increment or decrem...

Page 246: ...o SCSI First Byte Received SFBR register Syntax Move data8 to SFBR Move data into register Syntax Move data8 to RegA 0011 Shift register one bit to the left and place the result in the same register S...

Page 247: ...he right and place the result in the register Syntax Move SFBR SHR RegA 110 Add data to register without carry and place the result in the same register Syntax Move RegA data8 to RegA Add data to regi...

Page 248: ...be dependent on a true false comparison of the ALU Carry bit or a comparison of the SCSI information transfer phase with the Phase field and or a comparison of the First Byte Received with the Data Co...

Page 249: ...he comparisons are true it loads the DMA SCRIPTS Pointer DSP register with the contents of the DMA SCRIPTS Pointer Save DSPS register and that address value becomes the address of the next instruction...

Page 250: ...TS Pointer Save DSPS register can contain a unique interrupt service vector When servicing the interrupt this unique status code allows the Interrupt Service Routine to quickly identify the point at w...

Page 251: ...the next instruction not the one currently executing The relative mode does not apply to Return and Interrupt SCRIPTS Jump Call an Absolute Address Start execution at the new absolute address Jump Cal...

Page 252: ...n local labels can be called using relative transfers If a SCRIPT is written using only relative transfers it does not require any run time alteration of physical addresses and can be stored in and ex...

Page 253: ...the compare occurs When the LSI53C895A is operating in Target mode and this bit is set it tests for an active SCSI SATN signal WVP Wait For Valid Phase 16 If the Wait for Valid Phase bit is set the LS...

Page 254: ...r I O space By setting these bits appropriately data may be moved within memory space within I O space or between the two address spaces The Memory Move instruction is used to copy the specified numbe...

Page 255: ...ust be zero If any of these bits are set an illegal instruction interrupt occurs NF No Flush 24 When this bit is set the LSI53C895A performs a Memory Move without flushing the prefetch unit When this...

Page 256: ...on In this way register values are saved to system memory and later restored and SCRIPTS can make decisions based on data values in system memory The SFBR is not writable using the CPU and therefore n...

Page 257: ...ion of where to Load and Store or the offset from the Data Structure Address DSA depending on the value of bit 28 DSA Relative A maximum of 4 bytes may be moved with these instructions The register ad...

Page 258: ...chip determines the memory address to perform the Load and Store to from by adding the 24 bit signed offset value in the DMA SCRIPTS Pointer Save DSPS to the Data Structure Address DSA R Reserved 27 2...

Page 259: ...s the register to Load and Store to from within the LSI53C895A R Reserved 15 3 BC Byte Count 2 0 This value is the number of bytes to Load and Store 5 8 2 Second Dword Memory I O Address DSA Offset 31...

Page 260: ...5 38 SCSI SCRIPTS Instruction Set...

Page 261: ...teristics Section 6 2 TolerANT Technology Electrical Characteristics Section 6 3 AC Characteristics Section 6 4 PCI and External Memory Interface Timing Diagrams Section 6 5 SCSI Timing Diagrams Secti...

Page 262: ...evice at these or any other conditions beyond those indicated in the Operating Conditions section of the manual is not implied Latch up current 150 mA ESD Electrostatic discharge 2 K V MIL STD 883C Me...

Page 263: ...d state IO Sink current 7 13 mA Asserted state IO Source current 3 5 6 5 mA Negated state IO Sink current 3 5 6 5 mA Negated state IOZ 3 state leakage 20 20 A VPIN 0 V 3 47 V IOZ SRST only 3 state lea...

Page 264: ...l test specified for each mode VIH VS VIL VIH HVD sense voltage 2 4 5 5 V Note 1 VS LVD sense voltage 0 7 1 9 V Note 1 VIL SE sense voltage VSS 0 3 0 5 V Note 1 IIN Input leakage 10 10 A VPIN 0 V 5 25...

Page 265: ...voltage VSS 0 4 V 4 mA dynamic IOZ 3 state leakage 10 10 A VPIN 0 V 5 25 V IPULL Pull down current 7 5 75 A Table 6 8 Bidirectional Signals GPIO0_FETCH GPIO1_MASTER GPIO 2 8 Symbol Parameter Min Max...

Page 266: ...low voltage 0 55 V 16 mA IOZ 3 state leakage 10 10 A VPIN 0 V 5 25 V IPULL Pull down current 7 5 75 A Table 6 10 Input Signals CLK GNT IDSEL RST SCLK TCK TDI TEST_HSC1 TEST_RST TMS TRST 1 TEST_HSC ha...

Page 267: ...TOUT REQ Symbol Parameter Min Max Unit Test Conditions VOH Output high voltage 0 9 VDD V 500 A VOL Output low voltage 0 1 VDD V 1500 A VOH 5 V tolerant output high voltage 2 4 V 16 mA VOL 5 V tolerant...

Page 268: ...H 2 Output high voltage 2 0 VDD V IOH 7 mA VOL Output low voltage VSS 0 5 V IOL 48 mA VIH Input high voltage 2 0 VDD 0 3 V VIL Input low voltage VSS 0 3 0 8 V Referenced to VSS VIK Input clamp voltage...

Page 269: ...filter delay 10 15 ns Figure 6 4 Ultra2 filter delay 5 8 ns Figure 6 4 Extended filter delay 40 60 ns Figure 6 4 1 These values are guaranteed by periodic characterization they are not 100 tested on e...

Page 270: ...of SCSI Receivers Figure 6 6 Input Current as a Function of Input Voltage 1 Receiving Logic Level 0 1 1 1 3 1 5 1 7 Input Voltage Volts 40 20 0 20 40 4 0 4 8 12 16 0 7 V 8 2 V HIGH Z OUTPUT ACTIVE In...

Page 271: ...istics 6 11 Figure 6 7 Output Current as a Function of Output Voltage Output Sink Current milliAmperes 0 200 400 600 800 0 1 2 3 4 5 Output Voltage Volts Output Source Current milliAmperes Output Volt...

Page 272: ...e External Clock timing data Figure 6 8 External Clock Table 6 15 External Clock1 1 Timings are for an external 40 MHz clock A quadrupled 40 MHz clock is required for Ultra1 SCSI operation Symbol Para...

Page 273: ...16 Reset Input Symbol Parameter Min Max Unit t1 Reset pulse width 10 tCLK t2 Reset deasserted setup to CLK HIGH 0 ns t3 MAD setup time to CLK HIGH for configuring the MAD bus only 20 ns t4 MAD hold t...

Page 274: ...e second group applies to Initiator Timing The third group applies to External Memory Timing Note Multiple byte accesses to the external memory bus increase the read or write cycle by 11 clocks for ea...

Page 275: ...a Burst Write 32 Bit Address and Data Burst Write 64 Bit Address and 32 Bit Data External Memory Timing External Memory Read External Memory Write Normal Fast Memory 128 Kbytes Single Byte Access Read...

Page 276: ...ime 0 ns t3 CLK to shared signal output valid 11 ns CLK FRAME AD Driven by Master Addr LSI53C895A Data C_BE Driven by Master PAR Driven by Master Addr LSI53C895A Data IRDY Driven by Master TRDY Driven...

Page 277: ...ime 7 ns t2 Shared signal input hold time 0 ns t3 CLK to shared signal output valid 11 ns CLK Driven by System FRAME Driven by Master AD Driven by Master C_BE Driven by Master PAR Driven by Master IRD...

Page 278: ...Shared signal input hold time 0 ns t3 CLK to shared signal output valid 11 ns CLK Driven by System FRAME Driven by Master AD Driven by Master Addr LSI53C895A Data C_BE Driven by Master PAR Driven by...

Page 279: ...Shared signal input hold time 0 ns t3 CLK to shared signal output valid 11 ns CLK Driven by System FRAME Driven by Master AD 31 0 Driven by Master Addr LSI53C895A Data C_BE 3 0 Driven by Master PAR D...

Page 280: ...nal input setup time 7 ns t2 Shared signal input hold time 0 ns t3 CLK to shared signal output valid 11 ns CLK Driven by System FRAME Driven by Master AD Driven by Master C_BE Driven by Master PAR Dri...

Page 281: ...nput setup time 7 ns t2 Shared signal input hold time 0 ns t3 CLK to shared signal output valid 11 ns Bus Addr Lo Addr Hi Data In In t2 t3 CLK Driven by System FRAME Driven by Master AD Driven by Mast...

Page 282: ...Min Max Unit t1 Shared signal input setup time 7 ns t2 Shared signal input hold time 0 ns t3 CLK to shared signal output valid 2 11 ns t4 Side signal input setup time 10 ns t5 Side signal input hold t...

Page 283: ...n by LSI53C895A PAR Driven by LSI53C895A IRDY Driven by LSI53C895A TRDY Driven by Target STOP Driven by Target DEVSEL Driven by Target Addr Target Data Addr Target Data GNT Driven by Arbiter REQ Drive...

Page 284: ...t2 Shared signal input hold time 0 ns t3 CLK to shared signal output valid 2 11 ns t4 Side signal input setup time 10 ns t5 Side signal input hold time 0 ns t6 CLK to side signal output valid 2 12 ns...

Page 285: ...n by LSI53C895A PAR Driven by LSI53C895A IRDY Driven by LSI53C895A TRDY Driven by Target STOP Driven by Target DEVSEL Driven by Target Addr Target Data Addr Target Data GNT Driven by Arbiter REQ Drive...

Page 286: ...1 Shared signal input setup time 7 ns t2 Shared signal input hold time 0 ns t3 CLK to shared signal output valid 2 11 ns t4 Side signal input setup time 10 ns t5 Side signal input hold time 0 ns t6 CL...

Page 287: ...LSI53C895A PAR Driven by LSI53C895A IRDY Driven by LSI53C895A TRDY Driven by Target STOP Driven by Target DEVSEL Driven by Target Addr Target Data Addr Target Data GNT Driven by Arbiter REQ Driven by...

Page 288: ...1 Shared signal input setup time 7 ns t2 Shared signal input hold time 0 ns t3 CLK to shared signal output valid 2 11 ns t4 Side signal input setup time 10 ns t5 Side signal input hold time 0 ns t6 CL...

Page 289: ...iven by LSI53C895A REQ Driven by LSI53C895A PAR Driven by LSI53C895A IRDY Driven by LSI53C895A TRDY Driven by Target STOP Driven by Target DEVSEL Driven by Target t6 t3 AD 31 0 Driven by LSI53C895A C_...

Page 290: ...l Specifications Table 6 28 Burst Read 32 Bit Address and Data Symbol Parameter Min Max Unit t1 Shared signal input setup time 7 ns t2 Shared signal input hold time 0 ns t3 CLK to shared signal output...

Page 291: ...O1_MASTER Driven by LSI53C895A REQ Driven by LSI53C895A PAR Driven by LSI53C895A IRDY Driven by LSI53C895A TRDY Driven by Target STOP Driven by Target DEVSEL Driven by Target AD Driven by LSI53C895A C...

Page 292: ...le 6 29 Burst Read 64 Bit Address and Data Symbol Parameter Min Max Unit t1 Shared signal input setup time 7 ns t2 Shared signal input hold time 0 ns t3 CLK to shared signal output valid 2 11 ns t10 C...

Page 293: ...ven by LSI53C895A GPIO1_MASTER Driven by LSI53C895A REQ Driven by LSI53C895A PAR Driven by LSI53C895A IRDY Driven by LSI53C895A TRDY Driven by Target STOP Driven by Target DEVSEL Driven by Target AD D...

Page 294: ...e 6 30 Burst Write 32 Bit Address and Data Symbol Parameter Min Max Unit t1 Shared signal input setup time 7 ns t2 Shared signal input hold time 0 ns t3 CLK to shared signal output valid 2 11 ns t10 C...

Page 295: ...en by LSI53C895A GPIO1_MASTER Driven by LSI53C895A REQ Driven by LSI53C895A PAR Driven by LSI53C895A IRDY Driven by LSI53C895A TRDY Driven by Target STOP Driven by Target DEVSEL Driven by Target AD Dr...

Page 296: ...31 Burst Write 64 Bit Address and 32 Bit Data Symbol Parameter Min Max Unit t1 Shared signal input setup time 7 ns t2 Shared signal input hold time 0 ns t3 CLK to shared signal output valid 2 11 ns t...

Page 297: ...GPIO1_MASTER Driven by LSI53C895A REQ Driven by LSI53C895A PAR Driven by LSI53C895A IRDY Driven by LSI53C895A TRDY Driven by Target STOP Driven by Target DEVSEL Driven by Target AD 31 0 Driven by LSI5...

Page 298: ...6 38 Electrical Specifications This page intentionally left blank...

Page 299: ...ax Unit t1 Shared signal input setup time 7 ns t2 Shared signal input hold time 0 ns t3 CLK to shared signal output valid 11 ns t11 Address setup to MAS HIGH 25 ns t12 Address hold from MAS HIGH 15 ns...

Page 300: ...en by LSI53C895A AD Driven by Master Addr C_BE 3 0 Driven by Master FRAME Driven by Master LSI53C895A Data LSI53C895A Data MAD Addr driven by LSI53C895A Data driven by Memory MAS1 Driven by LSI53C895A...

Page 301: ...dr IRDY Driven by Master TRDY Driven by LSI53C895A STOP Driven by LSI53C895A DEVSEL Driven by LSI53C895A AD Driven by Master Addr C_BE 3 0 Driven by Master FRAME Driven by Master LSI53C895A Data LSI53...

Page 302: ...6 42 Electrical Specifications This page intentionally left blank...

Page 303: ...t hold time 0 ns t3 CLK to shared signal output valid 11 ns t11 Address setup to MAS HIGH 25 ns t12 Address hold from MAS HIGH 15 ns t13 MAS pulse width 25 ns t20 Data setup to MWE LOW 30 ns t21 Data...

Page 304: ...iven by Master FRAME Driven by Master 1 2 3 4 5 6 7 8 9 10 Addr In MAD Driven by LSI53C895A High Order Address Middle Order Address Low Order Address MAS1 Driven by LSI53C895A MAS0 Driven by LSI53C895...

Page 305: ...riven by LSI53C895A DEVSEL Driven by LSI53C895A AD 31 0 C_BE 3 0 Driven by Master FRAME Driven by Master 11 12 13 14 15 16 17 18 19 20 MAD Driven by LSI53C895A MAS1 Driven by LSI53C895A MAS0 Driven by...

Page 306: ...o data clocked in 150 ns t15 Address valid to data clocked in 205 ns t16 MOE LOW to data clocked in 100 ns t17 Data hold from address MOE MCE change 0 ns t18 Address out from MOE MCE HIGH 50 ns t19 Da...

Page 307: ...MAS pulse width 25 ns t20 Data setup to MWE LOW 30 ns t21 Data hold from MWE HIGH 20 ns t22 MWE pulse width 100 ns t23 Address setup to MWE LOW 60 ns t24 MCE LOW to MWE HIGH 120 ns t25 MCE LOW to MWE...

Page 308: ...riven by LSI53C895A MWE Driven by LSI53C895A 0 2 4 6 8 10 12 14 16 17 Data driven by Memory CLK Driven by System PAR Driven by LSI53C895A IRDY Driven by Master TRDY Driven by LSI53C895A STOP Driven by...

Page 309: ...by LSI53C895A MOE Driven by LSI53C895A MWE Driven by LSI53C895A 15 18 20 22 24 26 28 30 Data driven by Memory CLK Driven by System PAR Driven by LSI53C895A IRDY Driven by Master TRDY Driven by LSI53C...

Page 310: ...SEL Driven by LSI53C895A AD 31 0 C_BE 3 0 Driven by Master FRAME Driven by Master MAD Driven by LSI53C895A MAS1 Driven by LSI53C895A MAS0 Driven by LSI53C895A MCE Driven by LSI53C895A MOE Driven by LS...

Page 311: ...895A STOP Driven by LSI53C895A DEVSEL Driven by LSI53C895A AD 31 0 C_BE 3 0 Driven by Master FRAME Driven by Master MAD Driven by LSI53C895A MAS1 Driven by LSI53C895A MAS0 Driven by LSI53C895A MCE Dri...

Page 312: ...ns t15 Address valid to data clocked in 205 ns t16 MOE LOW to data clocked in 100 ns t17 Data hold from address MOE MCE change 0 ns t18 Address out from MOE MCE HIGH 50 ns t19 Data setup to CLK HIGH 5...

Page 313: ...t20 Data setup to MWE LOW 30 ns t21 Data hold from MWE HIGH 20 ns t22 MWE pulse width 100 ns t23 Address setup to MWE LOW 60 ns t24 MCE LOW to MWE HIGH 120 ns t25 MCE LOW to MWE LOW 25 ns t26 MWE HIG...

Page 314: ...s t15 Address valid to data clocked in 205 ns t16 MOE LOW to data clocked in 100 ns t17 Data hold from address MOE MCE change 0 ns t18 Address out from MOE MCE HIGH 50 ns t19 Data setup to CLK HIGH 5...

Page 315: ...0 Data setup to MWE LOW 30 ns t21 Data hold from MWE HIGH 20 ns t22 MWE pulse width 100 ns t23 Address setup to MWE LOW 60 ns t24 MCE LOW to MWE HIGH 120 ns t25 MCE LOW to MWE LOW 25 ns t26 MWE HIGH t...

Page 316: ...timing Figure 6 35 Initiator Asynchronous Send Table 6 40 Initiator Asynchronous Send Symbol Parameter Min Max Unit t1 SACK asserted from SREQ asserted 5 ns t2 SACK deasserted from SREQ deasserted 5 n...

Page 317: ...iator Asynchronous Receive Symbol Parameter Min Max Unit t1 SACK asserted from SREQ asserted 5 ns t2 SACK deasserted from SREQ deasserted 5 ns t3 Data setup to SREQ asserted 0 ns t4 Data hold from SAC...

Page 318: ...rget Asynchronous Send Symbol Parameter Min Max Unit t1 SREQ deasserted from SACK asserted 5 ns t2 SREQ asserted from SACK deasserted 5 ns t3 Data setup to SREQ asserted 55 ns t4 Data hold from SACK a...

Page 319: ...E 5 0 Mbytes Symbol Parameter Min Max Unit t1 Send SREQ or SACK assertion pulse width 80 ns t2 Send SREQ or SACK deassertion pulse width 80 ns t1 Receive SREQ or SACK assertion pulse width 70 ns t2 Re...

Page 320: ...etup to SREQ or SACK asserted 0 ns t6 Receive data hold from SREQ or SACK asserted 45 ns Table 6 46 SCSI 2 Fast Transfers 10 0 Mbytes 8 Bit Transfers or 20 0 Mbytes 16 Bit Transfers 40 MHz Clock Symbo...

Page 321: ...margin in differential systems ns t5 Receive data setup to SREQ or SACK asserted 14 ns t6 Receive data hold from SREQ or SACK asserted 24 ns Table 6 48 Ultra SCSI SE Transfers 20 0 Mbytes 8 Bit Transf...

Page 322: ...a SCSI transfers the value of the Extend REQ ACK Filtering bit SCSI Test Two STEST2 bit 1 has no effect Symbol Parameter Min Max Unit t1 Send SREQ or SACK assertion pulse width 15 ns t2 Send SREQ or S...

Page 323: ...Filtering bit SCSI Test Two STEST2 bit 1 has no effect Symbol Parameter Min Max Unit t1 Send SREQ or SACK assertion pulse width 8 ns t2 Send SREQ or SACK deassertion pulse width 8 ns t1 Receive SREQ o...

Page 324: ...nformation for the LSI53C895A 208 pin PQFP Table 6 51 provides the 272 BGA pin list by location and Table 6 52 provides the same pin list alphabetically Table 6 53 provides pinout information for the...

Page 325: ...K3 K4 K9 K10 K11 K12 K17 K18 K19 K20 TCK TEST_ RST N C VDD VSS VSS VSS VSS N C N C MAC _ TESTOUT MAD0 L1 L2 L3 L4 L9 L10 L11 L12 L17 L18 L19 L20 TMS TDO TDI N C VSS VSS VSS VSS VDD N C MAD2 MAD1 M1 M...

Page 326: ...NC D9 NC D10 VDD D11 NC D12 VSS D13 NC D14 VDD D15 SCD D16 VSS D17 SREQ D18 SD8 D19 SD8 D20 SDP1 E1 NC E2 NC E3 NC E4 SIO E17 NC E18 SD9 E19 SD9 E20 SD15 F1 SD15 F2 SDP1 F3 VDD F4 VDD F17 NC F18 SD10...

Page 327: ...No Connect C12 No Connect C13 No Connect C14 No Connect C15 No Connect C16 No Connect C18 No Connect D5 No Connect D7 No Connect D9 No Connect D10 No Connect D12 No Connect D14 No Connect E2 No Connec...

Page 328: ...DDSCSI VSSSCSI SATN VDDSCSI SACK VSSSCSI SD2 SD6 SD6 SDP0 VSSSCSI SACK SMSG VSSSCSI NC NC GPIO7 AD1 VDDPCI GPIO1_MASTER GPIO4 MAD7 MAD6 MAD3 MAD0 MAC _TESTOUT SCLK VDDSCSI SD10 SD10 VSSSCSI SD9 SD8 SD...

Page 329: ...22 IRQ 59 MAC _ TESTOUT 79 MAD0 77 MAD1 76 MAD2 75 MAD3 74 MAD4 72 MAD5 71 MAD6 70 MAD7 69 MAS0 186 MAS1 185 MCE 191 MOE 189 MWE 188 No Connect 4 No Connect 49 No Connect 53 No Connect 62 No Connect 1...

Page 330: ...6 70 Electrical Specifications This page intentionally left blank...

Page 331: ...h the only difference being the center grid is 6 x 6 balls vs the LSI53C895A s 272 BGA which has a center grid of 4 x 4 balls The LSI53C895A 272 BGA can be dropped onto a board that has been laid out...

Page 332: ...SACK2 and SACK2 are data handshake lines from the initiator device They are duplicates of SACK and SACK enabled by pulling MAD5 HIGH at reset TEST_RST I 178 K2 Previously TESTIN TEST_RST is used for...

Page 333: ...rds based on IPC assumptions TEST_HSC I 82 J19 Previously TEST TEST_HSC is used for LSI Logic test purposes only This signal can cause a full chip reset VDD_RBIAS RBIAS I 129 130 A11 A10 Previously RB...

Page 334: ...or the 272 PBGA for the LSI53C895A Figure 6 42 LSI53C895A 208 PQFP Mechanical Drawing Sheet 1 of 2 Important This drawing may not be the latest version For board layout and manufacturing obtain the mo...

Page 335: ...ical Drawing Sheet 2 of 2 Important This drawing may not be the latest version For board layout and manufacturing obtain the most recent engineering drawings from your LSI Logic marketing representati...

Page 336: ...2 PBGA Mechanical Drawing Important This drawing may not be the latest version For board layout and manufacturing obtain the most recent engineering drawings from your LSI Logic marketing representati...

Page 337: ...ess Register Zero I O 0x10 0x13 Read Write 4 9 Bridge Support Extensions PMCSR_BSE 0x46 Read Only 4 18 Cache Line Size 0x0C Read Write 4 7 Capabilities Pointer 0x34 Read Only 4 13 Capability ID 0x40 R...

Page 338: ...y 4 11 Subsystem ID Access 0x48 0x4B Write Only 4 18 Subsystem Vendor ID 0x2C 0x2D Read Only 4 10 Vendor ID 0x00 0x01 Read Only 4 3 Table A 1 LSI53C895A PCI Register Map Cont Register Name Address Rea...

Page 339: ...te 4 107 DMA SCRIPTS Pointer DSP 0x2C 0x2F Read Write 4 65 DMA SCRIPTS Pointer Save DSPS 0x30 0x33 Read Write 4 66 DMA Status DSTAT 0x0C Read Only 4 40 DSA Relative Selector DRS 0xAC 0xAF Read Write 4...

Page 340: ...4 113 Response ID One RESPID1 0x4B Read Write 4 88 Response ID Zero RESPID0 0x4A Read Write 4 88 Scratch Byte Register SBR 0x3A Read Write 4 71 Scratch Register A SCRATCHA 0x34 0x37 Read Write 4 67 Sc...

Page 341: ...77 SCSI Longitudinal Parity SLPAR 0x44 Read Write 4 81 SCSI Output Control Latch SOCL 0x09 Read Write 4 38 SCSI Output Data Latch SODL 0x54 0x55 Read Write 4 97 SCSI Selector ID SSID 0x0A Read Only 4...

Page 342: ...Read Write 4 32 SCSI Wide Residue SWIDE 0x45 Read Write 4 82 Static Block Move Selector SBMS 0xB0 0xB3 Read Write 4 106 Temporary TEMP 0x1C 0x1F Read Write 4 58 Updated Address UA 0xCC 0xCF Read Writ...

Page 343: ...memory interface diagrams Figure B 1 16 Kbyte Interface with 200 ns Memory LSI53C895A 27C128 MOE OE MCE CE D0 8 MAD 7 0 Bus CK Q0 8 A 7 0 QE 6 A 13 8 VDD MAS0 MAS1 Note MAD 3 1 pulled LOW internally M...

Page 344: ...0 8 MAD 7 0 Bus CK Q0 8 A 7 0 QE 6 A 15 8 VDD MAS0 MAS1 Note MAD 3 1 0 pulled LOW internally MAD bus sense logic enabled for 64 Kbyte of fast memory 150 ns devices 33 MHz HCT374 GPIO4 MWE VPP Control...

Page 345: ...S0 MAS1 Note MAD 2 0 pulled LOW internally MAD bus sense logic enabled for 128 256 512 Kbytes or 1 Mbyte of fast memory 150 ns devices 33 MHz The HCT374s may be replaced with HCT377s GPIO4 MWE VPP Con...

Page 346: ...2 Kbytes of slow memory 150 ns devices additional time required for HCT139 33 MHz The HCT374s may be replaced with HCT377s HCT374 GPIO4 MWE VPP Control 12 V VPP Optional for Flash Memory only not requ...

Page 347: ...4 7 CLSE 4 71 CM 4 55 CMP 4 75 4 78 COM 4 73 CON 4 25 4 50 CP 4 13 CSBC 4 112 CSF 4 95 CTEST0 4 54 CTEST1 4 54 CTEST2 4 55 CTEST3 4 57 CTEST4 4 60 CTEST5 4 62 CTEST6 4 63 D1S 4 16 D2S 4 16 DACK 4 56...

Page 348: ...L 4 83 MAN 4 69 MASR 4 62 MBOX0 4 53 MBOX1 4 53 MDPE 4 41 4 70 ME 4 84 MEMORY 4 9 MG 4 14 ML 4 15 MMRS 4 104 MMWS 4 105 MO 4 0 4 34 MPEE 4 60 MSG 4 38 4 40 4 46 NC 4 6 NIP 4 15 OLF 4 43 OLF1 4 47 ORF...

Page 349: ...29 WSS 4 28 ZMODE 4 100 ZSD 4 60 Numerics 16 bit system S16 4 94 32 64 bit jump 5 30 32 bit addressing 5 7 3 state 3 3 64 bit addressing in SCRIPTS 2 21 SCRIPT selectors 4 104 table indirect indexing...

Page 350: ...48 4 57 clear instruction 5 15 5 17 clear SCSI FIFO CSF 4 95 CLF 2 48 CLK 3 4 clock 3 4 address incrementor ADCK 4 62 byte counter BBCK 4 62 conversion factor CCF 2 0 4 30 quadrupler 2 22 CLSE 2 6 2...

Page 351: ...30 enabling cache mode 2 10 encoded chip SCSI ID ENC 4 31 destination SCSI ID ENC 4 36 ENID 4 39 SCSI destination ID 5 20 entry storage address ESA 4 111 error reporting signals 3 8 even parity 2 26...

Page 352: ...6 internal SCRIPTS RAM 2 20 internal RAM see also SCRIPTS RAM 2 20 interrupt acknowledge command 2 4 handling 2 43 instruction 5 28 line IL 4 13 on the fly 5 30 on the fly INTF 4 50 output 6 14 pin IP...

Page 353: ...N_GNT MG 4 14 MOE 3 14 move to from SFBR cycles 5 24 multiple cache line transfers 2 8 MWE 3 14 N new capabilities NC 4 6 new features in the LSI53C895A 1 3 Next_Item_Ptr NIP 4 15 no connections 3 18...

Page 354: ...TNM 3 13 SBSY status BSY 4 40 SC_D 3 13 SC_D status C_D 4 40 SCLK 3 11 SCLK 4 90 quadrupler enable QEN 4 91 quadrupler select QSEL 4 91 SCNTL0 2 27 SCNTL1 2 26 2 27 SCNTL3 2 41 2 42 scratch byte regis...

Page 355: ...lock 6 61 SCTRL signals 3 13 SD 15 0 3 12 SDP 1 0 3 12 second dword 5 12 5 21 5 23 5 32 5 34 5 37 SEL 2 45 select 2 19 instruction 5 16 with ATN 5 19 with SATN on a start sequence WATN 4 23 selected S...

Page 356: ...24 count 5 33 counter 5 12 information 2 19 rate synchronous 2 40 TRDY 2 9 3 6 TRST 3 16 U Ultra SCSI clock conversion factor bits 4 31 enable USE 4 29 high voltage differential transfers 20 0 mbytes...

Page 357: ...comments and fax it to us at the number shown If appropriate please also fax copies of any marked up pages from this document Important Please include your name phone number fax number and company add...

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Page 363: ...Singapore Singapore LSI Logic Pte Ltd 7 Temasek Boulevard 28 02 Suntec Tower One Singapore 038987 Tel 65 334 9061 Fax 65 334 4749 Sweden Stockholm LSI Logic AB Finlandsgatan 14 164 74 Kista Tel 46 8...

Page 364: ...ei Time24 Bldg 35 Tansu cho Shinjuku ku Tokyo 162 0833 Tel 81 3 3260 1411 Fax 81 3 3260 7100 Technical Center Tel 81 471 43 8200 Marubeni Solutions 1 26 20 Higashi Shibuya ku Tokyo 150 0001 Tel 81 3 5...

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