LSI LSI53C895A, Technical Manual

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SCSI Registers 4-21
Register: 0x00
SCSI Control Zero (SCNTL0)
Read/Write
ARB[1:0] Arbitration Mode Bits 1 and 0 [7:6]
Simple Arbitration
1. The LSI53C895A waits for a bus free condition to
occur.
2. It asserts SBSY/ and its SCSI ID (contained in the
SCSI Chip ID (SCID) register) onto the SCSI bus. If
the SSEL/ signal is asserted by another SCSI device,
the LSI53C895A deasserts SBSY/, deasserts its ID
and sets the Lost Arbitration bit (bit 3) in the
SCSI
Status Zero (SSTAT0) register.
3. After an arbitration delay, the CPU should read the
SCSI Bus Data Lines (SBDL) register to check if a
higher priority SCSI ID is present. If no higher priority
ID bit is set, and the Lost Arbitration bit is not set, the
LSI53C895A wins arbitration.
4. Once the LSI53C895A wins arbitration, SSEL/ must be
asserted using the SCSI Output Control Latch (SOCL)
for a bus clear plus a bus settle delay (1.2
µ
s) before
a low level selection is performed.
7 6 5 4 3 2 1 0
ARB[1:0] START WATN EPC R AAP TRG
1 1 0 0 0 x 0 0
ARB1 ARB0 Arbitration Mode
0 0 Simple arbitration
0 1 Reserved
1 0 Reserved
1 1 Full arbitration, selection/reselection