LSI LSI53C895A, Technical Manual

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2-18 Functional Description
Write Example 3 –
Burst = 16 Dwords, Cache Line Size = 8 Dwords:
2.1.3.6 Memory-to-Memory Moves
Memory-to-Memory Moves also support PCI cache commands, as
described above, with one limitation. Memory Write and Invalidate on
Memory-to-Memory Move writes are only supported if the source and
destination address are quad word aligned. If the source and destination
are not quad word aligned (that is, Source address [2:0] == Destination
Address [2:0]), write aligning is not performed and Memory Write and
Invalidate commands are not issued. The LSI53C895A is little endian
only.
2.2 SCSI Functional Description
The LSI53C895A provides an Ultra2 SCSI controller that supports an
8-bit or 16-bit bus. The controller supports Wide Ultra2 SCSI
synchronous transfer rates up to 80 Mbytes/s on a LVD SCSI bus. The
SCSI core can be programmed with SCSI SCRIPTS, making it easy to
“fine tune” the system for specific mass storage devices or Ultra2 SCSI
requirements.
A to B: MW (6 bytes)
A to C: MW (13 bytes)
A to D: MW (17 bytes)
C to D: MW (5 bytes)
C to E: MW (21 bytes)
D to F: MW (32 bytes)
A to H: MW (15 bytes)
MWI (64 bytes)
MW (2 bytes)
A to G: MW (15 bytes)
MWI (32 bytes)
MW (18 bytes)