LSI LSI53C895A, Technical Manual

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4-56 Registers
When it is set, the SCRATCHA register contains bits
[31:0] of the Memory Base Address value from the PCI
Base Address Register One (MEMORY) . This is the
memory mapped operating register base address. Bits
[9:0] will be 0. The SCRATCHB register contains bits
[31:13] of the RAM Base Address value from the PCI
Base Address Register Two (SCRIPTS RAM) . This is the
base address for the internal 8 Kbytes RAM. Bits [12:0]
will be 0. Bits [23:16] of
SCRIPTS Fetch Selector (SFS)
contain the PCI Revision ID (Rev ID) register value and
bits [15:0] contain the PCI Device ID register value. When
this bit is set, writes to this register have no effect.
When this bit is cleared, the Scratch Register A
(SCRATCHA) , Scratch Register B (SCRATCHB) , and
SCRIPTS Fetch Selector (SFS) registers return to normal
operation.
Note: Bit 3 is the only writable bit in this register. All other bits are
read only. When modifying this register, all other bits must
be written to zero. Do not execute a read-modify-write to
this register.
TEOP SCSI True End of Process 2
This bit indicates the status of the LSI53C895A’s TEOP
signal. The TEOP signal acknowledges the completion of
a transfer through the SCSI portion of the LSI53C895A.
When this bit is set, TEOP is active. When this bit is
clear, TEOP is inactive.
DREQ Data Request Status 1
This bit indicates the status of the LSI53C895A’s internal
Data Request signal (DREQ). When this bit is set, DREQ
is active. When this bit is clear, DREQ is inactive.
DACK Data Acknowledge Status 0
This bit indicates the status of the LSI53C895A’s internal
Data Acknowledge signal (DACK/). When this bit is set,
DACK/ is inactive. When this bit is clear, DACK/ is active.