LSI LSI53C895A, Technical Manual

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64-Bit SCRIPTS Selectors 4-105
Writes to the MMRS register are unaffected. Clearing the
PCI Configuration Into Enable bit causes the MMRS
register to return to normal operation.
Registers: 0xA4–0xA7
Memory Move Write Selector (MMWS)
Read/Write
MMWS Memory Move Write Selector [31:0]
Supplies the upper Dword of a 64-bit address during data
write operations during Memory-to-Memory Moves and
absolute address STORE operations.
A special mode of this register can be enabled by setting
the PCI Configuration Into Enable bit in the
Chip Test Two
(CTEST2) register. Because the LSI53C895A supports
only a 32-bit SCRIPTS RAM PCI base address, the
MMWS register is always read as 0x00000000 when in
the special mode.
Writes to the MMWS register are unaffected. Clearing the
PCI Configuration Enable bit causes the MMWS register
to return to normal operation.
Registers: 0xA8–0xAB
SCRIPTS Fetch Selector (SFS)
Read/Write
SFS SCRIPTS Fetch Selector [31:0]
Supplies the upper Dword of a 64-bit address during
SCRIPTS fetches and Indirect fetches (excluding Table
Indirect fetches). This register can be loaded
automatically using a 64-bit jump instruction.
A special mode of this register can be enabled by setting
the PCI Configuration Into Enable bit in the
Chip Test Two
(CTEST2) register. If this bit is set, bits [23:16] of the SFS
31 0
MMWS
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
31 0
SFS
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0