LSI LSI53C895A, Technical Manual

Page: 283 / 364

PCI and External Memory Interface Timing Diagrams 6-23
Figure 6.17 Nonburst Opcode Fetch, 32-Bit Address and Data
CLK
(Driven by System)
FRAME/
(Driven by LSI53C895A)
AD
(Driven by LSI53C895A-
C_BE/
(Driven by LSI53C895A)
PAR
(Driven by LSI53C895A-
IRDY/
(Driven by LSI53C895A)
TRDY/
(Driven by Target)
STOP/
(Driven by Target)
DEVSEL/
(Driven by Target)
Addr/ Target-Data)
Addr; Target-Data)
GNT/
(Driven by Arbiter)
REQ/
(Driven by LSI53C895A)
GPIO1_MASTER/
(Driven by LSI53C895A)
GPIO0_FETCH/
(Driven by LSI53C895A)
Addr
Out
Addr
Out
CMD BE BE CMD
t
1
t
2
t
3
Data
In
t
10
t
8
t
7
t
9
t
4
t
6
t
5
t
1
t
1
t
1
t
2
t
2
t
2
t
3
t
3
t
3
t
3
t
3
Data
In