LSI LSI53C895A, Technical Manual

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SCSI Registers 4-51
•
A phase mismatch (initiator mode) or SATN/ becomes
active (target mode)
•
An arbitration sequence completes
•
A selection or reselection time-out occurs
•
The LSI53C895A is selected
•
The LSI53C895A is reselected
•
A SCSI gross error occurs
•
An unexpected disconnect occurs
•
A SCSI reset occurs
•
A parity error is detected
•
The handshake-to-handshake timer is expired
•
The general purpose timer is expired
•
A SCSI bus mode change is detected
To determine exactly which condition(s) caused the
interrupt, read the
SCSI Interrupt Status Zero (SIST0)
and SCSI Interrupt Status One (SIST1) registers.
DIP DMA Interrupt Pending 0
This status bit is set when an interrupt condition is
detected in the DMA portion of the LSI53C895A. The
following conditions cause a DMA interrupt to occur:
•
A PCI parity error is detected
•
A bus fault is detected
•
An abort condition is detected
•
A SCRIPTS instruction is executed in single step
mode
•
A SCRIPTS interrupt instruction is executed
•
An illegal instruction is detected
To determine exactly which condition(s) caused the
interrupt, read the
DMA Status (DSTAT) register.