LTC3115-1
24
Rev. C
For more information
APPLICATIONS INFORMATION
Compensation of the Voltage Loop
The small-signal models of the LTC3115-1 reveal that the
transfer function from the error amplifier output, VC, to
the output voltage is characterized by a set of resonant
poles and a possible zero generated by the ESR of the
output capacitor as shown in the Bode plot of Figure 7.
In boost mode operation, there is an additional right half
plane zero that produces phase lag and increasing gain at
higher frequencies. Typically, the compensation network
is designed to ensure that the loop crossover frequency is
low enough that the phase loss from the right half plane
zero is minimized. The low frequency gain in buck mode
is a constant, but varies with both V
IN
and V
OUT
in boost
mode.
In most applications, the low bandwidth of the Type I
compensated loop will not provide sufficient transient
response performance. To obtain a wider bandwidth feed-
back loop, optimize the transient response, and minimize
the size of the output capacitor, a Type III compensation
network as shown in Figure 9 is required.
GAIN
PHASE
BOOST MODE
BUCK MODE
–20dB/DEC
–40dB/DEC
f
O
f
31151 F07
f
RHPZ
0°
–90°
–180°
–270°
Figure 7. Buck-Boost Converter Bode Plot
Figure 8. Error Amplifier with Type I Compensation
Figure 9. Error Amplifier with Type III Compensation
For charging or other applications that do not require an
optimized output voltage transient response, a simple
Type I compensation network as shown in Figure 8 can
be used to stabilize the voltage loop. To ensure sufficient
phase margin, the gain of the error amplifier must be
low enough that the resultant crossover frequency of the
control loop is well below the resonant frequency.
+
–
C1
GND
LTC3115-1
VC
31151 F08
FB
V
OUT
R
BOT
R
TOP
1000mV
C
FB
R
FB
GND
LTC3115-1
VC
31151 F09
FB
V
OUT
R
BOT
R
TOP
R
FF
C
FF
1000mV
C
POLE
+
–
A Bode plot of the typical Type III compensation network
is shown in Figure 10. The Type III compensation network
provides a pole near the origin which produces a very high
loop gain at DC to minimize any steady-state error in the
regulation voltage. Two zeros located at f
ZERO1
and f
ZERO2
provide sufficient phase boost to allow the loop crossover
frequency to be set above the resonant frequency, f
O
, of
the power stage. The Type III compensation network also
introduces a second and third pole. The second pole, at
frequency f
POLE2
, reduces the error amplifier gain to a
zero slope to prevent the loop crossover from extending
too high in frequency. The third pole at frequency f
POLE3
provides attenuation of high frequency switching noise.
