Lattice Semiconductor
Multi-Channel DMA Controller User’s Guide
9
Memory-to-Memory Write
transfer state four - S24
This is the eighth and final stage of the memory-to-memory transfer. The state
machine de-asserts the
memw_n
signal. In the 8237 mode, Channel 1’s current
word register is decremented. In the non-8237 mode, the word count register of the
channel being serviced is decremented. If the counter rolls over from 0xFFFF to
0x0000, the
eopout_n
signal is asserted and the state machine transitions to state
SI. Otherwise, the state machine transitions to state S11 and starts a new memory-
to-memory transfer.
Input Signals:
eopin_n
Asserted Output Signals:
eopout_n
(in case the counter rolls over)
Possible State Transitions:
SI, S11
Active DMA State One - S1
This is the first state of DMA transfer. The aen signal is asserted in this state while a
valid address is placed on the address bus. If dreq continues to be asserted, the
state machine transitions to state S2. If
dreq
is de-asserted, the state machine
transitions to state SI. DMA requests must be held active until the dack signal is
asserted.
Input Signals:
dreq
Asserted Output Signals:
aen
,
address
Possible State Transitions:
S2, SI
Active DMA state two - S2
This is the second state of the DMA transfer. The
dack
signal is asserted. The
dreq
signal does not need to be held asserted after this state if block or single
transfer mode is selected.
memr_n
or
iorout_n
is asserted depending on the
direction of the transfer.
8237 Mode:
memw_n
or
iowout_n
is asserted if the extended write option is
selected in the command register. The state machine will skip state S3 and transi-
tion to state S4 if the compressed timing option is selected. This will result both read
and write pulses being asserted for just a single cycle.
Non-8237 Mode:
memw_n
or
iowout_n
is asserted, and the state machine transi-
tions to state S3. While in state S2, S3, or S4, the state machine will terminate a
block or demand transfer if the
eopin_n
signal is sampled asserted.
Input Signals:
eopin_n
,
dreq
Asserted Output Signals:
dack
,
memw_n
,
memr_n
,
iorout_n
,
iowout_n
Possible State Transitions:
S3, S4
Active DMA state three - S3 This is the third state of the DMA transfer. In the 8237 mode, the
memw_n
or
iowout_n
signal is asserted if extended write is not selected. The state machine is
sensitive to the
eopin_n
and
dreq
signals for demand transfers. The state
machine transitions to state S4, when ready signal is sampled de-asserted. The
machine stays in state S3 as long as ready is sampled asserted.
Input Signals:
eopin_n
,
dreq
,
ready
Asserted Output Signals:
memw_n
,
iowout_n
Possible State Transitions:
S3, S4
Table 2. State Descriptions (Continued)
State
Description