Lattice Semiconductor ispLever Core Multi-Channel DMA Controller, User Manual, Page: 21 / 29

Lattice Semiconductor Multi-Channel DMA Controller User’s Guide
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Command Register
This register controls the operation of the core. This register is 4 bits wide in the non-8237 mode. A reset or master
clear clears the register. Table 13 lists the functions of this register for the non-8237 mode.
Mode Register (Non- 8237 Mode)
Each channel has an 8-bit mode register. Table 14 lists the format of the mode register in the non-8237 mode. Pro-
gramming the corresponding increment and decrement bits to the same value can hold the source or destination
address constant.
Channel Control Register
This register is visible in the non-8237 mode. Each channel has one channel control register. Table 15 lists the reg-
ister’s format. A reset or a master clear resets the request and sets the mask. This masks the channel’s hardware
requests. Auto-initialization is disabled upon a reset.
Table 13. Command Register – Non-8237 Mode
Table 14. Mode Register – Non-8237 Mode
Bit Description
0 0 Controller enable
1 Controller disable
1 Reserved. This bit is always 0
2 Reserved. This bit is always 0
3 0
dack
active low
1
dack
active high
Bit Description
0 0 Memory-to-memory disable
1 Memory-to-memory enable
1 0 Write transfer
1 Read transfer
X If bit0=1
2 0 Increment Source Address disable
1 Increment Source Address enable
3 0 Decrement Source Address disable
1 Decrement Source Address enable
4 0 Increment Destination Address disable
1 Increment Destination Address enable
5 0 Decrement Destination Address disable
1 Decrement Destination Address enable
7:6 00 Demand mode select
01 Single mode select
10 Block mode select
11 Illegal
Note: Bits 2 and 3 are mutually exclusive. They cannot be enabled
at the same time since the address will either increment or decre-
ment. This also applies to Bits 4 and 5.