Lattice Semiconductor
Multi-Channel DMA Controller User’s Guide
4
Block Diagram
Figure 1 shows the block diagram of this core.
Figure 1. Block Diagram of MCDMA Core
Functional Description
The MCDMA contains three basic blocks of control logic: CPU Interface (Data and Control Blocks), the DMA State
Machine, and the Priority Request Encoder
CPU Interface Control
This explanation applies mainly to the non-8237 mode because most of the programmability lies in this mode. How-
ever, the concepts are also applicable to the 8237 mode.
The CPU Interface Control block first decodes the
ain
bus. It then generates the enable signals to the selected
registers or to a subset of the selected registers when byte enables are present during the write cycle. When the
registers are read, it provides a select signal to the multiplexer that routes the appropriate register contents onto
the data bus.
CPU Interface Data
The CPU Interface Data block contains all the configuration registers. It includes all the routing logic required to
transfer either the selected register’s contents (during the register read cycle) or the temporary register contents
(during the memory write cycle of a memory-to-memory transfer).
DMA Finite State Machine
The DMA FSM (Finite State Machine) module initiates data transfers and generates control signals for various
transfer modes. It also generates the address and address-enable signals (
aen
). The FSM exchanges signals with
the CPU interface block and priority encoder block. The state machine in the 8237 mode is similar to the non-8237
mode except a few additional FSM branches in 8237 mode that incorporate:
CPU Interface
and
DMA State
Machine
hlda
ready
iowin_n
iorin_n
clk
reset
eopin_n
cs_n
hreq
aen
iorout_n
iowout_n
memr_n
memw_n
eopout_n
aout[ADDR_BUS_WIDTH-1:0]
dbout[DATA_BUS_WIDTH-1:0]
dack[N-1:0]
ain[AIN_BUS_WIDTH-1:0]
dreq[N-1:0]
N = Number of channels
dbin[DATA_BUS_WIDTH-1:0]
Priority
Request
Encoder
Register
Block