Lattice Semiconductor
Multi-Channel DMA Controller User’s Guide
18
Mode Register
Each channel has a 6-bit wide register. During a write operation by the microprocessor when MCDMA is in idle
state, the least two significant bits (bit 0 and 1) of the data bus determine which channel mode register is being
accessed. A reset or a master clear clears the mode registers. Table 7 lists the format of a mode register in the
8237 mode.
Mask Register
This register is only visible in the 8237 mode. Each channel has a bit associated with it that is used to mask a hard-
ware DMA request (disable the incoming
dreq
). All four bits of this register can be accessed at once, or the CPU
can program each of the bits separately. Each mask bit is set when its associated channel produces an
eopout_n
signal. A reset or master clear sets all four bits and masks all the channels. Table 8 and Table 9 list the mask regis-
ter format for the 8237 mode.
Request Register
This register is only visible in 8237 mode. The request register allows software DMA requests. The values in the
mask register mask the hardware request (
dreq
). Software requests generated from the request register are non-
maskable. Individual bits of this register can be accessed with the channel number supplied on the two least signif-
icant bits of the data bus. A reset or master clear clears this register. The channel must be in block mode in order to
make a software request. Table 10 lists the request register format in 8237 Mode.
Status Register
This register is only available in the 8237 mode. The microprocessor can read the status register, which contains
information about the status of the device. This information includes which of the channels have completed their
DMA service and which channels have a DMA request pending. The Status Register is reset upon a hardware
reset or a master clear. Bits 0 through 3, which indicate which channel has reached Terminal Count, are cleared
every time the Status register is read. Bits 4 through 7 are set when their corresponding channel is requesting ser-
vice. Table 11 shows the status register format.
Temporary Register
This register holds data during memory-to-memory transfers. A reset or master clear command clears this register.
The microprocessor can read this register in the 8237 mode while the MCDMA is in the idle state. This register
yields the last data transferred during the most recent memory-to-memory transfer.
Table 6. Command Register - 8237 Mode
Bit
Description
0
Memory-to-memory disable
Memory-to-memory enable
1
Channel 0 address hold disable
Channel 0 address hold enable
X
if bit0 = 0
2
Controller enable
Controller disable
3
Normal timing
Compressed timing
X
if bit0 = 1
4
Fixed Priority
Rotating Priority
5
Late Write
Extended Write
X
if bit3 = 1
6
dreq
active high
dreg
active low
7
dack
active low
dack
active high