Lattice Semiconductor
Multi-Channel DMA Controller User’s Guide
20
Table 11. Status Register: Access One Bit – 8237 Mode
Table 12. Non-8237 Internal Registers
Source Address Register
This register is only available in the non-8237 mode. Each channel has a Source Address Register whose width
matches with the address bus width. This register stores the value of the source or memory address used during
DMA transfers. The address is automatically incremented or decremented by 1, 2, or 4 after each transfer, depend-
ing on the respective data bus width of 8, 16 or 32 bits. This register has to be written in consecutive cycles after
clearing the byte pointer. The number of cycles taken to access this register depends on the size of the address
bus. During a DMA transfer between an I/O location and memory, this register holds the address of the memory
location. During a memory-to-memory transfer, this register stores the address of the location that is read from.
The user must always program the register with the address that is aligned with the width of the data bus.
Destination Address Register
This register is only available in the non-8237 mode. Each channel has a Destination Address Register whose
width matches with the address bus width. The address is automatically incremented or decremented by 1, 2, or 4
after each transfer depending on the respective data bus width of 8, 16 or 32 bits. This register has to be written in
consecutive cycles after clearing the byte pointer. The number of cycles taken to access this register depends on
the size of the address bus. During memory-to-memory transfers, this register stores the address of the memory
location that is written into. This register is not used during DMA transfers between memory and I/O. The user must
always program the register with the address that is aligned with the width of the data bus.
Word Count Register
This register is only available in non-8237 mode, and its width is configurable. This register determines the number
of transfers to be performed. The actual number of transfers is one more than the value programmed into this reg-
ister. The current word count is decremented after each transfer. When the value in the register goes from zero to
0xFFFF, a Terminal Count (
eopout_n
) signal is generated. At the end of a DMA transfer, this register has a value
of 0xFFFF if auto-initialization is not enabled for the channel.
Bit
Description
0
Channel 0 terminal count
1
Channel 1 terminal count
2
Channel 2 terminal count
3
Channel 3 terminal count
4
Channel 0 request
5
Channel 1 request
6
Channel 2 request
7
Channel 3 request
Name
Size in Bits
Number of Registers
Source Address Register
16, 24 or 32
1
N
4
Word Count Register
8, 16, 24 or 32
2
N
Destination Address Register
16, 24 or 32
1
N
Command Register
4
1
Temporary Register
8,16,32 or 64
3
1
Mode Register
8
N
Channel Control Register
3
N
1. Based on the width of the address bus selected
2. Based on the width of the word count register selected
3. Based on the width of the data bus selected
4. N = Number of channels selected