
Lattice Semiconductor
Multi-Channel DMA Controller User’s Guide
19
Table 7. Mode Register - 8237 Mode
Table 8. Mask Register: Access All Bits - 8237 Mode
Table 9. Mask Register: Access One Bit - 8237 Mode
Table 10. Request Register: Access One Bit - 8237 Mode
Bit
Description
1:0
00 Channel 0 select
01 Channel 1 select
10 Channel 2 select
11 Channel 3 select
3:2
00 Verify transfer
01 Write transfer
10 Read transfer
11 Illegal
xx
If bits 6 & 7 are 11
4
0
Auto-initialization disable
1
Auto-initialization enable
5
0
Address increment
1
Address decrement
7:6
10 Demand mode select
01 Single mode select
10 Block mode select
11 Cascade mode (unsupported)
Bit
Description
0
0
Channel 0 unmasked
1
Channel 0 masked
1
0
Channel 1 unmasked
1
Channel 1 masked
2
0
Channel 2 unmasked
1
Channel 2 masked
3
0
Channel 3 unmasked
1
Channel 3 masked
Bit
Description
1:0
00 Select channel 0 mask bit
01 Select channel 1 mask bit
10 Select channel 2 mask bit
11 Select channel 3 mask bit
2
0
Clear mask bit
1
Set mask bit
7:3
Don’t care
Bit
Description
1:0
00 Select channel 0 request bit
01 Select channel 1 request bit
10 Select channel 2 request bit
11 Select channel 3 request bit
2
0
Clear request bit
1
Set request bit
7:3
Don’t care