Lattice Semiconductor
Multi-Channel DMA Controller User’s Guide
5
• Illegal I/O to memory transfer mode bits
• Compressed timing mode
FSM Operation
When a software or hardware request is received and is found to be valid (having passed the polarity, mask and
mode checks), the DMA FSM in SI (Idle) state transmits a request signal,
hreq
to the CPU and transitions to S0
and waits for the
hlda
signal. If the request drops (
dreq
is de-asserted) or the mode register of the request in
hand is in cascade mode (unsupported), the FSM returns to SI (idle). Otherwise, the FSM remains in S0. Once the
request is acknowledged by the assertion of
hlda
signal, the FSM transitions to S1/S11 (S1 and S11 are synony-
mous).
The FSM also determines the transfer type based on the Command and Mode register that is received from the
CPU interface. If memory-to-memory transfer is enabled, the FSM transitions through states S12, S13, S14, S21,
S22, S23 and S24.
If the next transfer should continue for the same request, the path from S11 to S24 is repeated. If memory-to-I/O or
I/O-to-memory is enabled, the FSM goes through states S2, S3 (eliminated in 8237’s compressed timing mode),
and S4. If the transfer continues, the state machine repeats the loop from S2 through S4. This goes on until the
Word Count register gets an overflow or a termination from an external input occurs. External inputs that can termi-
nate a transfer includes an
eopin_n
or
hlda
drop or a request drop during demand transfer. (Note: In case of a
non-demand transfer, the request can be dropped after
dack
is received.). The
eopout_n
signal is generated on
the falling clock edge of S4 or S24 by the end of the transfer. All transfer read/write signals are generated on the
falling edge of clock.
In the state machine described in Figure 2, “input signals” refer to the signals that the state machine samples.
These signals affect the state machine’s transition logic. “Output signals” refer to signals that will be asserted or de-
asserted (transition) while in that state.