Lattice Semiconductor
Multi-Channel DMA Controller User’s Guide
7
Table 2. State Descriptions
State
Description
Idle State - SI
Upon reset, the state machine enters the idle state, SI. The CPU can program the
core’s internal registers while it is in this state. The device stays in this state until an
unmasked DMA request is detected; at which point the state machine asserts the
hreq signal then transitions to state S0. While in state SI, all the outputs of the state
machine are in their inactive states.
Input Signals:
hardware reset, software reset (only for 8237 mode), unmasked
dreq
signal
Asserted Output Signals:
hreq
Possible State Transitions:
SI, S0
Acquire Bus State - S0
The device stays in this state until the
hlda
signal from the CPU is sampled
asserted. The internal registers can still be programmed while in this state. Once
the state machine samples and asserts the
hlda
signal, it transitions to the state
S1 for regular I/O-to-memory or memory-to-I/O DMA transfers. For memory-to-
memory transfers, the state machine transitions to state S11. The criteria for detect-
ing a memory-to-memory transfer are different in the 8237 and non-8237 modes.
8237 Mode:
In this mode, a memory-to-memory transfer is detected if the memory-
transfer enable bit in the Command register is set and the
dreq[0]
signal is
asserted. The
dackout
signal generated by the priority encoder is used to check if
Channel 0 has the highest priority at that time. The DMA priority scheme will be
described more in the priority request encoder section.
Non-8237 Mode:
In this mode, memory-to-memory transfer is detected if bit zero of
the current channel’s mode register is set.
If the current channel’s
dreq
signal is de-asserted in this state and no other
requests are pending, the state machine transitions to state SI. If other requests are
pending or the
dreq
signal remains asserted, the state transitions to either S1 or
S11.
Input Signals:
hlda
,
command[0]
or
mode[0]
,
dackout
Asserted Output Signals:
hreq
Possible State Transitions:
SI, S1, S11
Memory-to-Memory Read
Transfer State One - S11
This is the first state of the memory-to-memory transfer. The absence of the
dack
signal characterizes this transfer. The aen signal is asserted. In the 8237 mode, the
address from Channel 0 of the current address register is placed on the address
bus. In the non-8237 mode, the contents of the source address register are placed
on the address bus. The
memr_n
and
memw_n
signals are de-asserted. During each
of the eight states of the memory-to-memory transfer, the state machine responds
to external
eopin_n
signal and stops the DMA transfer service as soon as the cur-
rent cycle is completed. The state machine transitions to state S12.
Input Signals:
eopin_n
Asserted Output Signals:
aen
,
address
Possible State Transitions:
S12
Memory-to-Memory Read
Transfer State Two - S12
This is the second state of memory-to-memory transfer. The
memr_n
signal is
asserted. The state transitions to state S13.
Input Signals:
eopin_n
Asserted Output Signals:
memr_n, address
Possible State Transitions:
S13