Lattice Semiconductor
Multi-Channel DMA Controller User’s Guide
10
Priority Request Encoder
This block prioritizes the DMA request and asserts the
dack
signal for the winning request. In the 8237 mode, the
arbitrating scheme is user programmable and available in either a fixed priority or rotating priority mode. In non-
8237 operation, the arbitrating scheme is restricted to the fixed priority mode.
In the fixed priority mode,
dreq[0]
has the highest priority and
dreq[n]
has the lowest priority. In the 8237 mode,
n (channel number) is fixed to 3 while in the non-8237 mode,
n
is user selectable (up to 16).
The rotating priority mode assigns the lowest priority to the channel that has been serviced most recently. This
mode ensures that all devices will be serviced fairly and prevents any one channel from monopolizing the system.
The maximum wait time for a channel to be serviced is the time taken to service all the other channels.
The main function of this block is to generate the
dack[x]
signal. Each channel has an associated priority register
that indicates the channel’s priority. In the fixed priority mode, the values in these registers will never change, while
in the rotating priority mode, their values change every time a channel is serviced.
DMA Operation
In the non-8237 mode, each channel can be programmed to perform DMA operation between memory locations or
from I/O-to-memory. Each channel has a dedicated source address register that holds the address of the targeted
read memory location and a destination address register, which points to the targeted write memory location.
Memory locations are addressable, but I/O locations are not addressable. The source address register in the non-
8237 mode holds the memory location address during DMA transfers between an I/O device and memory.
Active DMA state four - S4
This is the last stage of the DMA transfer. The
memw_n
or
iowout_n
signal is de-
asserted, depends on the operation (I/O-to-memory or memory-to-I/O). The same
thing happens to the
memr_n
or
iorout_n
signal for only one of them being de-
asserted. The
eopout_n
signal is asserted if the current word register rolls over
from 0xFFFF to 0x0000. This causes the state machine to transition to state SI. If
block or demand transfer mode is selected, the counter has not rolled over, and
DMA hasn’t satisfied the transfer complete-conditions, the state machine transitions
to a state where DMA transfers will continue. This next state depends upon the
mode of operation.
8237 Mode:
The state machine transitions to state S2 as long as the higher order
address remains the same. If the higher order address for the new transfer
changes, the state machine transitions to state S1 to enable the external latch to
update its latched value.
Non-8237 Mode:
The state machine transitions to state S2.
Input Signals:
eopin_n
Asserted Output signals:
eopout_n
Possible State Transitions:
SI, S1, S2
Compressed Timing Mode
This feature is only available in the 8237 mode MCDMA. The purpose of this mode
is to allow MCDMA to achieve greater throughput by compressing the memory-to-
I/O (or I/O-to-memory) transfer time to two clock cycles. In this mode, state S3 is
removed from the state machine. This causes the read pulse-width to equal the
write pulse-width. Thus, the transfer only has state S2 to change the address and
state S4 to perform a read/write operation.
Table 2. State Descriptions (Continued)
State
Description